misched: Added MultiIssueItineraries.

This allows a subtarget to explicitly specify the issue width and
other properties without providing pipeline stage details for every
instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157979 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 86 insertions, 8 deletions

diff --git a/include/llvm/MC/MCInstrItineraries.h b/include/llvm/MC/MCInstrItineraries.h
index e942892da1..199489599e 100644
--- a/include/llvm/MC/MCInstrItineraries.h
+++ b/include/llvm/MC/MCInstrItineraries.h
@@ -104,26 +104,85 @@ struct InstrItinerary {
 
 
 //===----------------------------------------------------------------------===//
+/// Instruction itinerary properties - These properties provide general
+/// information about the microarchitecture to the scheduler.
+///
+struct InstrItineraryProps {
+  // IssueWidth is the maximum number of instructions that may be scheduled in
+  // the same per-cycle group.
+  unsigned IssueWidth;
+
+  // MinLatency is the minimum latency between a register write
+  // followed by a data dependent read. This determines which
+  // instructions may be scheduled in the same per-cycle group. This
+  // is distinct from *expected* latency, which determines the likely
+  // critical path but does not guarantee a pipeline
+  // hazard. MinLatency can always be overridden by the number of
+  // InstrStage cycles.
+  //
+  // (-1) Standard in-order processor.
+  //      Use InstrItinerary OperandCycles as MinLatency.
+  //      If no OperandCycles exist, then use the cycle of the last InstrStage.
+  //
+  //  (0) Out-of-order processor, or in-order with bundled dependencies.
+  //      RAW dependencies may be dispatched in the same cycle.
+  //      Optional InstrItinerary OperandCycles provides expected latency.
+  //
+  // (>0) In-order processor with variable latencies.
+  //      Use the greater of this value or the cycle of the last InstrStage.
+  //      Optional InstrItinerary OperandCycles provides expected latency.
+  //      TODO: can't yet specify both min and expected latency per operand.
+  int MinLatency;
+
+  // LoadLatency is the expected latency of load instructions.
+  //
+  // If MinLatency >= 0, this may be overriden for individual load opcodes by
+  // InstrItinerary OperandCycles.
+  unsigned LoadLatency;
+
+  // HighLatency is the expected latency of "very high latency" operations.
+  // See TargetInstrInfo::isHighLatencyDef().
+  // By default, this is set to an arbitrarily high number of cycles
+  // likely to have some impact on scheduling heuristics.
+  // If MinLatency >= 0, this may be overriden by InstrItinData OperandCycles.
+  unsigned HighLatency;
+
+  InstrItineraryProps(): IssueWidth(1), MinLatency(-1), LoadLatency(4),
+                         HighLatency(10) {}
+
+  InstrItineraryProps(unsigned iw, int ml, unsigned ll, unsigned hl):
+    IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl) {}
+};
+
+//===----------------------------------------------------------------------===//
+/// Encapsulate all subtarget specific information for scheduling for use with
+/// SubtargetInfoKV.
+struct InstrItinerarySubtargetValue {
+  const InstrItineraryProps *Props;
+  const InstrItinerary *Itineraries;
+};
+
+//===----------------------------------------------------------------------===//
 /// Instruction itinerary Data - Itinerary data supplied by a subtarget to be
 /// used by a target.
 ///
 class InstrItineraryData {
 public:
+  InstrItineraryProps Props;
   const InstrStage     *Stages;         ///< Array of stages selected
   const unsigned       *OperandCycles;  ///< Array of operand cycles selected
   const unsigned       *Forwardings;    ///< Array of pipeline forwarding pathes
   const InstrItinerary *Itineraries;    ///< Array of itineraries selected
-  unsigned              IssueWidth;     ///< Max issue per cycle. 0=Unknown.
 
   /// Ctors.
   ///
   InstrItineraryData() : Stages(0), OperandCycles(0), Forwardings(0),
-                         Itineraries(0), IssueWidth(0) {}
+                         Itineraries(0) {}
 
-  InstrItineraryData(const InstrStage *S, const unsigned *OS,
-                     const unsigned *F, const InstrItinerary *I)
-    : Stages(S), OperandCycles(OS), Forwardings(F), Itineraries(I),
-      IssueWidth(0) {}
+  InstrItineraryData(const InstrItineraryProps *P, const InstrStage *S,
+                     const unsigned *OS, const unsigned *F,
+                     const InstrItinerary *I)
+    : Props(*P), Stages(S), OperandCycles(OS), Forwardings(F), Itineraries(I) {}
 
   /// isEmpty - Returns true if there are no itineraries.
   ///
@@ -160,7 +219,7 @@ public:
     // non-zero default value for all instructions.  Some target's provide a
     // dummy (Generic) itinerary which should be handled as if it's itinerary is
     // empty. We identify this by looking for a reference to stage zero (invalid
-    // stage). This is different from beginStage == endState != 0, which could
+    // stage). This is different from beginStage == endStage != 0, which could
     // be used for zero-latency pseudo ops.
     if (isEmpty() || Itineraries[ItinClassIndx].FirstStage == 0)
       return 1;
diff --git a/include/llvm/Target/TargetSchedule.td b/include/llvm/Target/TargetSchedule.td
index 307fe2d6a0..31e8b17f25 100644
--- a/include/llvm/Target/TargetSchedule.td
+++ b/include/llvm/Target/TargetSchedule.td
@@ -117,9 +117,16 @@ class InstrItinData<InstrItinClass Class, list<InstrStage> stages,
 // Processor itineraries - These values represent the set of all itinerary
 // classes for a given chip set.
 //
+// Set property values to -1 to use the default.
+// See InstrItineraryProps for comments and defaults.
 class ProcessorItineraries<list<FuncUnit> fu, list<Bypass> bp,
                            list<InstrItinData> iid> {
-  int IssueWidth = 1;
+  int IssueWidth = -1; // Max instructions that may be scheduled per cycle.
+  int MinLatency = -1; // Determines which instrucions are allowed in a group.
+                       // (-1) inorder (0) ooo, (1): inorder +var latencies.
+  int LoadLatency = -1; // Cycles for loads to access the cache.
+  int HighLatency = -1; // Approximation of cycles for "high latency" ops.
+
   list<FuncUnit> FU = fu;
   list<Bypass> BP = bp;
   list<InstrItinData> IID = iid;
@@ -129,3 +136,15 @@ class ProcessorItineraries<list<FuncUnit> fu, list<Bypass> bp,
 // info.
 def NoItineraries : ProcessorItineraries<[], [], []>;
 
+// Processor itineraries with non-unit issue width. This allows issue
+// width to be explicity specified at the beginning of the itinerary.
+class MultiIssueItineraries<int issuewidth, int minlatency,
+                            int loadlatency, int highlatency,
+                            list<FuncUnit> fu, list<Bypass> bp,
+                            list<InstrItinData> iid>
+  : ProcessorItineraries<fu, bp, iid> {
+  let IssueWidth = issuewidth;
+  let MinLatency = minlatency;
+  let LoadLatency = loadlatency;
+  let HighLatency = highlatency;
+}