aboutsummaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
authorEvan Cheng <evan.cheng@apple.com>2009-11-21 06:20:26 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-11-21 06:20:26 +0000
commite54cb16308ad40d0f0b257de47efaa0ee5a47004 (patch)
tree3e3b83a8c49d3ff9c9bbc27b3576213a2fc6bcf3 /include
parent2c4ceb177be718a7a3697ea63aa254719fc3528f (diff)
Allow target to disable if-converting predicable instructions. e.g. NEON instructions under ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89541 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r--include/llvm/Target/TargetInstrInfo.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index 43fd54e183..72ebe3cafa 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -514,6 +514,13 @@ public:
return false;
}
+ /// isPredicable - Return true if the specified instruction can be predicated.
+ /// By default, this returns true for every instruction with a
+ /// PredicateOperand.
+ virtual bool isPredicable(MachineInstr *MI) const {
+ return MI->getDesc().isPredicable();
+ }
+
/// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
/// instruction that defines the specified register class.
virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {