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authorJakob Stoklund Olesen <stoklund@2pi.dk>2012-05-04 03:30:34 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2012-05-04 03:30:34 +0000
commit338607ae0ddab00e197222e769748e2e0c0b4e18 (patch)
treeae0cdec113d5fb087b1bf0eccaecfdfae2432542 /include
parent7855ec62c3b6b5b7e6d3fada589511abd964fdb3 (diff)
Remove the SubRegClasses field from RegisterClass descriptions.
This information in now computed by TableGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156152 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
-rw-r--r--include/llvm/Target/Target.td4
1 files changed, 0 insertions, 4 deletions
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index cf87fb157c..bd959d067f 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -151,10 +151,6 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
// a valid alternate name for the given index.
RegAltNameIndex altNameIndex = idx;
- // SubRegClasses - Specify the register class of subregisters as a list of
- // dags: (RegClass SubRegIndex, SubRegindex, ...)
- list<dag> SubRegClasses = [];
-
// isAllocatable - Specify that the register class can be used for virtual
// registers and register allocation. Some register classes are only used to
// model instruction operand constraints, and should have isAllocatable = 0.