Introducing plugable register allocators and instruction schedulers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29434 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 17 insertions, 84 deletions

diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h
index 870d48af94..1146c327a6 100644
--- a/include/llvm/CodeGen/ScheduleDAG.h
+++ b/include/llvm/CodeGen/ScheduleDAG.h
@@ -221,29 +221,35 @@ namespace llvm {
                     std::map<SDNode*, unsigned> &VRBaseMap);
   };
 
-  ScheduleDAG *createBFS_DAGScheduler(SelectionDAG &DAG, MachineBasicBlock *BB);
+  /// createBFS_DAGScheduler - This creates a simple breadth first instruction
+  /// scheduler.
+  ScheduleDAG *createBFS_DAGScheduler(SelectionDAG *DAG, MachineBasicBlock *BB);
   
   /// createSimpleDAGScheduler - This creates a simple two pass instruction
-  /// scheduler.
-  ScheduleDAG* createSimpleDAGScheduler(bool NoItins, SelectionDAG &DAG,
+  /// scheduler using instruction itinerary.
+  ScheduleDAG* createSimpleDAGScheduler(SelectionDAG *DAG,
                                         MachineBasicBlock *BB);
 
+  /// createNoItinsDAGScheduler - This creates a simple two pass instruction
+  /// scheduler without using instruction itinerary.
+  ScheduleDAG* createNoItinsDAGScheduler(SelectionDAG *DAG,
+                                         MachineBasicBlock *BB);
+
   /// createBURRListDAGScheduler - This creates a bottom up register usage
   /// reduction list scheduler.
-  ScheduleDAG* createBURRListDAGScheduler(SelectionDAG &DAG,
+  ScheduleDAG* createBURRListDAGScheduler(SelectionDAG *DAG,
                                           MachineBasicBlock *BB);
   
   /// createTDRRListDAGScheduler - This creates a top down register usage
   /// reduction list scheduler.
-  ScheduleDAG* createTDRRListDAGScheduler(SelectionDAG &DAG,
+  ScheduleDAG* createTDRRListDAGScheduler(SelectionDAG *DAG,
                                           MachineBasicBlock *BB);
   
   /// createTDListDAGScheduler - This creates a top-down list scheduler with
-  /// the specified hazard recognizer.  This takes ownership of the hazard
-  /// recognizer and deletes it when done.
-  ScheduleDAG* createTDListDAGScheduler(SelectionDAG &DAG,
-                                        MachineBasicBlock *BB,
-                                        HazardRecognizer *HR);
+  /// a hazard recognizer.
+  ScheduleDAG* createTDListDAGScheduler(SelectionDAG *DAG,
+                                        MachineBasicBlock *BB);
+                                        
 }
 
 #endif
diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h
index 78179c9e2a..cd8e5f4989 100644
--- a/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/include/llvm/CodeGen/SelectionDAGISel.h
@@ -67,10 +67,6 @@ public:
   /// folded during instruction selection?
   virtual bool CanBeFoldedBy(SDNode *N, SDNode *U) { return true; }
   
-  /// CreateTargetHazardRecognizer - Return a newly allocated hazard recognizer
-  /// to use for this target when scheduling the DAG.
-  virtual HazardRecognizer *CreateTargetHazardRecognizer();
-  
   /// CaseBlock - This structure is used to communicate between SDLowering and
   /// SDISel for the code generation of additional basic blocks needed by multi-
   /// case switch statements.
diff --git a/include/llvm/PassSupport.h b/include/llvm/PassSupport.h
index a33b166d5b..c802fe2f0d 100644
--- a/include/llvm/PassSupport.h
+++ b/include/llvm/PassSupport.h
@@ -369,75 +369,6 @@ struct PassRegistrationListener {
 };
 
 
-//===---------------------------------------------------------------------===//
-///
-/// RegisterRegAlloc class - Track the registration of register allocators.
-///
-class RegisterRegAlloc {
-
-public:
-
-  typedef FunctionPass *(*FunctionPassCtor)();
-
-private:
-
-  static RegisterRegAlloc *List;        // Linked list of register allocators.
-  
-  RegisterRegAlloc *Next;               // Next allocation scheme in list.
-  const char *Name;                     // Name of register allocator.
-  const char *Description;              // Description string.
-  FunctionPassCtor Ctor;                // Function to construct register
-                                        // allocator pass.
-public:
-
-  RegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
-  : Name(N)
-  , Description(D)
-  , Ctor(C) {
-    Add();
-  }
-  
-  ~RegisterRegAlloc() {
-    Remove();
-  }
-  
-  
-  // Accessors
-  const char *getName()        const { return Name; }
-  const char *getDescription() const { return Description; }
-  FunctionPassCtor getCtor()   const { return Ctor; }
-  
-  
-  /// Add - Adds a register allocator to the registration list.
-  ///
-  void Add() {
-    Next = List;
-    List = this;
-  }
-  
-
-  /// Remove - Removes a register allocator from the registration list.
-  ///
-  void Remove() {
-    for (RegisterRegAlloc **RA = &List; *RA; RA = &(*RA)->Next) {
-      if (*RA == this) {
-        *RA = Next;
-        break;
-      }
-    }
-  }
-  
-  
-  /// Find - Finds a register allocator in registration list.
-  ///
-  static FunctionPassCtor Find(const char *N);
-
-#ifndef NDEBUG  
-  static void print();
-#endif
-};
-
-
 } // End llvm namespace
 
 #endif
diff --git a/include/llvm/Transforms/LinkAllPasses.h b/include/llvm/Transforms/LinkAllPasses.h
index cb83dadc4f..3a9c504155 100644
--- a/include/llvm/Transforms/LinkAllPasses.h
+++ b/include/llvm/Transforms/LinkAllPasses.h
@@ -110,7 +110,7 @@ namespace {
       (void) llvm::createRSProfilingPass();
       (void) llvm::createIndMemRemPass();
     }
-  } ForcePassLinking;
+  } ForcePassLinking; // Force link by creating a global definition.
 }
 
 #endif