diff options
| author | Andrew Trick <atrick@apple.com> | 2013-01-09 03:36:49 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2013-01-09 03:36:49 +0000 |
| commit | 47579cf390c42e0577519e0a2b6044baece9df00 (patch) | |
| tree | 2744c5de5c5c825a168a20f90b9e099d8feaaf88 /include/llvm/Target | |
| parent | 2af949ddddfaf2feb4a446c754e09d2d8c207ce4 (diff) | |
MIsched: add an ILP window property to machine model.
This was an experimental option, but needs to be defined
per-target. e.g. PPC A2 needs to aggressively hide latency.
I converted some in-order scheduling tests to A2. Hal is working on
more test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171946 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/Target')
| -rw-r--r-- | include/llvm/Target/TargetSchedule.td | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/llvm/Target/TargetSchedule.td b/include/llvm/Target/TargetSchedule.td index 0da82fdd89..b7920bae8a 100644 --- a/include/llvm/Target/TargetSchedule.td +++ b/include/llvm/Target/TargetSchedule.td @@ -76,6 +76,7 @@ class SchedMachineModel { int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle. int MinLatency = -1; // Determines which instrucions are allowed in a group. // (-1) inorder (0) ooo, (1): inorder +var latencies. + int ILPWindow = -1; // Cycles of latency likely hidden by hardware buffers. int LoadLatency = -1; // Cycles for loads to access the cache. int HighLatency = -1; // Approximation of cycles for "high latency" ops. int MispredictPenalty = -1; // Extra cycles for a mispredicted branch. |