Add versions of OutputArgReg, AnalyzeReturn, and AnalyzeCallOperands

which do not depend on SelectionDAG.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107666 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 21 insertions, 0 deletions

diff --git a/include/llvm/CodeGen/CallingConvLower.h b/include/llvm/CodeGen/CallingConvLower.h
index 0e60c963c0..71b246c0c9 100644
--- a/include/llvm/CodeGen/CallingConvLower.h
+++ b/include/llvm/CodeGen/CallingConvLower.h
@@ -185,6 +185,8 @@ public:
   /// incorporating info about the result values into this state.
   void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
                      CCAssignFn Fn);
+  void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArgReg> &Outs,
+                     CCAssignFn Fn);
 
   /// CheckReturn - Analyze the return values of a function, returning
   /// true if the return can be performed without sret-demotion, and
@@ -197,6 +199,8 @@ public:
   /// incorporating info about the passed values into this state.
   void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
                            CCAssignFn Fn);
+  void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArgReg> &Outs,
+                           CCAssignFn Fn);
 
   /// AnalyzeCallOperands - Same as above except it takes vectors of types
   /// and argument flags.
diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index 7b8c1dcfb8..bceb17bcbd 100644
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -1583,6 +1583,23 @@ namespace ISD {
              "OutputArg value type must be Simple!");
     }
   };
+
+  /// OutputArgReg - This struct carries flags and a register value for a
+  /// single outgoing (actual) argument or outgoing (from the perspective
+  /// of the caller) return value virtual register.
+  ///
+  struct OutputArgReg {
+    ArgFlagsTy Flags;
+    EVT VT;
+    unsigned Reg;
+
+    /// IsFixed - Is this a "fixed" value, ie not passed through a vararg "...".
+    bool IsFixed;
+
+    OutputArgReg() : IsFixed(false) {}
+    OutputArgReg(ISD::ArgFlagsTy flags, EVT vt, unsigned reg, bool isfixed)
+      : Flags(flags), VT(vt), Reg(reg), IsFixed(isfixed) {}
+  };
 }
 
 /// VTSDNode - This class is used to represent EVT's, which are used