rename TargetInstrDescriptor -> TargetInstrDesc.

Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 17 insertions, 17 deletions

diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h
index 5450e839db..72463f98d8 100644
--- a/include/llvm/CodeGen/MachineInstr.h
+++ b/include/llvm/CodeGen/MachineInstr.h
@@ -20,7 +20,7 @@
 
 namespace llvm {
 
-class TargetInstrDescriptor;
+class TargetInstrDesc;
 
 template <typename T> struct ilist_traits;
 template <typename T> struct ilist;
@@ -29,7 +29,7 @@ template <typename T> struct ilist;
 /// MachineInstr - Representation of each machine instruction.
 ///
 class MachineInstr {
-  const TargetInstrDescriptor *TID;     // Instruction descriptor.
+  const TargetInstrDesc *TID;           // Instruction descriptor.
   unsigned short NumImplicitOps;        // Number of implicit operands (which
                                         // are determined at construction time).
 
@@ -54,14 +54,14 @@ public:
 
   /// MachineInstr ctor - This constructor create a MachineInstr and add the
   /// implicit operands.  It reserves space for number of operands specified by
-  /// TargetInstrDescriptor.
-  explicit MachineInstr(const TargetInstrDescriptor &TID, bool NoImp = false);
+  /// TargetInstrDesc.
+  explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
 
   /// MachineInstr ctor - Work exactly the same as the ctor above, except that
   /// the MachineInstr is created and added to the end of the specified basic
   /// block.
   ///
-  MachineInstr(MachineBasicBlock *MBB, const TargetInstrDescriptor &TID);
+  MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
 
   ~MachineInstr();
 
@@ -70,7 +70,7 @@ public:
   
   /// getDesc - Returns the target instruction descriptor of this
   /// MachineInstr.
-  const TargetInstrDescriptor *getDesc() const { return TID; }
+  const TargetInstrDesc &getDesc() const { return *TID; }
 
   /// getOpcode - Returns the opcode of this MachineInstr.
   ///
@@ -166,7 +166,7 @@ public:
   /// setInstrDescriptor - Replace the instruction descriptor (thus opcode) of
   /// the current instruction with a new one.
   ///
-  void setInstrDescriptor(const TargetInstrDescriptor &tid) { TID = &tid; }
+  void setInstrDescriptor(const TargetInstrDesc &tid) { TID = &tid; }
 
   /// RemoveOperand - Erase an operand  from an instruction, leaving it with one
   /// fewer operand than it started with.
diff --git a/include/llvm/CodeGen/MachineInstrBuilder.h b/include/llvm/CodeGen/MachineInstrBuilder.h
index 91c4ad9ac1..97d6736ac0 100644
--- a/include/llvm/CodeGen/MachineInstrBuilder.h
+++ b/include/llvm/CodeGen/MachineInstrBuilder.h
@@ -22,7 +22,7 @@
 
 namespace llvm {
 
-class TargetInstrDescriptor;
+class TargetInstrDesc;
 
 class MachineInstrBuilder {
   MachineInstr *MI;
@@ -88,14 +88,14 @@ public:
 /// BuildMI - Builder interface.  Specify how to create the initial instruction
 /// itself.
 ///
-inline MachineInstrBuilder BuildMI(const TargetInstrDescriptor &TID) {
+inline MachineInstrBuilder BuildMI(const TargetInstrDesc &TID) {
   return MachineInstrBuilder(new MachineInstr(TID));
 }
 
 /// BuildMI - This version of the builder sets up the first operand as a
 /// destination virtual register.
 ///
-inline MachineInstrBuilder  BuildMI(const TargetInstrDescriptor &TID,
+inline MachineInstrBuilder  BuildMI(const TargetInstrDesc &TID,
                                     unsigned DestReg) {
   return MachineInstrBuilder(new MachineInstr(TID)).addReg(DestReg, true);
 }
@@ -106,7 +106,7 @@ inline MachineInstrBuilder  BuildMI(const TargetInstrDescriptor &TID,
 ///
 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                                    MachineBasicBlock::iterator I,
-                                   const TargetInstrDescriptor &TID,
+                                   const TargetInstrDesc &TID,
                                    unsigned DestReg) {
   MachineInstr *MI = new MachineInstr(TID);
   BB.insert(I, MI);
@@ -119,7 +119,7 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
 ///
 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
                                    MachineBasicBlock::iterator I,
-                                   const TargetInstrDescriptor &TID) {
+                                   const TargetInstrDesc &TID) {
   MachineInstr *MI = new MachineInstr(TID);
   BB.insert(I, MI);
   return MachineInstrBuilder(MI);
@@ -130,7 +130,7 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
 /// destination register.
 ///
 inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
-                                   const TargetInstrDescriptor &TID) {
+                                   const TargetInstrDesc &TID) {
   return BuildMI(*BB, BB->end(), TID);
 }
 
@@ -139,7 +139,7 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
 /// operand as a destination virtual register. 
 ///
 inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
-                                   const TargetInstrDescriptor &TID,
+                                   const TargetInstrDesc &TID,
                                    unsigned DestReg) {
   return BuildMI(*BB, BB->end(), TID, DestReg);
 }
diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h
index a07d0e9482..37c0a9032a 100644
--- a/include/llvm/CodeGen/ScheduleDAG.h
+++ b/include/llvm/CodeGen/ScheduleDAG.h
@@ -31,7 +31,7 @@ namespace llvm {
   class SelectionDAG;
   class SelectionDAGISel;
   class TargetInstrInfo;
-  class TargetInstrDescriptor;
+  class TargetInstrDesc;
   class TargetMachine;
   class TargetRegisterClass;
 
@@ -335,7 +335,7 @@ namespace llvm {
                          DenseMap<SDOperand, unsigned> &VRBaseMap);
     
     void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
-                                const TargetInstrDescriptor &II,
+                                const TargetInstrDesc &II,
                                 DenseMap<SDOperand, unsigned> &VRBaseMap);
 
     void EmitSchedule();
@@ -353,7 +353,7 @@ namespace llvm {
                         DenseMap<SDOperand, unsigned> &VRBaseMap);
   
     void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum,
-                    const TargetInstrDescriptor *II,
+                    const TargetInstrDesc *II,
                     DenseMap<SDOperand, unsigned> &VRBaseMap);
   };