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authorEvan Cheng <evan.cheng@apple.com>2008-07-12 01:38:51 +0000
committerEvan Cheng <evan.cheng@apple.com>2008-07-12 01:38:51 +0000
commitb5eec33dcde63bee6048d54bee2a376737028e5c (patch)
treee9de0819027f1757bd38661c5abd492a80fe9ddf /include/llvm/CodeGen/SelectionDAGISel.h
parentcddc11e7570893233af8e84dfb8e7f0f9ab0090d (diff)
Back out 53476 and 53480 for now. Somehow they cause llc to miscompile 179.art.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53502 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/CodeGen/SelectionDAGISel.h')
-rw-r--r--include/llvm/CodeGen/SelectionDAGISel.h5
1 files changed, 2 insertions, 3 deletions
diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h
index 72a836f55b..e0b26b926b 100644
--- a/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/include/llvm/CodeGen/SelectionDAGISel.h
@@ -30,7 +30,6 @@ namespace llvm {
class FunctionLoweringInfo;
class HazardRecognizer;
class CollectorMetadata;
- class ScheduleDAG;
/// SelectionDAGISel - This is the common base class used for SelectionDAG-based
/// pattern-matching instruction selectors.
@@ -192,9 +191,9 @@ private:
void ComputeLiveOutVRegInfo(SelectionDAG &DAG);
- /// Pick a safe ordering for instructions for each target node in the
+ /// Pick a safe ordering and emit instructions for each target node in the
/// graph.
- ScheduleDAG *Schedule(SelectionDAG &DAG);
+ void ScheduleAndEmitDAG(SelectionDAG &DAG);
/// SwitchCases - Vector of CaseBlock structures used to communicate
/// SwitchInst code generation information.