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authorDerek Schuff <dschuff@chromium.org>2013-01-30 11:34:40 -0800
committerDerek Schuff <dschuff@chromium.org>2013-01-30 11:34:40 -0800
commit1843e19bce9b11fc840858e136c6c52cf8b42e0b (patch)
treee8bfc928152e2d3b3dd120d141d13dc08a9b49e4 /include/llvm/CodeGen/MachineOperand.h
parentaa0fa8a8df25807f784ec9ca9deeb40328636595 (diff)
parenta662a9862501fc86904e90054f7c1519101d9126 (diff)
Merge commit 'a662a9862501fc86904e90054f7c1519101d9126'
Conflicts: include/llvm/CodeGen/IntrinsicLowering.h include/llvm/MC/MCAssembler.h include/llvm/MC/MCObjectStreamer.h lib/LLVMBuild.txt lib/Linker/LinkArchives.cpp lib/MC/MCAssembler.cpp lib/MC/MCELFStreamer.cpp lib/MC/MCParser/AsmParser.cpp lib/MC/MCPureStreamer.cpp lib/MC/WinCOFFStreamer.cpp lib/Makefile lib/Support/Unix/Memory.inc lib/Support/Unix/Process.inc lib/Support/Unix/Program.inc lib/Target/ARM/ARM.h lib/Target/ARM/ARMFastISel.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp lib/Target/Mips/MipsInstrFPU.td lib/Target/X86/CMakeLists.txt lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86TargetMachine.cpp lib/Target/X86/X86TargetObjectFile.cpp lib/Transforms/InstCombine/InstCombineCalls.cpp test/CodeGen/X86/fast-isel-x86-64.ll tools/llc/llc.cpp tools/lto/LTOModule.cpp utils/TableGen/EDEmitter.cpp
Diffstat (limited to 'include/llvm/CodeGen/MachineOperand.h')
-rw-r--r--include/llvm/CodeGen/MachineOperand.h45
1 files changed, 24 insertions, 21 deletions
diff --git a/include/llvm/CodeGen/MachineOperand.h b/include/llvm/CodeGen/MachineOperand.h
index 606833cd40..414770b9ec 100644
--- a/include/llvm/CodeGen/MachineOperand.h
+++ b/include/llvm/CodeGen/MachineOperand.h
@@ -35,6 +35,11 @@ class MCSymbol;
/// MachineOperand class - Representation of each machine instruction operand.
///
+/// This class isn't a POD type because it has a private constructor, but its
+/// destructor must be trivial. Functions like MachineInstr::addOperand(),
+/// MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on
+/// not having to call the MachineOperand destructor.
+///
class MachineOperand {
public:
enum MachineOperandType {
@@ -60,15 +65,11 @@ private:
/// union.
unsigned char OpKind; // MachineOperandType
- // This union is discriminated by OpKind.
- union {
- /// SubReg - Subregister number, only valid for MO_Register. A value of 0
- /// indicates the MO_Register has no subReg.
- unsigned char SubReg;
-
- /// TargetFlags - This is a set of target-specific operand flags.
- unsigned char TargetFlags;
- };
+ /// Subregister number for MO_Register. A value of 0 indicates the
+ /// MO_Register has no subReg.
+ ///
+ /// For all other kinds of operands, this field holds target-specific flags.
+ unsigned SubReg_TargetFlags : 12;
/// TiedTo - Non-zero when this register operand is tied to another register
/// operand. The encoding of this field is described in the block comment
@@ -176,24 +177,25 @@ private:
} OffsetedInfo;
} Contents;
- explicit MachineOperand(MachineOperandType K) : OpKind(K), ParentMI(0) {
- TargetFlags = 0;
- }
+ explicit MachineOperand(MachineOperandType K)
+ : OpKind(K), SubReg_TargetFlags(0), ParentMI(0) {}
public:
/// getType - Returns the MachineOperandType for this operand.
///
MachineOperandType getType() const { return (MachineOperandType)OpKind; }
- unsigned char getTargetFlags() const {
- return isReg() ? 0 : TargetFlags;
+ unsigned getTargetFlags() const {
+ return isReg() ? 0 : SubReg_TargetFlags;
}
- void setTargetFlags(unsigned char F) {
+ void setTargetFlags(unsigned F) {
assert(!isReg() && "Register operands can't have target flags");
- TargetFlags = F;
+ SubReg_TargetFlags = F;
+ assert(SubReg_TargetFlags == F && "Target flags out of range");
}
- void addTargetFlag(unsigned char F) {
+ void addTargetFlag(unsigned F) {
assert(!isReg() && "Register operands can't have target flags");
- TargetFlags |= F;
+ SubReg_TargetFlags |= F;
+ assert((SubReg_TargetFlags & F) && "Target flags out of range");
}
@@ -261,7 +263,7 @@ public:
unsigned getSubReg() const {
assert(isReg() && "Wrong MachineOperand accessor");
- return (unsigned)SubReg;
+ return SubReg_TargetFlags;
}
bool isUse() const {
@@ -336,7 +338,8 @@ public:
void setSubReg(unsigned subReg) {
assert(isReg() && "Wrong MachineOperand accessor");
- SubReg = (unsigned char)subReg;
+ SubReg_TargetFlags = subReg;
+ assert(SubReg_TargetFlags == subReg && "SubReg out of range");
}
/// substVirtReg - Substitute the current register with the virtual
@@ -574,7 +577,7 @@ public:
Op.SmallContents.RegNo = Reg;
Op.Contents.Reg.Prev = 0;
Op.Contents.Reg.Next = 0;
- Op.SubReg = SubReg;
+ Op.setSubReg(SubReg);
return Op;
}
static MachineOperand CreateMBB(MachineBasicBlock *MBB,