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authorDale Johannesen <dalej@apple.com>2008-09-19 01:02:35 +0000
committerDale Johannesen <dalej@apple.com>2008-09-19 01:02:35 +0000
commitfa48f941304f29f967e0a7fc6807d7026ba99b7b (patch)
treea8f9875394aebdba26f7d1b2f886ead96f181e1f /include/llvm/CodeGen/LiveInterval.h
parent4fe0fe8b493437e91f8510b81462ff39f0d889ca (diff)
Remove AsmThatEarlyClobber etc. from LiveIntervalAnalysis
and redo as linked list walk. Logic moved into RA. Per review feedback. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56326 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/llvm/CodeGen/LiveInterval.h')
-rw-r--r--include/llvm/CodeGen/LiveInterval.h9
1 files changed, 7 insertions, 2 deletions
diff --git a/include/llvm/CodeGen/LiveInterval.h b/include/llvm/CodeGen/LiveInterval.h
index 5e5e4b1957..8b9eb530ad 100644
--- a/include/llvm/CodeGen/LiveInterval.h
+++ b/include/llvm/CodeGen/LiveInterval.h
@@ -105,12 +105,17 @@ namespace llvm {
// if the top bits is set, it represents a stack slot.
unsigned preference; // preferred register to allocate for this interval
float weight; // weight of this interval
+ bool isEarlyClobber;
+ bool overlapsEarlyClobber;
Ranges ranges; // the ranges in which this register is live
VNInfoList valnos; // value#'s
public:
- LiveInterval(unsigned Reg, float Weight, bool IsSS = false)
- : reg(Reg), preference(0), weight(Weight) {
+ LiveInterval(unsigned Reg, float Weight, bool IsSS = false,
+ bool IsEarlyClobber = false, bool OverlapsEarlyClobber = false)
+ : reg(Reg), preference(0), weight(Weight),
+ isEarlyClobber(IsEarlyClobber),
+ overlapsEarlyClobber(OverlapsEarlyClobber) {
if (IsSS)
reg = reg | (1U << (sizeof(unsigned)*8-1));
}