Next round of earlyclobber handling. Approach the

RA problem by expanding the live interval of an
earlyclobber def back one slot.  Remove
overlap-earlyclobber throughout.  Remove 
earlyclobber bits and their handling from
live internals.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56539 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 2 insertions, 8 deletions

diff --git a/include/llvm/CodeGen/LiveInterval.h b/include/llvm/CodeGen/LiveInterval.h
index b346787bd9..0d5acb8392 100644
--- a/include/llvm/CodeGen/LiveInterval.h
+++ b/include/llvm/CodeGen/LiveInterval.h
@@ -104,19 +104,13 @@ namespace llvm {
     unsigned reg;        // the register or stack slot of this interval
                          // if the top bits is set, it represents a stack slot.
     float weight;        // weight of this interval
-    // The next 3 fields pack into a single word (on most hosts).
-    // Logically the first two could be bitfields, but that's slower.
-    bool isEarlyClobber;  // marked earlyclobber in some asm
-    bool overlapsEarlyClobber; // input to asm that has an earlyclobber
     unsigned short preference; // preferred register for this interval
     Ranges ranges;       // the ranges in which this register is live
     VNInfoList valnos;   // value#'s
 
   public:
-    LiveInterval(unsigned Reg, float Weight, bool IsSS = false, 
-                 bool IsEarlyClobber = false, bool OverlapsEarlyClobber = false)
-      : reg(Reg), weight(Weight), isEarlyClobber(IsEarlyClobber), 
-        overlapsEarlyClobber(OverlapsEarlyClobber), preference(0)  {
+    LiveInterval(unsigned Reg, float Weight, bool IsSS = false)
+      : reg(Reg), weight(Weight), preference(0)  {
       if (IsSS)
         reg = reg | (1U << (sizeof(unsigned)*8-1));
     }