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author | Jakub Staszak <kubastaszak@gmail.com> | 2012-04-15 20:13:47 +0000 |
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committer | Jakub Staszak <kubastaszak@gmail.com> | 2012-04-15 20:13:47 +0000 |
commit | 00920f68a42251b5bde8537a78bd55f33615b441 (patch) | |
tree | eb4117305c033839f564139caea8a6083dbeaff8 /docs/CodeGenerator.html | |
parent | f16af0a05358c953fe9a8c2fbb0cf892b940ece9 (diff) |
Fix filename and register numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154771 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'docs/CodeGenerator.html')
-rw-r--r-- | docs/CodeGenerator.html | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html index 77bd625a4e..313874e40a 100644 --- a/docs/CodeGenerator.html +++ b/docs/CodeGenerator.html @@ -1617,9 +1617,9 @@ def : Pat<(i32 imm:$imm), range from 1 to 1023. To see how this numbering is defined for a particular architecture, you can read the <tt>GenRegisterNames.inc</tt> file for that architecture. For instance, by - inspecting <tt>lib/Target/X86/X86GenRegisterNames.inc</tt> we see that the - 32-bit register <tt>EAX</tt> is denoted by 15, and the MMX register - <tt>MM0</tt> is mapped to 48.</p> + inspecting <tt>lib/Target/X86/X86GenRegisterInfo.inc</tt> we see that the + 32-bit register <tt>EAX</tt> is denoted by 43, and the MMX register + <tt>MM0</tt> is mapped to 65.</p> <p>Some architectures contain registers that share the same physical location. A notable example is the X86 platform. For instance, in the X86 architecture, |