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| author | Craig Topper <craig.topper@gmail.com> | 2012-01-13 05:04:25 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-01-13 05:04:25 +0000 |
| commit | e6cf4a070d41d19c133b8713dafa91e51a198e60 (patch) | |
| tree | 5b4a191e21791ea74a133ce754197a2b579752ab | |
| parent | 8dd6f0c8353f80de6526810899f271d539f6929c (diff) | |
Fix typo in PerformAddCombine that caused any vector type to be checked for horizontal add/sub if AVX2 is enabled. This caused an assert to fail for non 128/256-bit vectors when done before type legalizing. Fixes PR11749.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148096 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 6a5e6f5f24..a6f22fafee 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -14575,7 +14575,7 @@ static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG, // Try to synthesize horizontal adds from adds of shuffles. if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) || - (Subtarget->hasAVX2() && (VT == MVT::v16i16 || MVT::v8i32))) && + (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) && isHorizontalBinOp(Op0, Op1, true)) return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1); |