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| author | Matt Beaumont-Gay <matthewbg@google.com> | 2011-03-22 00:37:28 +0000 |
|---|---|---|
| committer | Matt Beaumont-Gay <matthewbg@google.com> | 2011-03-22 00:37:28 +0000 |
| commit | ddb657c63dd0865c13cf677484b59fc5f9758d1b (patch) | |
| tree | feab6ed87fecdffb6de4ebfa4fca5385438adcf1 | |
| parent | e17232ee4de2f608f0e5d965368c2bc54b6c1e83 (diff) | |
Avoid -Wunused-variable in -asserts builds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128048 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h index da4faf4971..b9cafeb831 100644 --- a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h +++ b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h @@ -607,11 +607,6 @@ static bool DisassembleThumb1LdSt(unsigned opA, MCInst &MI, unsigned Opcode, const TargetOperandInfo *OpInfo = TID.OpInfo; unsigned &OpIdx = NumOpsAdded; - // Table A6-5 16-bit Thumb Load/store instructions - // opA = 0b0101 for STR/LDR (register) and friends. - // Otherwise, we have STR/LDR (immediate) and friends. - bool Imm5 = (opA != 5); - assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID && OpInfo[1].RegClass == ARM::tGPRRegClassID @@ -632,7 +627,10 @@ static bool DisassembleThumb1LdSt(unsigned opA, MCInst &MI, unsigned Opcode, if (OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) { - assert(Imm5 && "Immediate operand expected for this opcode"); + // Table A6-5 16-bit Thumb Load/store instructions + // opA = 0b0101 for STR/LDR (register) and friends. + // Otherwise, we have STR/LDR (immediate) and friends. + assert(opA != 5 && "Immediate operand expected for this opcode"); MI.addOperand(MCOperand::CreateImm(getT1Imm5(insn))); ++OpIdx; } else { |