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authorEvan Cheng <evan.cheng@apple.com>2006-01-06 01:06:31 +0000
committerEvan Cheng <evan.cheng@apple.com>2006-01-06 01:06:31 +0000
commitda95a84a11e684072ea25fbb9830e769039fd985 (patch)
tree023a6eed0ee8c3e06bc2eaff95441d072fe9d837
parenta35ef6350defdc09eb912c52603cffa6afbd78e2 (diff)
fold (shl x, 1) -> (add x, x)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25120 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp3
-rw-r--r--lib/Target/X86/X86ISelDAGToDAG.cpp20
2 files changed, 3 insertions, 20 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 30a4c9f637..9770ae232b 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1282,6 +1282,9 @@ SDOperand DAGCombiner::visitSHL(SDNode *N) {
// fold (shl x, 0) -> x
if (N1C && N1C->isNullValue())
return N0;
+ // fold (shl x, 1) -> (add x, x)
+ if (N1C && N1C->getValue() == 1)
+ return DAG.getNode(ISD::ADD, VT, N0, N0);
// if (shl x, c) is known to be zero, return 0
if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
return DAG.getConstant(0, VT);
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 1a926d076e..437519c3f1 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -363,26 +363,6 @@ SDOperand X86DAGToDAGISel::Select(SDOperand N) {
switch (Node->getOpcode()) {
default: break;
- case ISD::SHL:
- if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node->getOperand(1))) {
- if (CN->getValue() == 1) {
- // X = SHL Y, 1 -> X = ADD Y, Y
- switch (NVT) {
- default: assert(0 && "Cannot shift this type!");
- case MVT::i8: Opc = X86::ADD8rr; break;
- case MVT::i16: Opc = X86::ADD16rr; break;
- case MVT::i32: Opc = X86::ADD32rr; break;
- }
- SDOperand Tmp0 = Select(Node->getOperand(0));
- if (Node->hasOneUse())
- return CurDAG->SelectNodeTo(Node, Opc, NVT, Tmp0, Tmp0);
- else
- return CodeGenMap[N] =
- CurDAG->getTargetNode(Opc, NVT, Tmp0, Tmp0);
- }
- }
- break;
-
case ISD::TRUNCATE: {
unsigned Reg;
MVT::ValueType VT;