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authorChris Lattner <sabre@nondot.org>2005-01-19 03:36:14 +0000
committerChris Lattner <sabre@nondot.org>2005-01-19 03:36:14 +0000
commitd6e496732b9cc2c4b4986d015c7dba9032aaa14c (patch)
tree38fef99d836db37bd1de88c85f1315322648e00a
parent6147a7aa17b40f457f073689481fed2ff9ef4819 (diff)
Add a hook to find out how the target handles shift amounts that are out of
range. Either they are undefined (the default), they mask the shift amount to the size of the register (X86, Alpha, etc), or they extend the shift (PPC). This defaults to undefined, which is conservatively correct. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19677 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/CodeGen/SelectionDAG/TargetLowering.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index dd8c084a59..206a806574 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -25,6 +25,7 @@ TargetLowering::TargetLowering(TargetMachine &tm)
IsLittleEndian = TD.isLittleEndian();
ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD.getIntPtrType());
+ ShiftAmtHandling = Undefined;
memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
}