Some cheap DAG combine goodness for multiplication with a particular constant.

This can be extended later on to handle more "complex" constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103881 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 101 insertions, 4 deletions

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 49dd9514b5..1e415d15f8 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -463,6 +463,7 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
   // ARMISD::VMOVRRD  - No need to call setTargetDAGCombine
   setTargetDAGCombine(ISD::ADD);
   setTargetDAGCombine(ISD::SUB);
+  setTargetDAGCombine(ISD::MUL);
 
   setStackPointerRegisterToSaveRestore(ARM::SP);
   setSchedulingPreference(SchedulingForRegPressure);
@@ -3584,6 +3585,75 @@ static SDValue PerformSUBCombine(SDNode *N,
   return SDValue();
 }
 
+static SDValue PerformMULCombine(SDNode *N,
+                                 TargetLowering::DAGCombinerInfo &DCI,
+                                 const ARMSubtarget *Subtarget) {
+  SelectionDAG &DAG = DCI.DAG;
+
+  if (Subtarget->isThumb1Only())
+    return SDValue();
+
+  if (DAG.getMachineFunction().
+      getFunction()->hasFnAttr(Attribute::OptimizeForSize))
+    return SDValue();
+
+  if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
+    return SDValue();
+
+  EVT VT = N->getValueType(0);
+  if (VT != MVT::i32)
+    return SDValue();
+
+  ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
+  if (!C)
+    return SDValue();
+
+  uint64_t MulAmt = C->getZExtValue();
+  unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
+  ShiftAmt = ShiftAmt & (32 - 1);
+  SDValue V = N->getOperand(0);
+  DebugLoc DL = N->getDebugLoc();
+  SDValue NewAdd;
+
+  // FIXME: Handle arbitrary powers of 2.
+  switch (MulAmt >> ShiftAmt) {
+  case 3: // 2 + 1
+    NewAdd = DAG.getNode(ISD::ADD, DL, VT,
+                         V, DAG.getNode(ISD::SHL, DL, VT,
+                                        V, DAG.getConstant(1, MVT::i32)));
+   break;
+  case 5: // 4 + 1
+    NewAdd = DAG.getNode(ISD::ADD, DL, VT,
+                         V, DAG.getNode(ISD::SHL, DL, VT,
+                                        V, DAG.getConstant(2, MVT::i32)));
+    break;
+  case 7: // 8 - 1
+    NewAdd = DAG.getNode(ISD::SUB, DL, VT,
+                         DAG.getNode(ISD::SHL, DL, VT,
+                                     V, DAG.getConstant(3, MVT::i32)),
+                         V);
+    break;
+  case 9: // 8 + 1
+    NewAdd = DAG.getNode(ISD::ADD, DL, VT,
+                         V, DAG.getNode(ISD::SHL, DL, VT,
+                                        V, DAG.getConstant(3, MVT::i32)));
+    break;
+  default: return SDValue();
+  }
+
+  if (ShiftAmt != 0) {
+    SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAdd,
+                                   DAG.getConstant(ShiftAmt, MVT::i32));
+    // Do not add new nodes to DAG combiner worklist.
+    DCI.CombineTo(N, NewShift, false);
+    return SDValue();
+  }
+
+  // Do not add new nodes to DAG combiner worklist.
+  DCI.CombineTo(N, NewAdd, false);
+  return SDValue();
+}
+
 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
 /// ARMISD::VMOVRRD.
 static SDValue PerformVMOVRRDCombine(SDNode *N,
@@ -3970,6 +4040,7 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
   default: break;
   case ISD::ADD:        return PerformADDCombine(N, DCI);
   case ISD::SUB:        return PerformSUBCombine(N, DCI);
+  case ISD::MUL:        return PerformMULCombine(N, DCI, Subtarget);
   case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
   case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
   case ISD::SHL:
diff --git a/test/CodeGen/ARM/mul_const.ll b/test/CodeGen/ARM/mul_const.ll
index 93188cdd88..8c10246461 100644
--- a/test/CodeGen/ARM/mul_const.ll
+++ b/test/CodeGen/ARM/mul_const.ll
@@ -1,17 +1,43 @@
 ; RUN: llc < %s -march=arm | FileCheck %s
 
-define i32 @t1(i32 %v) nounwind readnone {
+define i32 @t9(i32 %v) nounwind readnone {
 entry:
-; CHECK: t1:
+; CHECK: t9:
 ; CHECK: add r0, r0, r0, lsl #3
 	%0 = mul i32 %v, 9
 	ret i32 %0
 }
 
-define i32 @t2(i32 %v) nounwind readnone {
+define i32 @t7(i32 %v) nounwind readnone {
 entry:
-; CHECK: t2:
+; CHECK: t7:
 ; CHECK: rsb r0, r0, r0, lsl #3
 	%0 = mul i32 %v, 7
 	ret i32 %0
 }
+
+define i32 @t5(i32 %v) nounwind readnone {
+entry:
+; CHECK: t5:
+; CHECK: add r0, r0, r0, lsl #2
+        %0 = mul i32 %v, 5
+        ret i32 %0
+}
+
+define i32 @t3(i32 %v) nounwind readnone {
+entry:
+; CHECK: t3:
+; CHECK: add r0, r0, r0, lsl #1
+        %0 = mul i32 %v, 3
+        ret i32 %0
+}
+
+define i32 @t12288(i32 %v) nounwind readnone {
+entry:
+; CHECK: t12288:
+; CHECK: add r0, r0, r0, lsl #1
+; CHECK: mov     r0, r0, lsl #12
+        %0 = mul i32 %v, 12288
+        ret i32 %0
+}
+