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authorBill Wendling <isanbard@gmail.com>2013-06-07 10:52:37 +0000
committerBill Wendling <isanbard@gmail.com>2013-06-07 10:52:37 +0000
commita1e338368f5df797f3a1da81adac794340e30d11 (patch)
treecdd6fc5119e9cf68d1deadd686eb8baba79d6248
parent6a1cc8fbd6bef2c3464a51f812c9120f234a7a46 (diff)
Add blurb for PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_33@183500 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--docs/ReleaseNotes.rst24
1 files changed, 24 insertions, 0 deletions
diff --git a/docs/ReleaseNotes.rst b/docs/ReleaseNotes.rst
index 112662c2a6..f2afdc9efe 100644
--- a/docs/ReleaseNotes.rst
+++ b/docs/ReleaseNotes.rst
@@ -114,6 +114,30 @@ New features and improvements:
- Delay slot filler pass can now search successor blocks for instructions to
fill delay slots (use option -disable-mips-df-succbb-search=false).
+PowerPC Target
+--------------
+
+New features and improvements:
+
+- PowerPC now supports an assembly parser.
+- Support added for thread-local storage. 64-bit ELF subtarget only.
+- Support added for medium and large code model (-mcmodel=medium,large).
+ Medium code model is now the default. 64-bit ELF subtarget only.
+- Improved register allocation (fewer reserved registers).
+- 64-bit atomic load and store are now supported.
+- Improved code generation for unaligned memory accesses of scalar types.
+- Improved performance of floating-point divide and square root
+ with -ffast-math.
+- Support for predicated returns.
+- Improved code generation for comparisons.
+- Support added for inline setjmp and longjmp.
+- Support added for many instructions introduced in PowerISA 2.04, 2.05,
+ and 2.06.
+- Improved spill code for vector registers.
+- Support added for -mno-altivec.
+- ABI compatibility fixes for complex parameters, 128-bit integer parameters,
+ and varargs functions. 64-bit ELF subtarget only.
+
Loop Vectorizer
---------------