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authorOwen Anderson <resistor@mac.com>2011-09-01 17:47:45 +0000
committerOwen Anderson <resistor@mac.com>2011-09-01 17:47:45 +0000
commit7f17b5a483ea358f2b9e3958f16cf34d75d5b4da (patch)
tree84df33d55e7c8a99109119e2b3eb2790ec820feb
parentae779eea27f41d31268931a6508bd0536cfbc724 (diff)
t2Bcc is allowed to have a predicate without a preceding IT instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138946 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/AsmParser/ARMAsmParser.cpp3
-rw-r--r--test/MC/ARM/basic-thumb2-instructions.s6
2 files changed, 8 insertions, 1 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index bba09d4674..f71d0f8642 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -3377,7 +3377,8 @@ validateInstruction(MCInst &Inst,
// Check for non-'al' condition codes outside of the IT block.
} else if (isThumbTwo() && MCID.isPredicable() &&
Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
- ARMCC::AL && Inst.getOpcode() != ARM::tBcc)
+ ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
+ Inst.getOpcode() != ARM::t2Bcc)
return Error(Loc, "predicated instructions must be in IT block");
switch (Inst.getOpcode()) {
diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s
index 492687ea40..4641fe3d37 100644
--- a/test/MC/ARM/basic-thumb2-instructions.s
+++ b/test/MC/ARM/basic-thumb2-instructions.s
@@ -86,6 +86,12 @@ _func:
@ CHECK: addw r12, r6, #256 @ encoding: [0x06,0xf2,0x00,0x1c]
@ CHECK: adds.w r1, r2, #496 @ encoding: [0x12,0xf5,0xf8,0x71]
+@------------------------------------------------------------------------------
+@ B
+@------------------------------------------------------------------------------
+ bmi.w #-183396
+
+@ CHECK: bmi.w #-183396 @ encoding: [0x13,0xf5,0xce,0xa9]
@------------------------------------------------------------------------------
@ CBZ/CBNZ