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authorJim Grosbach <grosbach@apple.com>2010-11-18 23:24:22 +0000
committerJim Grosbach <grosbach@apple.com>2010-11-18 23:24:22 +0000
commit75b7b879c078366d3e7d90360f01a6e7c0a75b68 (patch)
treeea77efededab54c98d2ba5db11ecf64164bfbfa8
parent9684a7c1281e7d7f6d7ab7c3f8484fe2138f39bc (diff)
ARM Encoding information for UXTAH and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119753 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/Target/ARM/ARMInstrInfo.td12
1 files changed, 12 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 59071eef7a..0ef1e3c653 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -752,7 +752,14 @@ multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm",
[(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
Requires<[IsARM, HasV6]> {
+ bits<4> Rd;
+ bits<4> Rm;
+ bits<4> Rn;
+ let Inst{19-16} = Rn;
+ let Inst{15-12} = Rd;
let Inst{11-10} = 0b00;
+ let Inst{9-4} = 0b000111;
+ let Inst{3-0} = Rm;
}
def rr_rot : AExtI<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm,
rot_imm:$rot),
@@ -760,10 +767,15 @@ multiclass AI_exta_rrot<bits<8> opcod, string opc, PatFrag opnode> {
[(set GPR:$Rd, (opnode GPR:$Rn,
(rotr GPR:$Rm, rot_imm:$rot)))]>,
Requires<[IsARM, HasV6]> {
+ bits<4> Rd;
+ bits<4> Rm;
bits<4> Rn;
bits<2> rot;
let Inst{19-16} = Rn;
+ let Inst{15-12} = Rd;
let Inst{11-10} = rot;
+ let Inst{9-4} = 0b000111;
+ let Inst{3-0} = Rm;
}
}