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| author | Evan Cheng <evan.cheng@apple.com> | 2006-05-07 10:10:20 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-05-07 10:10:20 +0000 |
| commit | 74811450b24ee03f7328273b72efbeaad54d9e74 (patch) | |
| tree | 64ba4bae446a3b2d1c72c51d9f017cfd207e5e9a | |
| parent | e564de2d3746d0b7f62e2c82f27ebc24cc1ad9e4 (diff) | |
Typo's
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28158 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86RegisterInfo.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index b7b5874717..5b20c1c392 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -47,8 +47,8 @@ let Namespace = "X86" in { def AL : RegisterGroup<"AL", [AX,EAX]>, DwarfRegNum<0>; def CL : RegisterGroup<"CL", [CX,ECX]>, DwarfRegNum<2>; def DL : RegisterGroup<"DL", [DX,EDX]>, DwarfRegNum<1>; - def BL : RegisterGroup<"BL", [BX,EBX]>, DwarfRegNum<0>; - def AH : RegisterGroup<"AH", [AX,EAX]>, DwarfRegNum<2>; + def BL : RegisterGroup<"BL", [BX,EBX]>, DwarfRegNum<3>; + def AH : RegisterGroup<"AH", [AX,EAX]>, DwarfRegNum<0>; def CH : RegisterGroup<"CH", [CX,ECX]>, DwarfRegNum<2>; def DH : RegisterGroup<"DH", [DX,EDX]>, DwarfRegNum<1>; def BH : RegisterGroup<"BH", [BX,EBX]>, DwarfRegNum<3>; |