diff options
| author | Johnny Chen <johnny.chen@apple.com> | 2010-03-26 22:28:56 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2010-03-26 22:28:56 +0000 |
| commit | 629c25cda6af43c16ee4d1ef2301c9ff1531d041 (patch) | |
| tree | ef4b4b504b013df3d8ac2850d6b258e6bfc8e5cf | |
| parent | f35d88f439507c729e1f98522d9865b02fdc7c9c (diff) | |
Add NVExtFrm to represent NEON Vector Extract Instructions, that uses Inst{11-8}
to encode the byte location of the extracted result in the concatenation of the
operands, from the least significant end.
Modify VEXTd and VEXTq classes to use the format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99659 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrFormats.td | 1 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 20 |
2 files changed, 11 insertions, 10 deletions
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index f893e5b001..08ac36375c 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -68,6 +68,7 @@ def N2RegVShLFrm : Format<36>; def N2RegVShRFrm : Format<37>; def N3RegFrm : Format<38>; def N3RegVShFrm : Format<39>; +def NVExtFrm : Format<40>; // Misc flags. diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 3fcb95133d..6e17f77548 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -3253,18 +3253,18 @@ def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>; // VEXT : Vector Extract class VEXTd<string OpcodeStr, string Dt, ValueType Ty> - : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst), - (ins DPR:$lhs, DPR:$rhs, i32imm:$index), IIC_VEXTD, - OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "", - [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs), - (Ty DPR:$rhs), imm:$index)))]>; + : N3Vf<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$dst), + (ins DPR:$lhs, DPR:$rhs, i32imm:$index), NVExtFrm, + IIC_VEXTD, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "", + [(set DPR:$dst, (Ty (NEONvext (Ty DPR:$lhs), + (Ty DPR:$rhs), imm:$index)))]>; class VEXTq<string OpcodeStr, string Dt, ValueType Ty> - : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst), - (ins QPR:$lhs, QPR:$rhs, i32imm:$index), IIC_VEXTQ, - OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "", - [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs), - (Ty QPR:$rhs), imm:$index)))]>; + : N3Vf<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$dst), + (ins QPR:$lhs, QPR:$rhs, i32imm:$index), NVExtFrm, + IIC_VEXTQ, OpcodeStr, Dt, "$dst, $lhs, $rhs, $index", "", + [(set QPR:$dst, (Ty (NEONvext (Ty QPR:$lhs), + (Ty QPR:$rhs), imm:$index)))]>; def VEXTd8 : VEXTd<"vext", "8", v8i8>; def VEXTd16 : VEXTd<"vext", "16", v4i16>; |