diff options
| author | Jim Stichnoth <stichnot@chromium.org> | 2013-09-16 12:26:09 -0700 |
|---|---|---|
| committer | Jim Stichnoth <stichnot@chromium.org> | 2013-09-16 12:26:09 -0700 |
| commit | 591359fae065fb5f86ba957a550503daef727536 (patch) | |
| tree | 8881027a692cea07997f733b736a8ece34054361 | |
| parent | 1d241cef755d5a129d3f17117c559a70ecaa0e0c (diff) | |
Work around a gcc 4.6.3 / 4.7 bug.
GCC bug http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58416
causes the bf64-1.c test to fail in the GCC torture test suite.
This provides an upstreamable workaround.
Inspection of the LLVM code base showed no other instances of
the pattern that triggers the gcc bug.
This can also be upstreamed as soon as I can get a working
x86-32 upstream build working to verify/test against. In the
meantime, we can make one pnacl-fyi bot go green again.
BUG= https://code.google.com/p/nativeclient/issues/detail?id=3685
R=jfb@chromium.org, jfb@google.com
Review URL: https://codereview.chromium.org/23437037
| -rw-r--r-- | include/llvm/MC/MCInst.h | 6 | ||||
| -rw-r--r-- | test/CodeGen/X86/invalid-gcc-snan-conversion.ll | 25 |
2 files changed, 30 insertions, 1 deletions
diff --git a/include/llvm/MC/MCInst.h b/include/llvm/MC/MCInst.h index 4766815da5..0b657bd146 100644 --- a/include/llvm/MC/MCInst.h +++ b/include/llvm/MC/MCInst.h @@ -50,7 +50,11 @@ class MCOperand { }; public: - MCOperand() : Kind(kInvalid), FPImmVal(0.0) {} + // @LOCALMOD-START + // Initialize ImmVal instead of FPImmVal, thanks to + // http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58416 + MCOperand() : Kind(kInvalid), ImmVal(0) {} + // @LOCALMOD-END bool isValid() const { return Kind != kInvalid; } bool isReg() const { return Kind == kRegister; } diff --git a/test/CodeGen/X86/invalid-gcc-snan-conversion.ll b/test/CodeGen/X86/invalid-gcc-snan-conversion.ll new file mode 100644 index 0000000000..416f0c0b83 --- /dev/null +++ b/test/CodeGen/X86/invalid-gcc-snan-conversion.ll @@ -0,0 +1,25 @@ +; If LLVM is built in Release mode with a buggy gcc under x86-32, it +; may transform 64-bit constants with a signaling NaN bit pattern into +; a quiet NaN bit pattern. See +; http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58416 + +; RUN: llc -march=x86-64 < %s | FileCheck %s + +define i32 @main() #0 { +entry: + %retval = alloca i32, align 4 + %tmp = alloca i64, align 8 + store i32 0, i32* %retval +; -4503599627370495 == 0xfff0000000000001 + store i64 -4503599627370495, i64* %tmp, align 8 + %0 = load i64* %tmp, align 8 + call void @Consume(i64 %0) + ret i32 0 +} + +; CHECK: main: +; make sure 0xfff0000000000001 didn't change to 0xfff8000000000001 +; CHECK: 0xFFF00000 +; CHECK-NOT: 0xFFF80000 + +declare void @Consume(i64) #1 |