diff options
| author | Anton Korobeynikov <asl@math.spbu.ru> | 2011-01-24 22:38:45 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2011-01-24 22:38:45 +0000 |
| commit | 5899a60d2fb02f7e2d094d710babbe1d3bd97254 (patch) | |
| tree | 77a4f177816c0c6da72e9e4be8698fa99e3821cd | |
| parent | d4e09787526f105f16c11f091ef6ef67c82da5d3 (diff) | |
Provide correct registers for EH stuff on ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124151 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 91dca5fd59..ade00c6d0a 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -551,9 +551,10 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); - // FIXME: Shouldn't need this, since no register is used, but the legalizer - // doesn't yet know how to not do that for SjLj. - setExceptionSelectorRegister(ARM::R0); + setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); + setExceptionPointerRegister(ARM::R0); + setExceptionSelectorRegister(ARM::R1); + setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use // the default expansion. |