[MIPS] Update sandboxing changes for LLVM on MIPS.

This change

- resolves conflicts from previous merges;
- prevents delay slot filler to use instructions that could be masked;
- generates calls to __nacl_read_tp to access thread pointer;
- removes previous (now obsolete) sandboxing code of unaligned loads and stores;
- propagates relocation model to MipsELFObjectWriter, so that it can set
  flag ELF::EF_MIPS_PIC (small hack).

BUG= http://code.google.com/p/nativeclient/issues/detail?id=2275
TEST= pnacl/build.sh all

Review URL: https://codereview.chromium.org/11115013
Patch from Petar Jovanovic <petarj@mips.com>.

7 files changed, 46 insertions, 55 deletions

diff --git a/lib/MC/MCObjectFileInfo.cpp b/lib/MC/MCObjectFileInfo.cpp
index 2e1604d6b5..3338a17e5c 100644
--- a/lib/MC/MCObjectFileInfo.cpp
+++ b/lib/MC/MCObjectFileInfo.cpp
@@ -543,9 +543,16 @@ void MCObjectFileInfo::InitCOFFMCObjectFileInfo(Triple T) {
                         SectionKind::getDataRel());
 }
 
+// @LOCALMOD-START
+// TODO(petarj): HACK! Find a better way to set ELF::EF_MIPS_PIC flag.
+// See also file lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp.
+Reloc::Model RelocModelOption = Reloc::Default;
+// @LOCALMOD-END
+
 void MCObjectFileInfo::InitMCObjectFileInfo(StringRef TT, Reloc::Model relocm,
                                             CodeModel::Model cm,
                                             MCContext &ctx) {
+  RelocModelOption = relocm;  // @LOCALMOD
   RelocM = relocm;
   CMModel = cm;
   Ctx = &ctx;
diff --git a/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp b/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
index 5d240fe847..6ad8669d04 100644
--- a/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
+++ b/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp
@@ -18,6 +18,13 @@
 #include "llvm/Support/ErrorHandling.h"
 #include <list>
 
+// @LOCALMOD-START
+// TODO(petarj): HACK! Find better way to set ELF::EF_MIPS_PIC flag.
+// See also file lib/MC/MCObjectFileInfo.cpp.
+#include "llvm/Support/CodeGen.h"
+extern llvm::Reloc::Model RelocModelOption;
+// @LOCALMOD-END
+
 using namespace llvm;
 
 namespace {
@@ -71,6 +78,10 @@ unsigned MipsELFObjectWriter::getEFlags() const {
     Flag |= ELF::EF_MIPS_ARCH_64R2;
   else
     Flag |= ELF::EF_MIPS_ARCH_32R2;
+  /* @LOCLAMOD-START */
+  if (RelocModelOption == Reloc::PIC_ || RelocModelOption == Reloc::Default)
+    Flag |= ELF::EF_MIPS_PIC;
+  /* @LOCLAMOD-END */
   return Flag;
 }
 
diff --git a/lib/Target/Mips/MipsDelaySlotFiller.cpp b/lib/Target/Mips/MipsDelaySlotFiller.cpp
index e3c8ed75cf..d014ba1792 100644
--- a/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -141,6 +141,11 @@ FunctionPass *llvm::createMipsDelaySlotFillerPass(MipsTargetMachine &tm) {
   return new Filler(tm);
 }
 
+// @LOCALMOD-START
+extern bool IsDangerousLoad(const MachineInstr &MI, int *AddrIdx);
+extern bool IsDangerousStore(const MachineInstr &MI, int *AddrIdx);
+// @LOCALMOD-END
+
 bool Filler::findDelayInstr(MachineBasicBlock &MBB,
                             InstrIter slot,
                             InstrIter &Filler) {
@@ -160,11 +165,18 @@ bool Filler::findDelayInstr(MachineBasicBlock &MBB,
     // Convert to forward iterator.
     InstrIter FI(llvm::next(I).base());
 
+    int Dummy; // @LOCALMOD
     if (I->hasUnmodeledSideEffects()
         || I->isInlineAsm()
         || I->isLabel()
         || FI == LastFiller
         || I->isPseudo()
+        // @LOCALMOD-START
+        // Don't put in delay slot instructions that could be masked.
+        || IsDangerousLoad(*FI, &Dummy)
+        || IsDangerousStore(*FI, &Dummy)
+        || FI->modifiesRegister(Mips::SP, TM.getRegisterInfo())
+        // @LOCALMOD-END
         //
         // Should not allow:
         // ERET, DERET or WAIT, PAUSE. Need to add these to instruction
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index 9ff22905cb..da6a8d2a67 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -1835,17 +1835,21 @@ LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
     unsigned PtrSize = PtrVT.getSizeInBits();
     IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
 
-    SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
+    SDValue TlsReadTp = DAG.getExternalSymbol("__nacl_read_tp", PtrVT);
 
     ArgListTy Args;
-    std::pair<SDValue, SDValue> CallResult =
-        LowerCallTo(DAG.getEntryNode(),
-                   (Type *) Type::getInt32Ty(*DAG.getContext()),
-                   false, false, false, false, 0, CallingConv::C, false,
-                   false, true, TlsGetAddr, Args, DAG, dl);
+    TargetLowering::CallLoweringInfo CLI(DAG.getEntryNode(), PtrTy,
+                  false, false, false, false, 0, CallingConv::C,
+                  /*isTailCall=*/false, /*doesNotRet=*/false,
+                  /*isReturnValueUsed=*/true,
+                  TlsReadTp, Args, DAG, dl);
+    std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
 
     SDValue ThreadPointer = CallResult.first;
-    return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
+    SDValue TPOffset = DAG.getConstant(0x7000, MVT::i32);
+    SDValue ThreadPointer2 = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer,
+                                         TPOffset);
+    return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer2, Offset);
   }
   // @LOCALMOD-END
 
diff --git a/lib/Target/Mips/MipsMCInstLower.cpp b/lib/Target/Mips/MipsMCInstLower.cpp
index 1d108ab192..d8119ff75c 100644
--- a/lib/Target/Mips/MipsMCInstLower.cpp
+++ b/lib/Target/Mips/MipsMCInstLower.cpp
@@ -161,47 +161,3 @@ void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
 }
 
 
-  MCInst Instr4, Mask1, Mask2; // @LOCALMOD
-  // @LOCALMOD-START
-  MCOperand MaskReg = MCOperand::CreateReg(Mips::LoadStoreStackMaskReg);
-  // @LOCALMOD-END
-
-  // @LOCALMOD-START
-  if (AsmPrinter.TM.getSubtarget<MipsSubtarget>().isTargetNaCl()) {
-    Mask1.setOpcode(Mips::SFI_GUARD_LOADSTORE);
-    Mask1.addOperand(Base);
-    Mask1.addOperand(Base);
-    Mask1.addOperand(MaskReg);
-
-    Mask2.setOpcode(Mips::SFI_GUARD_LOADSTORE);
-    Mask2.addOperand(Base);
-    Mask2.addOperand(Base);
-    Mask2.addOperand(MaskReg);
-    if (Opc == Mips::ULW || Opc == Mips::USW || Opc == Mips::ULHu) {
-     // FIXME: ULHu should be rewritten because it uses mips32r2 instr. INS
-      MCInsts.push_back(Mask1);
-      MCInsts.push_back(Instr1);
-      MCInsts.push_back(Mask2);
-      MCInsts.push_back(Instr2);
-      if (!TwoInstructions) MCInsts.push_back(Instr3);
-      return;
-    } else if (Opc == Mips::ULH) {
-      MCInsts.push_back(Mask1);
-      MCInsts.push_back(Instr1);
-      MCInsts.push_back(Mask2);
-      MCInsts.push_back(Instr2);
-      MCInsts.push_back(Instr3);
-      MCInsts.push_back(Instr4);
-      return;
-    } else if (Opc == Mips::USH) {
-      MCInsts.push_back(Mask1);
-      MCInsts.push_back(Instr1);
-      MCInsts.push_back(Instr2);
-      MCInsts.push_back(Mask2);
-      MCInsts.push_back(Instr3);
-      return;
-    } else {
-      llvm_unreachable("unaligned instruction not sandboxed");
-    }
-  }
-  // @LOCALMOD-END
\ No newline at end of file
diff --git a/lib/Target/Mips/MipsNaClRewritePass.cpp b/lib/Target/Mips/MipsNaClRewritePass.cpp
index cce770eebd..f675e5663a 100644
--- a/lib/Target/Mips/MipsNaClRewritePass.cpp
+++ b/lib/Target/Mips/MipsNaClRewritePass.cpp
@@ -189,7 +189,7 @@ void MipsNaClRewritePass::SandboxLoadStore(MachineBasicBlock &MBB,
   return;
 }
 
-static bool IsDangerousLoad(const MachineInstr &MI, int *AddrIdx) {
+bool IsDangerousLoad(const MachineInstr &MI, int *AddrIdx) {
   unsigned Opcode = MI.getOpcode();
   switch (Opcode) {
   default: return false;
@@ -217,7 +217,7 @@ static bool IsDangerousLoad(const MachineInstr &MI, int *AddrIdx) {
   return true;
 }
 
-static bool IsDangerousStore(const MachineInstr &MI, int *AddrIdx) {
+bool IsDangerousStore(const MachineInstr &MI, int *AddrIdx) {
   unsigned Opcode = MI.getOpcode();
   switch (Opcode) {
   default: return false;
diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp
index 5e0f930395..ab32bc4a66 100644
--- a/lib/Target/Mips/MipsRegisterInfo.cpp
+++ b/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -81,8 +81,9 @@ MipsRegisterInfo::getCallPreservedMask(CallingConv::ID) const {
 BitVector MipsRegisterInfo::
 getReservedRegs(const MachineFunction &MF) const {
   static const uint16_t ReservedCPURegs[] = {
-    Mips::ZERO, Mips::AT, Mips::K0, Mips::K1, Mips::SP
-    Mips::T6, Mips::T7, Mips::T8          // @LOCALMOD: reserved for PNaCl use
+    Mips::ZERO, Mips::AT,
+    Mips::T6, Mips::T7, Mips::T8,          // @LOCALMOD: reserved for PNaCl use
+    Mips::K0, Mips::K1, Mips::SP
   };
 
   static const uint16_t ReservedCPU64Regs[] = {