diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2009-07-17 22:13:25 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-07-17 22:13:25 +0000 |
| commit | 47e9fab1584a3fc9311fdecdbb87124e0a0b39e8 (patch) | |
| tree | 48fad3fb8c68e73a61589eeb520e3c0ca6324d46 | |
| parent | 12c67fbf2a49145f332a12fbb32441310d322088 (diff) | |
Fix x86 inline ams 'q' constraint support. In 32-bit mode, it's just like 'Q', i.e. EAX, EDX, ECX, EBX. In 64-bit mode, it just means all the i64r registers. Yeah, that makes sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76248 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 32 | ||||
| -rw-r--r-- | test/CodeGen/X86/inline-asm-q-regs.ll | 10 |
2 files changed, 41 insertions, 1 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 097713f078..84e1612f9c 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -8840,7 +8840,37 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint, // FIXME: not handling fp-stack yet! switch (Constraint[0]) { // GCC X86 Constraint Letters default: break; // Unknown constraint letter - case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode) + case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. + if (Subtarget->is64Bit()) { + if (VT == MVT::i32) + return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, + X86::ESI, X86::EDI, X86::R8D, X86::R9D, + X86::R10D,X86::R11D,X86::R12D, + X86::R13D,X86::R14D,X86::R15D, + X86::EBP, X86::ESP, 0); + else if (VT == MVT::i16) + return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, + X86::SI, X86::DI, X86::R8W,X86::R9W, + X86::R10W,X86::R11W,X86::R12W, + X86::R13W,X86::R14W,X86::R15W, + X86::BP, X86::SP, 0); + else if (VT == MVT::i8) + return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, + X86::SIL, X86::DIL, X86::R8B,X86::R9B, + X86::R10B,X86::R11B,X86::R12B, + X86::R13B,X86::R14B,X86::R15B, + X86::BPL, X86::SPL, 0); + + else if (VT == MVT::i64) + return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, + X86::RSI, X86::RDI, X86::R8, X86::R9, + X86::R10, X86::R11, X86::R12, + X86::R13, X86::R14, X86::R15, + X86::RBP, X86::RSP, 0); + + break; + } + // 32-bit fallthrough case 'Q': // Q_REGS if (VT == MVT::i32) return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); diff --git a/test/CodeGen/X86/inline-asm-q-regs.ll b/test/CodeGen/X86/inline-asm-q-regs.ll new file mode 100644 index 0000000000..19df81b231 --- /dev/null +++ b/test/CodeGen/X86/inline-asm-q-regs.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=x86-64 +; rdar://7066579 + + type { i64, i64, i64, i64, i64 } ; type %0 + +define void @t() nounwind { +entry: + %asmtmp = call %0 asm sideeffect "mov %cr0, $0 \0Amov %cr2, $1 \0Amov %cr3, $2 \0Amov %cr4, $3 \0Amov %cr8, $0 \0A", "=q,=q,=q,=q,=q,~{dirflag},~{fpsr},~{flags}"() nounwind ; <%0> [#uses=0] + ret void +} |