diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2011-11-09 01:57:03 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-11-09 01:57:03 +0000 |
| commit | 44ee4714a8c245d4fdfd03840efcf58c3f66c6bc (patch) | |
| tree | 86a1807d5e2e9f275789cad8808d86d7d03e2ba6 | |
| parent | f4c4768fb2277cb940a90cb2f0e9a747ebc671c3 (diff) | |
Hide cpu name checking in ARMSubtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144154 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMSubtarget.h | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index a871ed7d44..4c3be89b3e 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -1080,7 +1080,7 @@ bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB, unsigned OddRegNum = TRI->getDwarfRegNum(OddReg, false); // ARM errata 602117: LDRD with base in list may result in incorrect base // register when interrupted or faulted. - bool Errata602117 = EvenReg == BaseReg && STI->getCPUString() == "cortex-m3"; + bool Errata602117 = EvenReg == BaseReg && STI->isCortexM3(); if (!Errata602117 && ((EvenRegNum & 1) == 0 && (EvenRegNum + 1) == OddRegNum)) return false; diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h index 5e884e0099..a35f450550 100644 --- a/lib/Target/ARM/ARMSubtarget.h +++ b/lib/Target/ARM/ARMSubtarget.h @@ -191,6 +191,7 @@ protected: bool isCortexA8() const { return ARMProcFamily == CortexA8; } bool isCortexA9() const { return ARMProcFamily == CortexA9; } + bool isCortexM3() const { return CPUString == "cortex-m3"; } bool hasARMOps() const { return !NoARM; } |