diff options
| author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-07-16 14:27:53 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-07-16 14:27:53 +0000 |
| commit | 361a78756b35c886aa3d01d3bd40c2adcf56cce2 (patch) | |
| tree | 756991777db9b025c36c6bb1067754ea441a5c00 | |
| parent | 628d41952001784bcd5b45156eefb2eed1fd6c43 (diff) | |
Out GR128 regclass is not a 'real' i128 one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76044 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/SystemZ/SystemZISelLowering.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/SystemZ/SystemZInstrInfo.td | 6 | ||||
| -rw-r--r-- | lib/Target/SystemZ/SystemZRegisterInfo.td | 2 |
3 files changed, 4 insertions, 5 deletions
diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp index 05797c81ab..df9164a07a 100644 --- a/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -45,7 +45,6 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) : addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass); addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass); addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass); - addRegisterClass(MVT::i128, SystemZ::GR128RegisterClass); addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass); if (!UseSoftFloat) { diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index 7bfd8eb82b..9b98ec7119 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -810,18 +810,18 @@ def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>; // muls def : Pat<(mulhs GR32:$src1, GR32:$src2), - (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)), + (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), GR32:$src1, subreg_odd32), GR32:$src2), subreg_even32)>; def : Pat<(mulhu GR32:$src1, GR32:$src2), - (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)), + (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), GR32:$src1, subreg_odd32), GR32:$src2), subreg_even32)>; def : Pat<(mulhu GR64:$src1, GR64:$src2), - (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)), + (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src1, subreg_odd), GR64:$src2), subreg_even)>; diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.td b/lib/Target/SystemZ/SystemZRegisterInfo.td index 73df94238b..8795847a6c 100644 --- a/lib/Target/SystemZ/SystemZRegisterInfo.td +++ b/lib/Target/SystemZ/SystemZRegisterInfo.td @@ -399,7 +399,7 @@ def GR64P : RegisterClass<"SystemZ", [v2i32], 64, }]; } -def GR128 : RegisterClass<"SystemZ", [i128, v2i64], 128, +def GR128 : RegisterClass<"SystemZ", [v2i64], 128, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q]> { let SubRegClassList = [GR32, GR32, GR64, GR64]; |