diff options
| author | Chris Lattner <sabre@nondot.org> | 2006-03-31 19:48:58 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-03-31 19:48:58 +0000 |
| commit | 32a988a095ac93f54ca058bbeb7561f694c66b07 (patch) | |
| tree | 27b9c0b021c8d39276be9a716ec5c845c107b986 | |
| parent | b067a1e7e68c4446d3512c25d3a5ac55c6dd76f8 (diff) | |
Add, sub and shuffle are legal for all vector types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27305 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index b92e4f35cd..4160bb3338 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -171,12 +171,16 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) // First set operation action for all vector types to expand. Then we // will selectively turn on ones that can be effectively codegen'd. - for (unsigned VT = (unsigned)MVT::Vector + 1; - VT != (unsigned)MVT::LAST_VALUETYPE; VT++) { - setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand); - setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand); + for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; + VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { + // Add and sub are legal for all supported VT's. + setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal); + setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal); + setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Legal); + setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand); - setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand); + setOperationAction(ISD::DIV , (MVT::ValueType)VT, Expand); + setOperationAction(ISD::REM , (MVT::ValueType)VT, Expand); setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand); setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand); setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand); @@ -188,10 +192,7 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); - setOperationAction(ISD::ADD , MVT::v4f32, Legal); - setOperationAction(ISD::SUB , MVT::v4f32, Legal); setOperationAction(ISD::MUL , MVT::v4f32, Legal); - setOperationAction(ISD::ADD , MVT::v4i32, Legal); setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); |