diff options
| author | Craig Topper <craig.topper@gmail.com> | 2012-02-13 04:30:38 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-02-13 04:30:38 +0000 |
| commit | 2dcd718c1352f79a9728e6cc8d961fc1fe67bf2c (patch) | |
| tree | ae0227b85543706494f38cbd1576bab10686eafe | |
| parent | 7f42e9886e7da1dfb18bce03e444cd0686194872 (diff) | |
Update CanXFormVExtractWithShuffleIntoLoad to ensure bitcasts of loads only have one use. Matches DAGCombiner and prevents vector_shuffles from reaching isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150360 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 5 | ||||
| -rw-r--r-- | test/CodeGen/X86/vec_zext.ll | 58 |
2 files changed, 4 insertions, 59 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 6d292068bd..9eb91d2a40 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -6186,8 +6186,11 @@ bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG, return false; // Skip one more bit_convert if necessary - if (V.getOpcode() == ISD::BITCAST) + if (V.getOpcode() == ISD::BITCAST) { + if (!V.hasOneUse()) + return false; V = V.getOperand(0); + } if (!ISD::isNormalLoad(V.getNode())) return false; diff --git a/test/CodeGen/X86/vec_zext.ll b/test/CodeGen/X86/vec_zext.ll index 615a50b7af..8879565371 100644 --- a/test/CodeGen/X86/vec_zext.ll +++ b/test/CodeGen/X86/vec_zext.ll @@ -1,26 +1,6 @@ ; RUN: llc < %s -march=x86-64 ; PR 9267 -define<4 x i32> @func_16_32() { - %F = load <4 x i16>* undef - %G = zext <4 x i16> %F to <4 x i32> - %H = load <4 x i16>* undef - %Y = zext <4 x i16> %H to <4 x i32> - %T = add <4 x i32> %Y, %G - store <4 x i32>%T , <4 x i32>* undef - ret <4 x i32> %T -} - -define<4 x i64> @func_16_64() { - %F = load <4 x i16>* undef - %G = zext <4 x i16> %F to <4 x i64> - %H = load <4 x i16>* undef - %Y = zext <4 x i16> %H to <4 x i64> - %T = xor <4 x i64> %Y, %G - store <4 x i64>%T , <4 x i64>* undef - ret <4 x i64> %T -} - define<4 x i64> @func_32_64() { %F = load <4 x i32>* undef %G = zext <4 x i32> %F to <4 x i64> @@ -29,41 +9,3 @@ define<4 x i64> @func_32_64() { %T = or <4 x i64> %Y, %G ret <4 x i64> %T } - -define<4 x i16> @func_8_16() { - %F = load <4 x i8>* undef - %G = zext <4 x i8> %F to <4 x i16> - %H = load <4 x i8>* undef - %Y = zext <4 x i8> %H to <4 x i16> - %T = add <4 x i16> %Y, %G - ret <4 x i16> %T -} - -define<4 x i32> @func_8_32() { - %F = load <4 x i8>* undef - %G = zext <4 x i8> %F to <4 x i32> - %H = load <4 x i8>* undef - %Y = zext <4 x i8> %H to <4 x i32> - %T = sub <4 x i32> %Y, %G - ret <4 x i32> %T -} - -define<4 x i64> @func_8_64() { - %F = load <4 x i8>* undef - %G = zext <4 x i8> %F to <4 x i64> - %H = load <4 x i8>* undef - %Y = zext <4 x i8> %H to <4 x i64> - %T = add <4 x i64> %Y, %G - ret <4 x i64> %T -} - -define<4 x i32> @const_16_32() { - %G = zext <4 x i16> <i16 0, i16 3, i16 8, i16 7> to <4 x i32> - ret <4 x i32> %G -} - -define<4 x i64> @const_16_64() { - %G = zext <4 x i16> <i16 0, i16 3, i16 8, i16 7> to <4 x i64> - ret <4 x i64> %G -} - |