[indvars] Fix PR10946: SCEV cannot handle Vector IVs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140026 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 22 insertions, 0 deletions

diff --git a/lib/Transforms/Utils/SimplifyIndVar.cpp b/lib/Transforms/Utils/SimplifyIndVar.cpp
index ffaad2717b..5ee1eb1897 100644
--- a/lib/Transforms/Utils/SimplifyIndVar.cpp
+++ b/lib/Transforms/Utils/SimplifyIndVar.cpp
@@ -85,6 +85,8 @@ namespace {
 /// foldIVUser - Fold an IV operand into its use.  This removes increments of an
 /// aligned IV when used by a instruction that ignores the low bits.
 ///
+/// IVOperand is guaranteed SCEVable, but UseInst may not be.
+///
 /// Return the operand of IVOperand for this induction variable if IVOperand can
 /// be folded (in case more folding opportunities have been exposed).
 /// Otherwise return null.
@@ -241,6 +243,7 @@ void SimplifyIndvar::eliminateIVRemainder(BinaryOperator *Rem,
 
 /// eliminateIVUser - Eliminate an operation that consumes a simple IV and has
 /// no observable side-effect given the range of IV values.
+/// IVOperand is guaranteed SCEVable, but UseInst may not be.
 bool SimplifyIndvar::eliminateIVUser(Instruction *UseInst,
                                      Instruction *IVOperand) {
   if (ICmpInst *ICmp = dyn_cast<ICmpInst>(UseInst)) {
@@ -324,6 +327,9 @@ static bool isSimpleIVUser(Instruction *I, const Loop *L, ScalarEvolution *SE) {
 /// Once DisableIVRewrite is default, LSR will be the only client of IVUsers.
 ///
 void SimplifyIndvar::simplifyUsers(PHINode *CurrIV, IVVisitor *V) {
+  if (!SE->isSCEVable(CurrIV->getType()))
+    return;
+
   // Instructions processed by SimplifyIndvar for CurrIV.
   SmallPtrSet<Instruction*,16> Simplified;
 
diff --git a/test/Transforms/IndVarSimplify/2011-09-19-vectoriv.ll b/test/Transforms/IndVarSimplify/2011-09-19-vectoriv.ll
new file mode 100644
index 0000000000..6a01012fe2
--- /dev/null
+++ b/test/Transforms/IndVarSimplify/2011-09-19-vectoriv.ll
@@ -0,0 +1,16 @@
+; RUN: opt < %s -indvars -S | FileCheck %s
+; PR10946: Vector IVs are not SCEVable.
+; CHECK-NOT: phi
+define void @test() nounwind {
+allocas:
+  br i1 undef, label %cif_done, label %for_loop398
+
+cif_done:                                         ; preds = %allocas
+  ret void
+
+for_loop398:                                      ; preds = %for_loop398, %allocas
+  %storemerge35 = phi <4 x i32> [ %storemerge, %for_loop398 ], [ undef, %allocas ]
+  %bincmp431 = icmp sge <4 x i32> %storemerge35, <i32 5, i32 5, i32 5, i32 5>
+  %storemerge = bitcast <4 x float> undef to <4 x i32>
+  br label %for_loop398
+}