diff options
| author | Richard Osborne <richard@xmos.com> | 2013-01-22 22:55:04 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2013-01-22 22:55:04 +0000 |
| commit | 0ec35ac4fcd5c83e2ec35d04fc20db9eb387d289 (patch) | |
| tree | 1bbcb8be8f3ba1fe46640810b271f14cff74d286 | |
| parent | 7ad70bf46adf7a444c3318ba165e0cfd37fdd591 (diff) | |
Add instruction encodings / disassembly support for u10 / lu10 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173204 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/XCore/XCoreInstrFormats.td | 14 | ||||
| -rw-r--r-- | lib/Target/XCore/XCoreInstrInfo.td | 20 | ||||
| -rw-r--r-- | test/MC/Disassembler/XCore/xcore.txt | 14 |
3 files changed, 36 insertions, 12 deletions
diff --git a/lib/Target/XCore/XCoreInstrFormats.td b/lib/Target/XCore/XCoreInstrFormats.td index 0e0aab9e78..29bc65853d 100644 --- a/lib/Target/XCore/XCoreInstrFormats.td +++ b/lib/Target/XCore/XCoreInstrFormats.td @@ -125,12 +125,22 @@ class _FLU6<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern> let Inst{9-0} = a{15-6}; } -class _FU10<dag outs, dag ins, string asmstr, list<dag> pattern> +class _FU10<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> : InstXCore<2, outs, ins, asmstr, pattern> { + bits<10> a; + + let Inst{15-10} = opc; + let Inst{9-0} = a; } -class _FLU10<dag outs, dag ins, string asmstr, list<dag> pattern> +class _FLU10<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> : InstXCore<4, outs, ins, asmstr, pattern> { + bits<20> a; + + let Inst{31-26} = opc; + let Inst{25-16} = a{9-0}; + let Inst{15-10} = 0b111100; + let Inst{9-0} = a{19-10}; } class _F2R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern> diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td index 3984140b6a..d193b459f5 100644 --- a/lib/Target/XCore/XCoreInstrInfo.td +++ b/lib/Target/XCore/XCoreInstrInfo.td @@ -649,24 +649,24 @@ defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">; // TODO ldwcpl, blacp let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in -def LDAPF_u10 : _FU10<(outs), (ins i32imm:$addr), "ldap r11, $addr", []>; +def LDAPF_u10 : _FU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a", []>; let Defs = [R11], isReMaterializable = 1 in -def LDAPF_lu10 : _FLU10<(outs), (ins i32imm:$addr), "ldap r11, $addr", - [(set R11, (pcrelwrapper tglobaladdr:$addr))]>; +def LDAPF_lu10 : _FLU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a", + [(set R11, (pcrelwrapper tglobaladdr:$a))]>; -let Defs = [R11], isReMaterializable = 1 in -def LDAPF_lu10_ba : _FLU10<(outs), (ins i32imm:$addr), "ldap r11, $addr", - [(set R11, (pcrelwrapper tblockaddress:$addr))]>; +let Defs = [R11], isReMaterializable = 1, isCodeGenOnly = 1 in +def LDAPF_lu10_ba : _FLU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a", + [(set R11, (pcrelwrapper tblockaddress:$a))]>; let isCall=1, // All calls clobber the link register and the non-callee-saved registers: Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { -def BLRF_u10 : _FU10<(outs), (ins calltarget:$target), "bl $target", - [(XCoreBranchLink immU10:$target)]>; +def BLRF_u10 : _FU10<0b110100, (outs), (ins calltarget:$a), "bl $a", + [(XCoreBranchLink immU10:$a)]>; -def BLRF_lu10 : _FLU10<(outs), (ins calltarget:$target), "bl $target", - [(XCoreBranchLink immU20:$target)]>; +def BLRF_lu10 : _FLU10<0b110100, (outs), (ins calltarget:$a), "bl $a", + [(XCoreBranchLink immU20:$a)]>; } // Two operand short diff --git a/test/MC/Disassembler/XCore/xcore.txt b/test/MC/Disassembler/XCore/xcore.txt index 62e3ef60e3..43c3c8d99e 100644 --- a/test/MC/Disassembler/XCore/xcore.txt +++ b/test/MC/Disassembler/XCore/xcore.txt @@ -442,3 +442,17 @@ # CHECK: setsr 21863 0x55 0xf1 0x67 0x7b + +# u10 / lu10 instructions + +# CHECK: ldap r11, 40 +0x28 0xd8 + +# CHECK: ldap r11, 53112 +0x33 0xf0 0x78 0xdb + +# CHECK: bl 8 +0x08 0xd0 + +# CHECK: bl 38631 +0x25 0xf0 0xe7 0xd2 |