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| author | Rafael Espindola <rafael.espindola@gmail.com> | 2006-10-10 16:33:47 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2006-10-10 16:33:47 +0000 |
| commit | 0d9fe764dfcacf9978680cd8bc91cc27191f8546 (patch) | |
| tree | 727a9e37f7c821ac7d2f560484350ed8e2bd82ec | |
| parent | fb6abd7deae16f2a180415d85fa33b58e1467afa (diff) | |
compare doubles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30856 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMISelDAGToDAG.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 4 | ||||
| -rw-r--r-- | test/CodeGen/ARM/fpcmp.ll | 11 |
3 files changed, 16 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 5598733890..c27136c473 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -539,10 +539,10 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, static SDOperand GetCMP(ISD::CondCode CC, SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) { MVT::ValueType vt = LHS.getValueType(); - assert(vt == MVT::i32 || vt == MVT::f32); + assert(vt == MVT::i32 || vt == MVT::f32 || vt == MVT::f64); //Note: unordered floating point compares should use a non throwing //compare. - bool isUnorderedFloat = vt == MVT::f32 && + bool isUnorderedFloat = (vt == MVT::f32 || vt == MVT::f64) && (CC >= ISD::SETUO && CC <= ISD::SETUNE); assert(!isUnorderedFloat && "Unordered float compares are not supported"); diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 3371871a7c..45728ac607 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -178,6 +178,10 @@ def fcmpes : InstARM<(ops FPRegs:$a, FPRegs:$b), "fcmpes $a, $b", [(armcmp FPRegs:$a, FPRegs:$b)]>; +def fcmped : InstARM<(ops DFPRegs:$a, DFPRegs:$b), + "fcmped $a, $b", + [(armcmp DFPRegs:$a, DFPRegs:$b)]>; + // Floating Point Conversion // We use bitconvert for moving the data between the register classes. // The format conversion is done with ARM specific nodes diff --git a/test/CodeGen/ARM/fpcmp.ll b/test/CodeGen/ARM/fpcmp.ll index 6d9012df41..53529bcf04 100644 --- a/test/CodeGen/ARM/fpcmp.ll +++ b/test/CodeGen/ARM/fpcmp.ll @@ -3,7 +3,9 @@ ; RUN: llvm-as < %s | llc -march=arm | grep moveq && ; RUN: llvm-as < %s | llc -march=arm | grep movgt && ; RUN: llvm-as < %s | llc -march=arm | grep movge && -; RUN: llvm-as < %s | llc -march=arm | grep movle +; RUN: llvm-as < %s | llc -march=arm | grep movle && +; RUN: llvm-as < %s | llc -march=arm | grep fcmpes && +; RUN: llvm-as < %s | llc -march=arm | grep fcmped int %f1(float %a) { entry: @@ -39,3 +41,10 @@ entry: %tmp = cast bool %tmp to int ; <int> [#uses=1] ret int %tmp } + +int %g1(double %a) { +entry: + %tmp = setlt double %a, 1.000000e+00 ; <bool> [#uses=1] + %tmp = cast bool %tmp to int ; <int> [#uses=1] + ret int %tmp +} |