diff options
Diffstat (limited to 'lib/CodeGen')
| -rw-r--r-- | lib/CodeGen/CGBuiltin.cpp | 298 | ||||
| -rw-r--r-- | lib/CodeGen/CodeGenFunction.h | 1 |
2 files changed, 299 insertions, 0 deletions
diff --git a/lib/CodeGen/CGBuiltin.cpp b/lib/CodeGen/CGBuiltin.cpp index a3d4af72da..cf5387a107 100644 --- a/lib/CodeGen/CGBuiltin.cpp +++ b/lib/CodeGen/CGBuiltin.cpp @@ -1380,6 +1380,11 @@ Value *CodeGenFunction::EmitTargetBuiltinExpr(unsigned BuiltinID, return EmitPPCBuiltinExpr(BuiltinID, E); case llvm::Triple::hexagon: return EmitHexagonBuiltinExpr(BuiltinID, E); + case llvm::Triple::mips: + case llvm::Triple::mipsel: + case llvm::Triple::mips64: + case llvm::Triple::mips64el: + return EmitMipsBuiltinExpr(BuiltinID, E); default: return 0; } @@ -5123,3 +5128,296 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID, } } } + +Value *CodeGenFunction::EmitMipsBuiltinExpr(unsigned BuiltinID, + const CallExpr *E) { + llvm::SmallVector<Value*, 4> Ops; + + for (unsigned i = 0, e = E->getNumArgs(); i != e; i++) + Ops.push_back(EmitScalarExpr(E->getArg(i))); + + Intrinsic::ID ID = Intrinsic::not_intrinsic; + + switch (BuiltinID) { + default: return 0; + case Mips::BI__builtin_mips_addu_qb: + ID = Intrinsic::mips_addu_qb; + break; + case Mips::BI__builtin_mips_addu_s_qb: + ID = Intrinsic::mips_addu_s_qb; + break; + case Mips::BI__builtin_mips_subu_qb: + ID = Intrinsic::mips_subu_qb; + break; + case Mips::BI__builtin_mips_subu_s_qb: + ID = Intrinsic::mips_subu_s_qb; + break; + case Mips::BI__builtin_mips_addq_ph: + ID = Intrinsic::mips_addq_ph; + break; + case Mips::BI__builtin_mips_addq_s_ph: + ID = Intrinsic::mips_addq_s_ph; + break; + case Mips::BI__builtin_mips_subq_ph: + ID = Intrinsic::mips_subq_ph; + break; + case Mips::BI__builtin_mips_subq_s_ph: + ID = Intrinsic::mips_subq_s_ph; + break; + case Mips::BI__builtin_mips_madd: + ID = Intrinsic::mips_madd; + break; + case Mips::BI__builtin_mips_maddu: + ID = Intrinsic::mips_maddu; + break; + case Mips::BI__builtin_mips_msub: + ID = Intrinsic::mips_msub; + break; + case Mips::BI__builtin_mips_msubu: + ID = Intrinsic::mips_msubu; + break; + case Mips::BI__builtin_mips_addq_s_w: + ID = Intrinsic::mips_addq_s_w; + break; + case Mips::BI__builtin_mips_subq_s_w: + ID = Intrinsic::mips_subq_s_w; + break; + case Mips::BI__builtin_mips_addsc: + ID = Intrinsic::mips_addsc; + break; + case Mips::BI__builtin_mips_addwc: + ID = Intrinsic::mips_addwc; + break; + case Mips::BI__builtin_mips_modsub: + ID = Intrinsic::mips_modsub; + break; + case Mips::BI__builtin_mips_raddu_w_qb: + ID = Intrinsic::mips_raddu_w_qb; + break; + case Mips::BI__builtin_mips_absq_s_ph: + ID = Intrinsic::mips_absq_s_ph; + break; + case Mips::BI__builtin_mips_absq_s_w: + ID = Intrinsic::mips_absq_s_w; + break; + case Mips::BI__builtin_mips_precrq_qb_ph: + ID = Intrinsic::mips_precrq_qb_ph; + break; + case Mips::BI__builtin_mips_precrqu_s_qb_ph: + ID = Intrinsic::mips_precrqu_s_qb_ph; + break; + case Mips::BI__builtin_mips_precrq_ph_w: + ID = Intrinsic::mips_precrq_ph_w; + break; + case Mips::BI__builtin_mips_precrq_rs_ph_w: + ID = Intrinsic::mips_precrq_rs_ph_w; + break; + case Mips::BI__builtin_mips_preceq_w_phl: + ID = Intrinsic::mips_preceq_w_phl; + break; + case Mips::BI__builtin_mips_preceq_w_phr: + ID = Intrinsic::mips_preceq_w_phr; + break; + case Mips::BI__builtin_mips_precequ_ph_qbl: + ID = Intrinsic::mips_precequ_ph_qbl; + break; + case Mips::BI__builtin_mips_precequ_ph_qbr: + ID = Intrinsic::mips_precequ_ph_qbr; + break; + case Mips::BI__builtin_mips_precequ_ph_qbla: + ID = Intrinsic::mips_precequ_ph_qbla; + break; + case Mips::BI__builtin_mips_precequ_ph_qbra: + ID = Intrinsic::mips_precequ_ph_qbra; + break; + case Mips::BI__builtin_mips_preceu_ph_qbl: + ID = Intrinsic::mips_preceu_ph_qbl; + break; + case Mips::BI__builtin_mips_preceu_ph_qbr: + ID = Intrinsic::mips_preceu_ph_qbr; + break; + case Mips::BI__builtin_mips_preceu_ph_qbla: + ID = Intrinsic::mips_preceu_ph_qbla; + break; + case Mips::BI__builtin_mips_preceu_ph_qbra: + ID = Intrinsic::mips_preceu_ph_qbra; + break; + case Mips::BI__builtin_mips_shll_qb: + ID = Intrinsic::mips_shll_qb; + break; + case Mips::BI__builtin_mips_shrl_qb: + ID = Intrinsic::mips_shrl_qb; + break; + case Mips::BI__builtin_mips_shll_ph: + ID = Intrinsic::mips_shll_ph; + break; + case Mips::BI__builtin_mips_shll_s_ph: + ID = Intrinsic::mips_shll_s_ph; + break; + case Mips::BI__builtin_mips_shra_ph: + ID = Intrinsic::mips_shra_ph; + break; + case Mips::BI__builtin_mips_shra_r_ph: + ID = Intrinsic::mips_shra_r_ph; + break; + case Mips::BI__builtin_mips_shll_s_w: + ID = Intrinsic::mips_shll_s_w; + break; + case Mips::BI__builtin_mips_shra_r_w: + ID = Intrinsic::mips_shra_r_w; + break; + case Mips::BI__builtin_mips_shilo: + ID = Intrinsic::mips_shilo; + break; + case Mips::BI__builtin_mips_muleu_s_ph_qbl: + ID = Intrinsic::mips_muleu_s_ph_qbl; + break; + case Mips::BI__builtin_mips_muleu_s_ph_qbr: + ID = Intrinsic::mips_muleu_s_ph_qbr; + break; + case Mips::BI__builtin_mips_mulq_rs_ph: + ID = Intrinsic::mips_mulq_rs_ph; + break; + case Mips::BI__builtin_mips_muleq_s_w_phl: + ID = Intrinsic::mips_muleq_s_w_phl; + break; + case Mips::BI__builtin_mips_muleq_s_w_phr: + ID = Intrinsic::mips_muleq_s_w_phr; + break; + case Mips::BI__builtin_mips_mulsaq_s_w_ph: + ID = Intrinsic::mips_mulsaq_s_w_ph; + break; + case Mips::BI__builtin_mips_maq_s_w_phl: + ID = Intrinsic::mips_maq_s_w_phl; + break; + case Mips::BI__builtin_mips_maq_s_w_phr: + ID = Intrinsic::mips_maq_s_w_phr; + break; + case Mips::BI__builtin_mips_maq_sa_w_phl: + ID = Intrinsic::mips_maq_sa_w_phl; + break; + case Mips::BI__builtin_mips_maq_sa_w_phr: + ID = Intrinsic::mips_maq_sa_w_phr; + break; + case Mips::BI__builtin_mips_mult: + ID = Intrinsic::mips_mult; + break; + case Mips::BI__builtin_mips_multu: + ID = Intrinsic::mips_multu; + break; + case Mips::BI__builtin_mips_dpau_h_qbl: + ID = Intrinsic::mips_dpau_h_qbl; + break; + case Mips::BI__builtin_mips_dpau_h_qbr: + ID = Intrinsic::mips_dpau_h_qbr; + break; + case Mips::BI__builtin_mips_dpsu_h_qbl: + ID = Intrinsic::mips_dpsu_h_qbl; + break; + case Mips::BI__builtin_mips_dpsu_h_qbr: + ID = Intrinsic::mips_dpsu_h_qbr; + break; + case Mips::BI__builtin_mips_dpaq_s_w_ph: + ID = Intrinsic::mips_dpaq_s_w_ph; + break; + case Mips::BI__builtin_mips_dpsq_s_w_ph: + ID = Intrinsic::mips_dpsq_s_w_ph; + break; + case Mips::BI__builtin_mips_dpaq_sa_l_w: + ID = Intrinsic::mips_dpaq_sa_l_w; + break; + case Mips::BI__builtin_mips_dpsq_sa_l_w: + ID = Intrinsic::mips_dpsq_sa_l_w; + break; + case Mips::BI__builtin_mips_cmpu_eq_qb: + ID = Intrinsic::mips_cmpu_eq_qb; + break; + case Mips::BI__builtin_mips_cmpu_lt_qb: + ID = Intrinsic::mips_cmpu_lt_qb; + break; + case Mips::BI__builtin_mips_cmpu_le_qb: + ID = Intrinsic::mips_cmpu_le_qb; + break; + case Mips::BI__builtin_mips_cmpgu_eq_qb: + ID = Intrinsic::mips_cmpgu_eq_qb; + break; + case Mips::BI__builtin_mips_cmpgu_lt_qb: + ID = Intrinsic::mips_cmpgu_lt_qb; + break; + case Mips::BI__builtin_mips_cmpgu_le_qb: + ID = Intrinsic::mips_cmpgu_le_qb; + break; + case Mips::BI__builtin_mips_cmp_eq_ph: + ID = Intrinsic::mips_cmp_eq_ph; + break; + case Mips::BI__builtin_mips_cmp_lt_ph: + ID = Intrinsic::mips_cmp_lt_ph; + break; + case Mips::BI__builtin_mips_cmp_le_ph: + ID = Intrinsic::mips_cmp_le_ph; + break; + case Mips::BI__builtin_mips_extr_s_h: + ID = Intrinsic::mips_extr_s_h; + break; + case Mips::BI__builtin_mips_extr_w: + ID = Intrinsic::mips_extr_w; + break; + case Mips::BI__builtin_mips_extr_rs_w: + ID = Intrinsic::mips_extr_rs_w; + break; + case Mips::BI__builtin_mips_extr_r_w: + ID = Intrinsic::mips_extr_r_w; + break; + case Mips::BI__builtin_mips_extp: + ID = Intrinsic::mips_extp; + break; + case Mips::BI__builtin_mips_extpdp: + ID = Intrinsic::mips_extpdp; + break; + case Mips::BI__builtin_mips_wrdsp: + ID = Intrinsic::mips_wrdsp; + break; + case Mips::BI__builtin_mips_rddsp: + ID = Intrinsic::mips_rddsp; + break; + case Mips::BI__builtin_mips_insv: + ID = Intrinsic::mips_insv; + break; + case Mips::BI__builtin_mips_bitrev: + ID = Intrinsic::mips_bitrev; + break; + case Mips::BI__builtin_mips_packrl_ph: + ID = Intrinsic::mips_packrl_ph; + break; + case Mips::BI__builtin_mips_repl_qb: + ID = Intrinsic::mips_repl_qb; + break; + case Mips::BI__builtin_mips_repl_ph: + ID = Intrinsic::mips_repl_ph; + break; + case Mips::BI__builtin_mips_pick_qb: + ID = Intrinsic::mips_pick_qb; + break; + case Mips::BI__builtin_mips_pick_ph: + ID = Intrinsic::mips_pick_ph; + break; + case Mips::BI__builtin_mips_mthlip: + ID = Intrinsic::mips_mthlip; + break; + case Mips::BI__builtin_mips_bposge32: + ID = Intrinsic::mips_bposge32; + break; + case Mips::BI__builtin_mips_lbux: + ID = Intrinsic::mips_lbux; + break; + case Mips::BI__builtin_mips_lhx: + ID = Intrinsic::mips_lhx; + break; + case Mips::BI__builtin_mips_lwx: + ID = Intrinsic::mips_lwx; + break; + } + + llvm::Function *F = CGM.getIntrinsic(ID); + return Builder.CreateCall(F, Ops, ""); +} diff --git a/lib/CodeGen/CodeGenFunction.h b/lib/CodeGen/CodeGenFunction.h index fd93fbbdd2..114730769b 100644 --- a/lib/CodeGen/CodeGenFunction.h +++ b/lib/CodeGen/CodeGenFunction.h @@ -2266,6 +2266,7 @@ public: llvm::Value *EmitX86BuiltinExpr(unsigned BuiltinID, const CallExpr *E); llvm::Value *EmitHexagonBuiltinExpr(unsigned BuiltinID, const CallExpr *E); llvm::Value *EmitPPCBuiltinExpr(unsigned BuiltinID, const CallExpr *E); + llvm::Value *EmitMipsBuiltinExpr(unsigned BuiltinID, const CallExpr *E); llvm::Value *EmitObjCProtocolExpr(const ObjCProtocolExpr *E); llvm::Value *EmitObjCStringLiteral(const ObjCStringLiteral *E); |