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authorChris Lattner <sabre@nondot.org>2010-07-13 19:41:32 +0000
committerChris Lattner <sabre@nondot.org>2010-07-13 19:41:32 +0000
commit90a8f27f144233b53cac0c88a1595f7f05105b7e (patch)
treea3ef6406b2b4ac33704047c7ae3a8188a7200640 /lib/Sema/SemaExpr.cpp
parent3d4b482b5f2cacc7686f65bb231ad666a5adad4a (diff)
Add a warning to catch a bug recently caught by code review, like this:
t2.c:2:12: warning: use of logical && with constant operand; switch to bitwise & or remove constant [-Wlogical-bitwise-confusion] return x && 4; ^ ~ wording improvement suggestions are welcome. git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@108260 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Sema/SemaExpr.cpp')
-rw-r--r--lib/Sema/SemaExpr.cpp18
1 files changed, 16 insertions, 2 deletions
diff --git a/lib/Sema/SemaExpr.cpp b/lib/Sema/SemaExpr.cpp
index 5d53ddeb98..cb3518ae83 100644
--- a/lib/Sema/SemaExpr.cpp
+++ b/lib/Sema/SemaExpr.cpp
@@ -5735,7 +5735,21 @@ inline QualType Sema::CheckBitwiseOperands(
}
inline QualType Sema::CheckLogicalOperands( // C99 6.5.[13,14]
- Expr *&lex, Expr *&rex, SourceLocation Loc) {
+ Expr *&lex, Expr *&rex, SourceLocation Loc, unsigned Opc) {
+
+ // Diagnose cases where the user write a logical and/or but probably meant a
+ // bitwise one. We do this when the LHS is a non-bool integer and the RHS
+ // is a constant.
+ if (lex->getType()->isIntegerType() && !lex->getType()->isBooleanType() &&
+ rex->getType()->isIntegerType() && rex->isEvaluatable(Context) &&
+ !Loc.isMacroID())
+ Diag(Loc, diag::warn_logical_instead_of_bitwise)
+ << rex->getSourceRange()
+ << (Opc == BinaryOperator::LAnd ? "&&" : "||")
+ << (Opc == BinaryOperator::LAnd ? "&" : "|");
+
+
+
if (!Context.getLangOptions().CPlusPlus) {
UsualUnaryConversions(lex);
UsualUnaryConversions(rex);
@@ -6363,7 +6377,7 @@ Action::OwningExprResult Sema::CreateBuiltinBinOp(SourceLocation OpLoc,
break;
case BinaryOperator::LAnd:
case BinaryOperator::LOr:
- ResultTy = CheckLogicalOperands(lhs, rhs, OpLoc);
+ ResultTy = CheckLogicalOperands(lhs, rhs, OpLoc, Opc);
break;
case BinaryOperator::MulAssign:
case BinaryOperator::DivAssign: