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| author | Bob Wilson <bob.wilson@apple.com> | 2010-12-09 18:58:31 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-12-09 18:58:31 +0000 |
| commit | 2427dbfa880a72fa3dcba700cf587fb5d8b3cf57 (patch) | |
| tree | b91622fdb64b0a36210f48c492f87108b4e0daf2 /lib/Sema/SemaCodeComplete.cpp | |
| parent | c9ccad380f858c511756e2d8cd55058d8fc6fbcb (diff) | |
Fix type of last vector operand of Neon quad-register multiple-lane intrinsics.
The sensible thing would be to have these intrinsics take all quad-register
vector operands, but that's not what ARM did. They made the last vector
operand always be a double-register type. Since the lane number
must be a constant, the user can know which half of a quad-register contains
that lane, extract the high or low half of the vector, and adjust the lane
number accordingly. The only advantage I can see for this is that it works
better when you want to multiply a quad-register value by a lane from a
double-register value, but I wouldn't have expected that to be the common
case. Oh well -- at this point we just need to follow the spec.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@121397 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Sema/SemaCodeComplete.cpp')
0 files changed, 0 insertions, 0 deletions