Slightly revised handling of mult-alt constraints, to avoid an assert, until we have the full fix.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@110706 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 48 insertions, 5 deletions

diff --git a/lib/Basic/TargetInfo.cpp b/lib/Basic/TargetInfo.cpp
index 7fcf372a36..05db02a9fe 100644
--- a/lib/Basic/TargetInfo.cpp
+++ b/lib/Basic/TargetInfo.cpp
@@ -287,8 +287,17 @@ bool TargetInfo::validateOutputConstraint(ConstraintInfo &Info) const {
       Info.setAllowsRegister();
       Info.setAllowsMemory();
       break;
-    case ',': // FIXME: Until we handle multiple alternative constraints,
-      return true;  // ignore everything after the first comma.
+    case ',': // multiple alternative constraint.  Pass it.
+      Name++;
+      // An output constraint must start with '=' or '+'
+      if (*Name != '=' && *Name != '+')
+        return false;
+      if (*Name == '+')
+        Info.setIsReadWrite();
+      break;
+    case '?': // Disparage slightly code.
+    case '!': // Disparage severly.
+      break;  // Pass them.
     }
 
     Name++;
@@ -382,8 +391,11 @@ bool TargetInfo::validateInputConstraint(ConstraintInfo *OutputConstraints,
       Info.setAllowsRegister();
       Info.setAllowsMemory();
       break;
-    case ',': // FIXME: Until we handle multiple alternative constraints,
-      return true;  // ignore everything after the first comma.
+    case ',': // multiple alternative constraint.  Ignore comma.
+      break;
+    case '?': // Disparage slightly code.
+    case '!': // Disparage severly.
+      break;  // Pass them.
     }
 
     Name++;
diff --git a/lib/CodeGen/CGStmt.cpp b/lib/CodeGen/CGStmt.cpp
index 3bbecfa59c..6dad8597a8 100644
--- a/lib/CodeGen/CGStmt.cpp
+++ b/lib/CodeGen/CGStmt.cpp
@@ -861,16 +861,24 @@ static std::string
 SimplifyConstraint(const char *Constraint, const TargetInfo &Target,
                  llvm::SmallVectorImpl<TargetInfo::ConstraintInfo> *OutCons=0) {
   std::string Result;
+  std::string tmp;
 
   while (*Constraint) {
     switch (*Constraint) {
     default:
-      Result += Target.convertConstraint(*Constraint);
+      tmp = Target.convertConstraint(*Constraint);
+      if (Result.find(tmp) == std::string::npos) // Combine unique constraints
+        Result += tmp;
       break;
     // Ignore these
     case '*':
     case '?':
     case '!':
+    case '=': // Will see this and the following in mult-alt constraints.
+    case '+':
+      break;
+    case ',':			// FIXME - Until the back-end properly supports
+		return Result;	// multiple alternative constraints, we stop here.
       break;
     case 'g':
       Result += "imr";
diff --git a/test/CodeGen/asm-inout.c b/test/CodeGen/asm-inout.c
index f04276693e..b67540436c 100644
--- a/test/CodeGen/asm-inout.c
+++ b/test/CodeGen/asm-inout.c
@@ -17,3 +17,26 @@ void test2() {
   // CHECK: store i32 {{%[a-zA-Z0-9\.]+}}, i32* [[REGCALLRESULT]]
   asm ("foobar" : "+r"(*foo()));
 }
+
+// PR7338
+// CHECK: @test3
+void test3(int *vout, int vin)
+{
+  // CHECK: entry:
+  // CHECK: [[REGCALLRESULT1:%[a-zA-Z0-9\.]+]] = alloca i32*, align 4               ; <i32**> [#uses=2]
+  // CHECK: [[REGCALLRESULT2:%[a-zA-Z0-9\.]+]] = alloca i32, align 4                 ; <i32*> [#uses=2]
+  // CHECK: store i32* [[REGCALLRESULT5:%[a-zA-Z0-9\.]+]], i32** [[REGCALLRESULT1]]
+  // CHECK: store i32 [[REGCALLRESULT6:%[a-zA-Z0-9\.]+]], i32* [[REGCALLRESULT2]]
+  // CHECK: [[REGCALLRESULT3:%[a-zA-Z0-9\.]+]] = load i32** [[REGCALLRESULT1]]                    ; <i32*> [#uses=1]
+  // CHECK: [[REGCALLRESULT4:%[a-zA-Z0-9\.]+]] = load i32* [[REGCALLRESULT2]]                     ; <i32> [#uses=1]
+  //  The following is disabled until mult-alt constraint support is enabled.
+  //  call void asm "opr $0,$1", "=*rm,rm,~{di},~{dirflag},~{fpsr},~{flags}"(i32* [[REGCALLRESULT3]], i32 [[REGCALLRESULT4]]) nounwind,
+  //  Delete the following line when mult-alt constraint support is enabled.
+  // CHECK: call void asm "opr $0,$1", "=*r,r,~{di},~{dirflag},~{fpsr},~{flags}"(i32* [[REGCALLRESULT3]], i32 [[REGCALLRESULT4]]) nounwind,
+asm(
+		"opr %[vout],%[vin]"
+		: [vout] "=r,=m,=r" (*vout)
+		: [vin] "r,m,r" (vin)
+		: "edi"
+		);
+}