Update to use references to attribute groups instead of listing the attributes on the call/invoke instructions.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@175878 91177308-0d34-0410-b5e6-96231b3b80d8

38 files changed, 308 insertions, 243 deletions

diff --git a/test/CXX/except/except.spec/p14-ir.cpp b/test/CXX/except/except.spec/p14-ir.cpp
index 81fbf7d970..9b41f3d1bc 100644
--- a/test/CXX/except/except.spec/p14-ir.cpp
+++ b/test/CXX/except/except.spec/p14-ir.cpp
@@ -27,12 +27,12 @@ struct X5 : X0, X4 { };
 
 void test(X2 x2, X3 x3, X5 x5) {
   // CHECK: define linkonce_odr void @_ZN2X2C1ERKS_(%struct.X2* %this, %struct.X2*) unnamed_addr
-  // CHECK:      call void @_ZN2X2C2ERKS_({{.*}}) nounwind
+  // CHECK:      call void @_ZN2X2C2ERKS_({{.*}}) [[NUW:#[0-9]+]]
   // CHECK-NEXT: ret void
   // CHECK-NEXT: }
   X2 x2a(x2);
   // CHECK: define linkonce_odr void @_ZN2X3C1ERKS_(%struct.X3* %this, %struct.X3*) unnamed_addr
-  // CHECK:      call void @_ZN2X3C2ERKS_({{.*}}) nounwind
+  // CHECK:      call void @_ZN2X3C2ERKS_({{.*}}) [[NUW]]
   // CHECK-NEXT: ret void
   // CHECK-NEXT: }
   X3 x3a(x3);
@@ -56,7 +56,7 @@ struct X9 : X6, X7 { };
 
 void test() {
   // CHECK: define linkonce_odr void @_ZN2X8C1Ev(%struct.X8* %this) unnamed_addr
-  // CHECK:      call void @_ZN2X8C2Ev({{.*}}) nounwind
+  // CHECK:      call void @_ZN2X8C2Ev({{.*}}) [[NUW]]
   // CHECK-NEXT: ret void
   X8();
 
@@ -67,13 +67,15 @@ void test() {
   X9();
 
   // CHECK: define linkonce_odr void @_ZN2X9C2Ev(%struct.X9* %this) unnamed_addr
-  // CHECK:      call void @_ZN2X6C2Ev({{.*}}) nounwind
+  // CHECK:      call void @_ZN2X6C2Ev({{.*}}) [[NUW]]
   //   FIXME: and here:
   // CHECK-NEXT: bitcast
   // CHECK-NEXT: call void @_ZN2X7C2Ev({{.*}})
   // CHECK: ret void
 
   // CHECK: define linkonce_odr void @_ZN2X8C2Ev(%struct.X8* %this) unnamed_addr
-  // CHECK:      call void @_ZN2X6C2Ev({{.*}}) nounwind
+  // CHECK:      call void @_ZN2X6C2Ev({{.*}}) [[NUW]]
   // CHECK-NEXT: ret void
 }
+
+// CHECK: attributes [[NUW]] = { nounwind{{.*}} }
diff --git a/test/CXX/except/except.spec/p9-noexcept.cpp b/test/CXX/except/except.spec/p9-noexcept.cpp
index 0e592ce001..3fd45c55da 100644
--- a/test/CXX/except/except.spec/p9-noexcept.cpp
+++ b/test/CXX/except/except.spec/p9-noexcept.cpp
@@ -10,7 +10,7 @@ void target() noexcept
 // CHECK:      [[T0:%.*]] = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*)
 // CHECK-NEXT:  catch i8* null
 // CHECK-NEXT: [[T1:%.*]] = extractvalue { i8*, i32 } [[T0]], 0
-// CHECK-NEXT: call void @__clang_call_terminate(i8* [[T1]]) noreturn nounwind
+// CHECK-NEXT: call void @__clang_call_terminate(i8* [[T1]]) [[NR_NUW:#[0-9]+]]
 // CHECK-NEXT: unreachable
 
 void reverse() noexcept(false)
@@ -18,3 +18,5 @@ void reverse() noexcept(false)
   // CHECK: call void @_Z8externalv()
   external();
 }
+
+// CHECK: attributes [[NR_NUW]] = { noreturn nounwind }
diff --git a/test/CodeGen/builtin-attributes.c b/test/CodeGen/builtin-attributes.c
index 1d3a94376d..79026cb54b 100644
--- a/test/CodeGen/builtin-attributes.c
+++ b/test/CodeGen/builtin-attributes.c
@@ -12,7 +12,7 @@ void f1() {
   exit(1);
 }
 
-// CHECK: call i8* @strstr{{.*}} nounwind
+// CHECK: call i8* @strstr{{.*}} [[NUW:#[0-9]+]]
 char* f2(char* a, char* b) {
   return __builtin_strstr(a, b);
 }
@@ -57,3 +57,6 @@ int f3(double x) {
   __builtin_remquol(x, x, &e);
   return e;
 }
+
+// CHECK: attributes [[NUW]] = { nounwind }
+// CHECK: attributes #1 = { noreturn }
diff --git a/test/CodeGen/catch-undef-behavior.c b/test/CodeGen/catch-undef-behavior.c
index 2901a0155e..cd86dd5a60 100644
--- a/test/CodeGen/catch-undef-behavior.c
+++ b/test/CodeGen/catch-undef-behavior.c
@@ -58,7 +58,7 @@ void foo() {
   // CHECK:      %[[ARG:.*]] = ptrtoint {{.*}} %[[PTR]] to i64
   // CHECK-NEXT: call void @__ubsan_handle_type_mismatch(i8* bitcast ({{.*}} @[[LINE_100]] to i8*), i64 %[[ARG]])
 
-  // CHECK-TRAP:      call void @llvm.trap() noreturn nounwind
+  // CHECK-TRAP:      call void @llvm.trap() [[NR_NUW:#[0-9]+]]
   // CHECK-TRAP-NEXT: unreachable
 
   // With -fsanitize=null, only perform the null check.
@@ -89,7 +89,7 @@ int bar(int *a) {
   // CHECK:      %[[ARG:.*]] = ptrtoint
   // CHECK-NEXT: call void @__ubsan_handle_type_mismatch(i8* bitcast ({{.*}} @[[LINE_200]] to i8*), i64 %[[ARG]])
 
-  // CHECK-TRAP:      call void @llvm.trap() noreturn nounwind
+  // CHECK-TRAP:      call void @llvm.trap() [[NR_NUW]]
   // CHECK-TRAP-NEXT: unreachable
 
 #line 200
@@ -116,7 +116,7 @@ int lsh_overflow(int a, int b) {
   // CHECK-NEXT: %[[ARG2:.*]] = zext
   // CHECK-NEXT: call void @__ubsan_handle_shift_out_of_bounds(i8* bitcast ({{.*}} @[[LINE_300_A]] to i8*), i64 %[[ARG1]], i64 %[[ARG2]])
 
-  // CHECK-TRAP:      call void @llvm.trap() noreturn nounwind
+  // CHECK-TRAP:      call void @llvm.trap() [[NR_NUW]]
   // CHECK-TRAP-NEXT: unreachable
 
   // CHECK:      %[[SHIFTED_OUT_WIDTH:.*]] = sub nuw nsw i32 31, %[[RHS]]
@@ -133,7 +133,7 @@ int lsh_overflow(int a, int b) {
   // CHECK-NEXT: %[[ARG2:.*]] = zext
   // CHECK-NEXT: call void @__ubsan_handle_shift_out_of_bounds(i8* bitcast ({{.*}} @[[LINE_300_B]] to i8*), i64 %[[ARG1]], i64 %[[ARG2]])
 
-  // CHECK-TRAP:      call void @llvm.trap() noreturn nounwind
+  // CHECK-TRAP:      call void @llvm.trap() [[NR_NUW]]
   // CHECK-TRAP-NEXT: unreachable
 
   // CHECK:      %[[RET:.*]] = shl i32 %[[LHS]], %[[RHS]]
@@ -158,7 +158,7 @@ int rsh_inbounds(int a, int b) {
   // CHECK-NEXT: %[[ARG2:.*]] = zext
   // CHECK-NEXT: call void @__ubsan_handle_shift_out_of_bounds(i8* bitcast ({{.*}} @[[LINE_400]] to i8*), i64 %[[ARG1]], i64 %[[ARG2]])
 
-  // CHECK-TRAP:      call void @llvm.trap() noreturn nounwind
+  // CHECK-TRAP:      call void @llvm.trap() [[NR_NUW]]
   // CHECK-TRAP-NEXT: unreachable
 
   // CHECK:      %[[RET:.*]] = ashr i32 %[[LHS]], %[[RHS]]
@@ -175,7 +175,7 @@ int rsh_inbounds(int a, int b) {
 int load(int *p) {
   // CHECK: call void @__ubsan_handle_type_mismatch(i8* bitcast ({{.*}} @[[LINE_500]] to i8*), i64 %{{.*}})
 
-  // CHECK-TRAP:      call void @llvm.trap() noreturn nounwind
+  // CHECK-TRAP:      call void @llvm.trap() [[NR_NUW]]
   // CHECK-TRAP-NEXT: unreachable
 #line 500
   return *p;
@@ -186,7 +186,7 @@ int load(int *p) {
 void store(int *p, int q) {
   // CHECK: call void @__ubsan_handle_type_mismatch(i8* bitcast ({{.*}} @[[LINE_600]] to i8*), i64 %{{.*}})
 
-  // CHECK-TRAP:      call void @llvm.trap() noreturn nounwind
+  // CHECK-TRAP:      call void @llvm.trap() [[NR_NUW]]
   // CHECK-TRAP-NEXT: unreachable
 #line 600
   *p = q;
@@ -199,7 +199,7 @@ struct S { int k; };
 int *member_access(struct S *p) {
   // CHECK: call void @__ubsan_handle_type_mismatch(i8* bitcast ({{.*}} @[[LINE_700]] to i8*), i64 %{{.*}})
 
-  // CHECK-TRAP:      call void @llvm.trap() noreturn nounwind
+  // CHECK-TRAP:      call void @llvm.trap() [[NR_NUW]]
   // CHECK-TRAP-NEXT: unreachable
 #line 700
   return &p->k;
@@ -212,7 +212,7 @@ int signed_overflow(int a, int b) {
   // CHECK-NEXT: %[[ARG2:.*]] = zext
   // CHECK-NEXT: call void @__ubsan_handle_add_overflow(i8* bitcast ({{.*}} @[[LINE_800]] to i8*), i64 %[[ARG1]], i64 %[[ARG2]])
 
-  // CHECK-TRAP:      call void @llvm.trap() noreturn nounwind
+  // CHECK-TRAP:      call void @llvm.trap() [[NR_NUW]]
   // CHECK-TRAP-NEXT: unreachable
 #line 800
   return a + b;
@@ -259,7 +259,7 @@ float int_float_overflow(unsigned __int128 n) {
   // CHECK-TRAP: %[[INBOUNDS:.*]] = icmp ule i128 %{{.*}}, -20282409603651670423947251286016
   // CHECK-TRAP-NEXT: br i1 %[[INBOUNDS]]
 
-  // CHECK-TRAP:      call void @llvm.trap() noreturn nounwind
+  // CHECK-TRAP:      call void @llvm.trap() [[NR_NUW]]
   // CHECK-TRAP-NEXT: unreachable
   return n;
 }
@@ -277,7 +277,7 @@ void int_fp16_overflow(int n, __fp16 *p) {
   // CHECK-TRAP: %[[INBOUNDS:.*]] = and i1 %[[GE]], %[[LE]]
   // CHECK-TRAP-NEXT: br i1 %[[INBOUNDS]]
 
-  // CHECK-TRAP:      call void @llvm.trap() noreturn nounwind
+  // CHECK-TRAP:      call void @llvm.trap() [[NR_NUW]]
   // CHECK-TRAP-NEXT: unreachable
   *p = n;
 }
@@ -295,7 +295,7 @@ int float_int_overflow(float f) {
   // CHECK-TRAP: %[[INBOUNDS:.*]] = and i1 %[[GE]], %[[LE]]
   // CHECK-TRAP-NEXT: br i1 %[[INBOUNDS]]
 
-  // CHECK-TRAP:      call void @llvm.trap() noreturn nounwind
+  // CHECK-TRAP:      call void @llvm.trap() [[NR_NUW]]
   // CHECK-TRAP-NEXT: unreachable
   return f;
 }
@@ -313,7 +313,7 @@ unsigned float_uint_overflow(float f) {
   // CHECK-TRAP: %[[INBOUNDS:.*]] = and i1 %[[GE]], %[[LE]]
   // CHECK-TRAP-NEXT: br i1 %[[INBOUNDS]]
 
-  // CHECK-TRAP:      call void @llvm.trap() noreturn nounwind
+  // CHECK-TRAP:      call void @llvm.trap() [[NR_NUW]]
   // CHECK-TRAP-NEXT: unreachable
   return f;
 }
@@ -331,7 +331,7 @@ signed char fp16_char_overflow(__fp16 *p) {
   // CHECK-TRAP: %[[INBOUNDS:.*]] = and i1 %[[GE]], %[[LE]]
   // CHECK-TRAP-NEXT: br i1 %[[INBOUNDS]]
 
-  // CHECK-TRAP:      call void @llvm.trap() noreturn nounwind
+  // CHECK-TRAP:      call void @llvm.trap() [[NR_NUW]]
   // CHECK-TRAP-NEXT: unreachable
   return *p;
 }
@@ -349,7 +349,7 @@ float float_float_overflow(double f) {
   // CHECK-TRAP: %[[INBOUNDS:.*]] = and i1 %[[GE]], %[[LE]]
   // CHECK-TRAP-NEXT: br i1 %[[INBOUNDS]]
 
-  // CHECK-TRAP:      call void @llvm.trap() noreturn nounwind
+  // CHECK-TRAP:      call void @llvm.trap() [[NR_NUW]]
   // CHECK-TRAP-NEXT: unreachable
   return f;
 }
@@ -381,7 +381,7 @@ int int_divide_overflow(int a, int b) {
   // CHECK-TRAP:          %[[OK:.*]] = and i1 %[[ZERO]], %[[OVER]]
   // CHECK-TRAP:          br i1 %[[OK]]
 
-  // CHECK-TRAP: call void @llvm.trap() noreturn nounwind
+  // CHECK-TRAP: call void @llvm.trap() [[NR_NUW]]
   // CHECK-TRAP: unreachable
   return a / b;
 
@@ -399,9 +399,11 @@ _Bool sour_bool(_Bool *p) {
   // CHECK-TRAP: %[[OK:.*]] = icmp ule i8 {{.*}}, 1
   // CHECK-TRAP: br i1 %[[OK]]
 
-  // CHECK-TRAP: call void @llvm.trap() noreturn nounwind
+  // CHECK-TRAP: call void @llvm.trap() [[NR_NUW]]
   // CHECK-TRAP: unreachable
   return *p;
 }
 
 // CHECK: ![[WEIGHT_MD]] = metadata !{metadata !"branch_weights", i32 1048575, i32 1}
+
+// CHECK-TRAP: attributes [[NR_NUW]] = { noreturn nounwind }
diff --git a/test/CodeGen/function-attributes.c b/test/CodeGen/function-attributes.c
index 1d685c2465..1d1be90c7a 100644
--- a/test/CodeGen/function-attributes.c
+++ b/test/CodeGen/function-attributes.c
@@ -30,20 +30,20 @@ void f7(unsigned short x) { }
 void __attribute__((always_inline)) f8(void) { }
 
 // CHECK: call void @f9_t()
-// CHECK: noreturn
+// CHECK: #2
 // CHECK: }
 void __attribute__((noreturn)) f9_t(void);
 void f9(void) { f9_t(); }
 
 // CHECK: call void @f9a()
-// CHECK: noreturn
+// CHECK: #2
 // CHECK: }
 _Noreturn void f9a(void);
 void f9b(void) { f9a(); }
 
 // FIXME: We should be setting nounwind on calls.
 // CHECK: call i32 @f10_t()
-// CHECK: readnone
+// CHECK: #0
 // CHECK: {
 int __attribute__((const)) f10_t(void);
 int f10(void) { return f10_t(); }
@@ -99,7 +99,7 @@ void __attribute__((force_align_arg_pointer)) f16(void) {
 // CHECK: #7
 // CHECK: {
 // CHECK: call void @f17()
-// CHECK: returns_twice
+// CHECK: #7
 // CHECK: ret void
 __attribute__ ((returns_twice)) void f17(void);
 __attribute__ ((returns_twice)) void f18(void) {
@@ -109,7 +109,7 @@ __attribute__ ((returns_twice)) void f18(void) {
 // CHECK: define void @f19()
 // CHECK: {
 // CHECK: call i32 @setjmp(i32* null)
-// CHECK: returns_twice
+// CHECK: #7
 // CHECK: ret void
 typedef int jmp_buf[((9 * 2) + 3 + 16)];
 int setjmp(jmp_buf);
diff --git a/test/CodeGen/mips-constraint-regs.c b/test/CodeGen/mips-constraint-regs.c
index ea063b50d5..c42a888fcf 100644
--- a/test/CodeGen/mips-constraint-regs.c
+++ b/test/CodeGen/mips-constraint-regs.c
@@ -11,7 +11,7 @@ int main()
   // 'c': 16 bit address register for Mips16, GPR for all others
   // I am using 'c' to constrain both the target and one of the source
   // registers. We are looking for syntactical correctness.
-  // CHECK: %{{[0-9]+}} = call i32 asm sideeffect "addi $0,$1,$2 \0A\09\09", "=c,c,I"(i32 %{{[0-9]+}}, i32 %{{[0-9]+}}) nounwind, !srcloc !{{[0-9]+}}
+  // CHECK: %{{[0-9]+}} = call i32 asm sideeffect "addi $0,$1,$2 \0A\09\09", "=c,c,I"(i32 %{{[0-9]+}}, i32 %{{[0-9]+}}) [[NUW:#[0-9]+]], !srcloc !{{[0-9]+}}
   int __s, __v = 17;
   int __t;
   __asm__ __volatile__(
@@ -22,7 +22,7 @@ int main()
   // 'l': lo register
   // We are making it clear that destination register is lo with the
   // use of the 'l' constraint ("=l").
-  // CHECK:   %{{[0-9]+}} = call i32 asm sideeffect "mtlo $1 \0A\09\09", "=l,r,~{lo}"(i32 %{{[0-9]+}}) nounwind, !srcloc !{{[0-9]+}}
+  // CHECK:   %{{[0-9]+}} = call i32 asm sideeffect "mtlo $1 \0A\09\09", "=l,r,~{lo}"(i32 %{{[0-9]+}}) [[NUW]], !srcloc !{{[0-9]+}}
   int i_temp = 44;
   int i_result;
   __asm__ __volatile__(
@@ -34,7 +34,7 @@ int main()
   // 'x': Combined lo/hi registers
   // We are specifying that destination registers are the hi/lo pair with the
   // use of the 'x' constraint ("=x").
-  // CHECK:  %{{[0-9]+}} = call i64 asm sideeffect "mthi $1 \0A\09\09mtlo $2 \0A\09\09", "=x,r,r"(i32 %{{[0-9]+}}, i32 %{{[0-9]+}}) nounwind, !srcloc !{{[0-9]+}}
+  // CHECK:  %{{[0-9]+}} = call i64 asm sideeffect "mthi $1 \0A\09\09mtlo $2 \0A\09\09", "=x,r,r"(i32 %{{[0-9]+}}, i32 %{{[0-9]+}}) [[NUW]], !srcloc !{{[0-9]+}}
   int i_hi = 3;
   int i_lo = 2;
   long long ll_result = 0;
@@ -47,3 +47,5 @@ int main()
 
   return 0;
 }
+
+// CHECK: attributes [[NUW]] = { nounwind }
diff --git a/test/CodeGen/ms-declspecs.c b/test/CodeGen/ms-declspecs.c
index 74bf8ad1a5..fea2cf6747 100644
--- a/test/CodeGen/ms-declspecs.c
+++ b/test/CodeGen/ms-declspecs.c
@@ -18,11 +18,11 @@ void t22() {}
 // CHECK: define void @t2() #2 {
 __declspec(noinline) void t2() {}
 
-// CHECK: call void @f20_t() noreturn
+// CHECK: call void @f20_t() [[NR:#[0-9]+]]
 __declspec(noreturn) void f20_t(void);
 void f20(void) { f20_t(); }
 
 // CHECK: attributes #0 = { naked noinline nounwind "target-features"={{.*}} }
 // CHECK: attributes #1 = { nounwind "target-features"={{.*}} }
 // CHECK: attributes #2 = { noinline nounwind "target-features"={{.*}} }
-// CHECK: attributes #3 = { noreturn "target-features"={{.*}} }
+// CHECK: attributes [[NR]] = { noreturn "target-features"={{.*}} }
diff --git a/test/CodeGen/ms-inline-asm-64.c b/test/CodeGen/ms-inline-asm-64.c
index d700f01f04..8d2940d4e0 100644
--- a/test/CodeGen/ms-inline-asm-64.c
+++ b/test/CodeGen/ms-inline-asm-64.c
@@ -5,12 +5,14 @@ void t1() {
   int var = 10;
   __asm mov rax, offset var ; rax = address of myvar
 // CHECK: t1
-// CHECK: call void asm sideeffect inteldialect "mov rax, $0", "r,~{rax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}) nounwind
+// CHECK: call void asm sideeffect inteldialect "mov rax, $0", "r,~{rax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}) [[NUW:#[0-9]+]]
 }
 
 void t2() {
   int var = 10;
   __asm mov [eax], offset var
 // CHECK: t2
-// CHECK: call void asm sideeffect inteldialect "mov [eax], $0", "r,~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}) nounwind
+// CHECK: call void asm sideeffect inteldialect "mov [eax], $0", "r,~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}) [[NUW]]
 }
+
+// CHECK: attributes [[NUW]] = { nounwind }
diff --git a/test/CodeGen/ms-inline-asm.c b/test/CodeGen/ms-inline-asm.c
index 2283a50987..64b12aa0f8 100644
--- a/test/CodeGen/ms-inline-asm.c
+++ b/test/CodeGen/ms-inline-asm.c
@@ -3,16 +3,16 @@
 
 void t1() {
 // CHECK: @t1
-// CHECK: call void asm sideeffect inteldialect "", "~{dirflag},~{fpsr},~{flags}"() nounwind
+// CHECK: call void asm sideeffect inteldialect "", "~{dirflag},~{fpsr},~{flags}"() [[NUW:#[0-9]+]]
 // CHECK: ret void
   __asm {}
 }
 
 void t2() {
 // CHECK: @t2
-// CHECK: call void asm sideeffect inteldialect "nop", "~{dirflag},~{fpsr},~{flags}"() nounwind
-// CHECK: call void asm sideeffect inteldialect "nop", "~{dirflag},~{fpsr},~{flags}"() nounwind
-// CHECK: call void asm sideeffect inteldialect "nop", "~{dirflag},~{fpsr},~{flags}"() nounwind
+// CHECK: call void asm sideeffect inteldialect "nop", "~{dirflag},~{fpsr},~{flags}"() [[NUW]]
+// CHECK: call void asm sideeffect inteldialect "nop", "~{dirflag},~{fpsr},~{flags}"() [[NUW]]
+// CHECK: call void asm sideeffect inteldialect "nop", "~{dirflag},~{fpsr},~{flags}"() [[NUW]]
 // CHECK: ret void
   __asm nop
   __asm nop
@@ -21,15 +21,15 @@ void t2() {
 
 void t3() {
 // CHECK: @t3
-// CHECK: call void asm sideeffect inteldialect "nop\0A\09nop\0A\09nop", "~{dirflag},~{fpsr},~{flags}"() nounwind
+// CHECK: call void asm sideeffect inteldialect "nop\0A\09nop\0A\09nop", "~{dirflag},~{fpsr},~{flags}"() [[NUW]]
 // CHECK: ret void
   __asm nop __asm nop __asm nop
 }
 
 void t4(void) {
 // CHECK: @t4
-// CHECK: call void asm sideeffect inteldialect "mov ebx, eax", "~{ebx},~{dirflag},~{fpsr},~{flags}"() nounwind
-// CHECK: call void asm sideeffect inteldialect "mov ecx, ebx", "~{ecx},~{dirflag},~{fpsr},~{flags}"() nounwind
+// CHECK: call void asm sideeffect inteldialect "mov ebx, eax", "~{ebx},~{dirflag},~{fpsr},~{flags}"() [[NUW]]
+// CHECK: call void asm sideeffect inteldialect "mov ecx, ebx", "~{ecx},~{dirflag},~{fpsr},~{flags}"() [[NUW]]
 // CHECK: ret void
   __asm mov ebx, eax
   __asm mov ecx, ebx
@@ -37,7 +37,7 @@ void t4(void) {
 
 void t5(void) {
 // CHECK: @t5
-// CHECK: call void asm sideeffect inteldialect "mov ebx, eax\0A\09mov ecx, ebx", "~{ebx},~{ecx},~{dirflag},~{fpsr},~{flags}"() nounwind
+// CHECK: call void asm sideeffect inteldialect "mov ebx, eax\0A\09mov ecx, ebx", "~{ebx},~{ecx},~{dirflag},~{fpsr},~{flags}"() [[NUW]]
 // CHECK: ret void
   __asm mov ebx, eax __asm mov ecx, ebx
 }
@@ -45,7 +45,7 @@ void t5(void) {
 void t6(void) {
   __asm int 0x2c
 // CHECK: t6
-// CHECK: call void asm sideeffect inteldialect "int $$0x2c", "~{dirflag},~{fpsr},~{flags}"() nounwind
+// CHECK: call void asm sideeffect inteldialect "int $$0x2c", "~{dirflag},~{fpsr},~{flags}"() [[NUW]]
 }
 
 void t7() {
@@ -54,8 +54,8 @@ void t7() {
   }
   __asm {}
 // CHECK: t7
-// CHECK: call void asm sideeffect inteldialect "int $$0x2c", "~{dirflag},~{fpsr},~{flags}"() nounwind
-// CHECK: call void asm sideeffect inteldialect "", "~{dirflag},~{fpsr},~{flags}"() nounwind
+// CHECK: call void asm sideeffect inteldialect "int $$0x2c", "~{dirflag},~{fpsr},~{flags}"() [[NUW]]
+// CHECK: call void asm sideeffect inteldialect "", "~{dirflag},~{fpsr},~{flags}"() [[NUW]]
 }
 
 int t8() {
@@ -64,9 +64,9 @@ int t8() {
   __asm int 4
   return 10;
 // CHECK: t8
-// CHECK: call void asm sideeffect inteldialect "int $$4", "~{dirflag},~{fpsr},~{flags}"() nounwind
-// CHECK: call void asm sideeffect inteldialect "", "~{dirflag},~{fpsr},~{flags}"() nounwind
-// CHECK: call void asm sideeffect inteldialect "int $$4", "~{dirflag},~{fpsr},~{flags}"() nounwind
+// CHECK: call void asm sideeffect inteldialect "int $$4", "~{dirflag},~{fpsr},~{flags}"() [[NUW]]
+// CHECK: call void asm sideeffect inteldialect "", "~{dirflag},~{fpsr},~{flags}"() [[NUW]]
+// CHECK: call void asm sideeffect inteldialect "int $$4", "~{dirflag},~{fpsr},~{flags}"() [[NUW]]
 // CHECK: ret i32 10
 }
 
@@ -77,7 +77,7 @@ void t9() {
     pop ebx
   }
 // CHECK: t9
-// CHECK: call void asm sideeffect inteldialect "push ebx\0A\09mov ebx, $$0x07\0A\09pop ebx", "~{ebx},~{dirflag},~{fpsr},~{flags}"() nounwind
+// CHECK: call void asm sideeffect inteldialect "push ebx\0A\09mov ebx, $$0x07\0A\09pop ebx", "~{ebx},~{dirflag},~{fpsr},~{flags}"() [[NUW]]
 }
 
 unsigned t10(void) {
@@ -91,7 +91,7 @@ unsigned t10(void) {
 // CHECK: [[I:%[a-zA-Z0-9]+]] = alloca i32, align 4
 // CHECK: [[J:%[a-zA-Z0-9]+]] = alloca i32, align 4
 // CHECK: store i32 1, i32* [[I]], align 4
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $1\0A\09mov dword ptr $0, eax", "=*m,*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32* %{{.*}}) nounwind
+// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $1\0A\09mov dword ptr $0, eax", "=*m,*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32* %{{.*}}) [[NUW]]
 // CHECK: [[RET:%[a-zA-Z0-9]+]] = load i32* [[J]], align 4
 // CHECK: ret i32 [[RET]]
 }
@@ -99,7 +99,7 @@ unsigned t10(void) {
 void t11(void) {
   __asm mov eax, 1
 // CHECK: t11
-// CHECK: call void asm sideeffect inteldialect "mov eax, $$1", "~{eax},~{dirflag},~{fpsr},~{flags}"() nounwind
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$1", "~{eax},~{dirflag},~{fpsr},~{flags}"() [[NUW]]
 }
 
 unsigned t12(void) {
@@ -112,7 +112,7 @@ unsigned t12(void) {
   }
   return j + m;
 // CHECK: t12
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $2\0A\09mov dword ptr $0, eax\0A\09mov eax, dword ptr $3\0A\09mov dword ptr $1, eax", "=*m,=*m,*m,*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32* %{{.*}}, i32* %{{.*}}, i32* %{{.*}}) nounwind
+// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $2\0A\09mov dword ptr $0, eax\0A\09mov eax, dword ptr $3\0A\09mov dword ptr $1, eax", "=*m,=*m,*m,*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32* %{{.*}}, i32* %{{.*}}, i32* %{{.*}}) [[NUW]]
 }
 
 void t13() {
@@ -121,8 +121,8 @@ void t13() {
   __asm movzx eax, i
   __asm movzx eax, j
 // CHECK: t13
-// CHECK: call void asm sideeffect inteldialect "movzx eax, byte ptr $0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i8* %{{.*}}) nounwind
-// CHECK: call void asm sideeffect inteldialect "movzx eax, word ptr $0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i16* %{{.*}}) nounwind
+// CHECK: call void asm sideeffect inteldialect "movzx eax, byte ptr $0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i8* %{{.*}}) [[NUW]]
+// CHECK: call void asm sideeffect inteldialect "movzx eax, word ptr $0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i16* %{{.*}}) [[NUW]]
 }
 
 void t14() {
@@ -135,7 +135,7 @@ void t14() {
     .endif
   }
 // CHECK: t14
-// CHECK: call void asm sideeffect inteldialect ".if 1\0A\09mov eax, dword ptr $0\0A\09.else\0A\09mov ebx, j\0A\09.endif", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}) nounwind
+// CHECK: call void asm sideeffect inteldialect ".if 1\0A\09mov eax, dword ptr $0\0A\09.else\0A\09mov ebx, j\0A\09.endif", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}) [[NUW]]
 }
 
 int gvar = 10;
@@ -145,16 +145,16 @@ void t15() {
   __asm mov eax, offset lvar ; eax = address of lvar
   __asm mov eax, offset gvar ; eax = address of gvar
 // CHECK: t15
-// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}) nounwind
-// CHECK: call void asm sideeffect inteldialect "mov eax, $0", "r,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}) nounwind
-// CHECK: call void asm sideeffect inteldialect "mov eax, $0", "r,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* @{{.*}}) nounwind
+// CHECK: call void asm sideeffect inteldialect "mov eax, dword ptr $0", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}) [[NUW]]
+// CHECK: call void asm sideeffect inteldialect "mov eax, $0", "r,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}) [[NUW]]
+// CHECK: call void asm sideeffect inteldialect "mov eax, $0", "r,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* @{{.*}}) [[NUW]]
 }
 
 void t16() {
   int var = 10;
   __asm mov [eax], offset var
 // CHECK: t16
-// CHECK: call void asm sideeffect inteldialect "mov [eax], $0", "r,~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}) nounwind
+// CHECK: call void asm sideeffect inteldialect "mov [eax], $0", "r,~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}) [[NUW]]
 }
 
 void t17() {
@@ -163,10 +163,10 @@ void t17() {
   __asm _emit 0x4B
   __asm _EMIT 0x4B
 // CHECK: t17
-// CHECK:  call void asm sideeffect inteldialect ".byte 0x4A", "~{dirflag},~{fpsr},~{flags}"() nounwind
-// CHECK:  call void asm sideeffect inteldialect ".byte 0x43", "~{dirflag},~{fpsr},~{flags}"() nounwind
-// CHECK:  call void asm sideeffect inteldialect ".byte 0x4B", "~{dirflag},~{fpsr},~{flags}"() nounwind
-// CHECK:  call void asm sideeffect inteldialect ".byte 0x4B", "~{dirflag},~{fpsr},~{flags}"() nounwind
+// CHECK:  call void asm sideeffect inteldialect ".byte 0x4A", "~{dirflag},~{fpsr},~{flags}"() [[NUW]]
+// CHECK:  call void asm sideeffect inteldialect ".byte 0x43", "~{dirflag},~{fpsr},~{flags}"() [[NUW]]
+// CHECK:  call void asm sideeffect inteldialect ".byte 0x4B", "~{dirflag},~{fpsr},~{flags}"() [[NUW]]
+// CHECK:  call void asm sideeffect inteldialect ".byte 0x4B", "~{dirflag},~{fpsr},~{flags}"() [[NUW]]
 }
 
 struct t18_type { int a, b; };
@@ -182,7 +182,7 @@ int t18() {
   }
   return foo.b;
 // CHECK: t18
-// CHECK: call void asm sideeffect inteldialect "lea ebx, foo\0A\09mov eax, [ebx].0\0A\09mov [ebx].4, ecx", "~{eax},~{dirflag},~{fpsr},~{flags}"() nounwind
+// CHECK: call void asm sideeffect inteldialect "lea ebx, foo\0A\09mov eax, [ebx].0\0A\09mov [ebx].4, ecx", "~{eax},~{dirflag},~{fpsr},~{flags}"() [[NUW]]
 }
 
 int t19() {
@@ -196,7 +196,7 @@ int t19() {
   }
   return foo.b;
 // CHECK: t19
-// CHECK: call void asm sideeffect inteldialect "lea ebx, foo\0A\09mov eax, [ebx].0\0A\09mov [ebx].4, ecx", "~{eax},~{dirflag},~{fpsr},~{flags}"() nounwind
+// CHECK: call void asm sideeffect inteldialect "lea ebx, foo\0A\09mov eax, [ebx].0\0A\09mov [ebx].4, ecx", "~{eax},~{dirflag},~{fpsr},~{flags}"() [[NUW]]
 }
 
 void t20() {
@@ -210,28 +210,28 @@ void t20() {
   __asm mov eax, LENGTH _foo
   __asm mov eax, LENGTH _bar
 // CHECK: t20
-// CHECK: call void asm sideeffect inteldialect "mov eax, $$1", "~{eax},~{dirflag},~{fpsr},~{flags}"() nounwind
-// CHECK: call void asm sideeffect inteldialect "mov eax, $$1", "~{eax},~{dirflag},~{fpsr},~{flags}"() nounwind
-// CHECK: call void asm sideeffect inteldialect "mov eax, $$4", "~{eax},~{dirflag},~{fpsr},~{flags}"() nounwind
-// CHECK: call void asm sideeffect inteldialect "mov eax, $$2", "~{eax},~{dirflag},~{fpsr},~{flags}"() nounwind
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$1", "~{eax},~{dirflag},~{fpsr},~{flags}"() [[NUW]]
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$1", "~{eax},~{dirflag},~{fpsr},~{flags}"() [[NUW]]
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$4", "~{eax},~{dirflag},~{fpsr},~{flags}"() [[NUW]]
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$2", "~{eax},~{dirflag},~{fpsr},~{flags}"() [[NUW]]
 
   __asm mov eax, TYPE foo
   __asm mov eax, TYPE bar
   __asm mov eax, TYPE _foo
   __asm mov eax, TYPE _bar
-// CHECK: call void asm sideeffect inteldialect "mov eax, $$4", "~{eax},~{dirflag},~{fpsr},~{flags}"() nounwind
-// CHECK: call void asm sideeffect inteldialect "mov eax, $$1", "~{eax},~{dirflag},~{fpsr},~{flags}"() nounwind
-// CHECK: call void asm sideeffect inteldialect "mov eax, $$4", "~{eax},~{dirflag},~{fpsr},~{flags}"() nounwind
-// CHECK: call void asm sideeffect inteldialect "mov eax, $$1", "~{eax},~{dirflag},~{fpsr},~{flags}"() nounwind
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$4", "~{eax},~{dirflag},~{fpsr},~{flags}"() [[NUW]]
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$1", "~{eax},~{dirflag},~{fpsr},~{flags}"() [[NUW]]
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$4", "~{eax},~{dirflag},~{fpsr},~{flags}"() [[NUW]]
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$1", "~{eax},~{dirflag},~{fpsr},~{flags}"() [[NUW]]
 
   __asm mov eax, SIZE foo
   __asm mov eax, SIZE bar
   __asm mov eax, SIZE _foo
   __asm mov eax, SIZE _bar
-// CHECK: call void asm sideeffect inteldialect "mov eax, $$4", "~{eax},~{dirflag},~{fpsr},~{flags}"() nounwind
-// CHECK: call void asm sideeffect inteldialect "mov eax, $$1", "~{eax},~{dirflag},~{fpsr},~{flags}"() nounwind
-// CHECK: call void asm sideeffect inteldialect "mov eax, $$16", "~{eax},~{dirflag},~{fpsr},~{flags}"() nounwind
-// CHECK: call void asm sideeffect inteldialect "mov eax, $$2", "~{eax},~{dirflag},~{fpsr},~{flags}"() nounwind
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$4", "~{eax},~{dirflag},~{fpsr},~{flags}"() [[NUW]]
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$1", "~{eax},~{dirflag},~{fpsr},~{flags}"() [[NUW]]
+// CHECK: call void asm sideeffect inteldialect "mov eax, $$16", "~{eax},~{dirflag},~{fpsr},~{flags}"() [[NUW]]