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Diffstat (limited to 'KSDK_1.2.0/platform/hal/inc')
59 files changed, 35524 insertions, 0 deletions
diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_adc16_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_adc16_hal.h new file mode 100755 index 0000000..43ccbca --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_adc16_hal.h @@ -0,0 +1,660 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_ADC16_HAL_H__ +#define __FSL_ADC16_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> +#include <assert.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_ADC16_COUNT + +/*! + * @addtogroup adc16_hal + * @{ + */ + +/****************************************************************************** + * Enumerations. + *****************************************************************************/ + +/*! + * @brief ADC16 status return codes. + */ +typedef enum _adc16_status +{ + kStatus_ADC16_Success = 0U, /*!< Success. */ + kStatus_ADC16_InvalidArgument = 1U, /*!< Invalid argument existed. */ + kStatus_ADC16_Failed = 2U /*!< Execution failed. */ +} adc16_status_t; + +#if FSL_FEATURE_ADC16_HAS_MUX_SELECT + +/*! + * @brief Defines the type of the enumerating channel multiplexer mode for each channel. + * + * For some ADC16 channels, there are two selections for the channel multiplexer. For + * example, ADC0_SE4a and ADC0_SE4b are the different channels but share the same + * channel index. + */ +typedef enum _adc16_chn_mux_mode +{ + kAdc16ChnMuxOfA = 0U, /*!< For channel with channel mux a. @internal gui name="MUX A" */ + kAdc16ChnMuxOfB = 1U, /*!< For channel with channel mux b. @internal gui name="MUX B" */ + kAdc16ChnMuxOfDefault = kAdc16ChnMuxOfA /*!< For channel without any channel mux identifier. @internal gui name="" */ +} adc16_chn_mux_mode_t; +#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ + +/*! + * @brief Defines the type of the enumerating divider for the converter. + */ +typedef enum _adc16_clk_divider +{ + kAdc16ClkDividerOf1 = 0U, /*!< For divider 1 from the input clock to ADC16. @internal gui name="1" */ + kAdc16ClkDividerOf2 = 1U, /*!< For divider 2 from the input clock to ADC16. @internal gui name="2" */ + kAdc16ClkDividerOf4 = 2U, /*!< For divider 4 from the input clock to ADC16. @internal gui name="4" */ + kAdc16ClkDividerOf8 = 3U /*!< For divider 8 from the input clock to ADC16. @internal gui name="8" */ +} adc16_clk_divider_t; + +/*! + *@brief Defines the type of the enumerating resolution for the converter. + */ +typedef enum _adc16_resolution +{ + kAdc16ResolutionBitOf8or9 = 0U, + /*!< 8-bit for single end sample, or 9-bit for differential sample. @internal gui name="" */ + kAdc16ResolutionBitOfSingleEndAs8 = kAdc16ResolutionBitOf8or9, /*!< 8-bit for single end sample. @internal gui name="8 bit in single mode" */ + kAdc16ResolutionBitOfDiffModeAs9 = kAdc16ResolutionBitOf8or9, /*!< 9-bit for differential sample. @internal gui name="9 bit in differential mode" */ + + kAdc16ResolutionBitOf12or13 = 1U, + /*!< 12-bit for single end sample, or 13-bit for differential sample. @internal gui name="" */ + kAdc16ResolutionBitOfSingleEndAs12 = kAdc16ResolutionBitOf12or13, /*!< 12-bit for single end sample. @internal gui name="12 bit in single mode" */ + kAdc16ResolutionBitOfDiffModeAs13 = kAdc16ResolutionBitOf12or13, /*!< 13-bit for differential sample. @internal gui name="13 bit in differential mode" */ + + kAdc16ResolutionBitOf10or11 = 2U, + /*!< 10-bit for single end sample, or 11-bit for differential sample. @internal gui name="" */ + kAdc16ResolutionBitOfSingleEndAs10 = kAdc16ResolutionBitOf10or11, /*!< 10-bit for single end sample. @internal gui name="10 bit in single mode" */ + kAdc16ResolutionBitOfDiffModeAs11 = kAdc16ResolutionBitOf10or11 /*!< 11-bit for differential sample. @internal gui name="11 bit in differential mode" */ +#if (FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U) + , kAdc16ResolutionBitOf16 = 3U, + /*!< 16-bit for both single end sample and differential sample. @internal gui name="16-bit" */ + kAdc16ResolutionBitOfSingleEndAs16 = kAdc16ResolutionBitOf16, /*!< 16-bit for single end sample. @internal gui name="" */ + kAdc16ResolutionBitOfDiffModeAs16 = kAdc16ResolutionBitOf16 /*!< 16-bit for differential sample. @internal gui name="" */ + +#endif /* FSL_FEATURE_ADC16_MAX_RESOLUTION */ +} adc16_resolution_t; + +/*! + * @brief Defines the type of the enumerating source of the input clock. + */ +typedef enum _adc16_clk_src_mode +{ + kAdc16ClkSrcOfBusClk = 0U, /*!< For input as bus clock. @internal gui name="Bus clock" */ + kAdc16ClkSrcOfAltClk2 = 1U, /*!< For input as alternate clock 2 (AltClk2). @internal gui name="Alternate clock 2" */ + kAdc16ClkSrcOfAltClk = 2U, /*!< For input as alternate clock (ALTCLK). @internal gui name="Alternate clock 1" */ + kAdc16ClkSrcOfAsynClk = 3U /*!< For input as asynchronous clock (ADACK). @internal gui name="Asynchronous clock" */ +} adc16_clk_src_mode_t; + +/*! + * @brief Defines the type of the enumerating long sample cycles. + */ +typedef enum _adc16_long_sample_cycle +{ + kAdc16LongSampleCycleOf24 = 0U, /*!< 20 extra ADCK cycles, 24 ADCK cycles total. */ + kAdc16LongSampleCycleOf16 = 1U, /*!< 12 extra ADCK cycles, 16 ADCK cycles total. */ + kAdc16LongSampleCycleOf10 = 2U, /*!< 6 extra ADCK cycles, 10 ADCK cycles total. */ + kAdc16LongSampleCycleOf4 = 3U /*!< 2 extra ADCK cycles, 6 ADCK cycles total. */ +} adc16_long_sample_cycle_t; + +/*! + * @brief Defines the type of the enumerating reference voltage source. + */ +typedef enum _adc16_ref_volt_src +{ + kAdc16RefVoltSrcOfVref = 0U, /*!< For external pins pair of VrefH and VrefL. @internal gui name="Vref pair" */ + kAdc16RefVoltSrcOfValt = 1U /*!< For alternate reference pair of ValtH and ValtL. @internal gui name="Valt pair" */ +} adc16_ref_volt_src_t; + +#if FSL_FEATURE_ADC16_HAS_HW_AVERAGE + +/*! + * @brief Defines the type of the enumerating hardware average mode. + */ +typedef enum _adc16_hw_average_count +{ + kAdc16HwAverageCountOf4 = 0U, /*!< For hardware average with 4 samples. */ + kAdc16HwAverageCountOf8 = 1U, /*!< For hardware average with 8 samples. */ + kAdc16HwAverageCountOf16 = 2U, /*!< For hardware average with 16 samples. */ + kAdc16HwAverageCountOf32 = 3U /*!< For hardware average with 32 samples. */ +} adc16_hw_average_count_t; + +#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ + +#if FSL_FEATURE_ADC16_HAS_PGA + +/*! + * @brief Defines the type of enumerating PGA's Gain mode. + */ +typedef enum _adc16_pga_gain +{ + kAdc16PgaGainValueOf1 = 0U, /*!< For amplifier gain of 1. @internal gui name="1" */ + kAdc16PgaGainValueOf2 = 1U, /*!< For amplifier gain of 2. @internal gui name="2" */ + kAdc16PgaGainValueOf4 = 2U, /*!< For amplifier gain of 4. @internal gui name="4" */ + kAdc16PgaGainValueOf8 = 3U, /*!< For amplifier gain of 8. @internal gui name="8" */ + kAdc16PgaGainValueOf16 = 4U, /*!< For amplifier gain of 16. @internal gui name="16" */ + kAdc16PgaGainValueOf32 = 5U, /*!< For amplifier gain of 32. @internal gui name="32" */ + kAdc16PgaGainValueOf64 = 6U /*!< For amplifier gain of 64. @internal gui name="64" */ +} adc16_pga_gain_t; + +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +/*! + * @brief Defines the type of enumerating ADC16's channel index. + */ +typedef enum _adc16_chn +{ + kAdc16Chn0 = 0U, /*!< AD0. */ + kAdc16Chn1 = 1U, /*!< AD1. */ + kAdc16Chn2 = 2U, /*!< AD2. */ + kAdc16Chn3 = 3U, /*!< AD3. */ + kAdc16Chn4 = 4U, /*!< AD4. */ + kAdc16Chn5 = 5U, /*!< AD5. */ + kAdc16Chn6 = 6U, /*!< AD6. */ + kAdc16Chn7 = 7U, /*!< AD6. */ + kAdc16Chn8 = 8U, /*!< AD8. */ + kAdc16Chn9 = 9U, /*!< AD9. */ + kAdc16Chn10 = 10U, /*!< AD10. */ + kAdc16Chn11 = 11U, /*!< AD11. */ + kAdc16Chn12 = 12U, /*!< AD12. */ + kAdc16Chn13 = 13U, /*!< AD13. */ + kAdc16Chn14 = 14U, /*!< AD14. */ + kAdc16Chn15 = 15U, /*!< AD15. */ + kAdc16Chn16 = 16U, /*!< AD16. */ + kAdc16Chn17 = 17U, /*!< AD17. */ + kAdc16Chn18 = 18U, /*!< AD18. */ + kAdc16Chn19 = 19U, /*!< AD19. */ + kAdc16Chn20 = 20U, /*!< AD20. */ + kAdc16Chn21 = 21U, /*!< AD21. */ + kAdc16Chn22 = 22U, /*!< AD22. */ + kAdc16Chn23 = 23U, /*!< AD23. */ + kAdc16Chn24 = 24U, /*!< AD24. */ + kAdc16Chn25 = 25U, /*!< AD25. */ + kAdc16Chn26 = 26U, /*!< AD26. */ + kAdc16Chn27 = 27U, /*!< AD27. */ + kAdc16Chn28 = 28U, /*!< AD28. */ + kAdc16Chn29 = 29U, /*!< AD29. */ + kAdc16Chn30 = 30U, /*!< AD30. */ + kAdc16Chn31 = 31U, /*!< AD31. */ + + kAdc16Chn0d = kAdc16Chn0, /*!< DAD0. */ + kAdc16Chn1d = kAdc16Chn1, /*!< DAD1. */ + kAdc16Chn2d = kAdc16Chn2, /*!< DAD2. */ + kAdc16Chn3d = kAdc16Chn3, /*!< DAD3. */ + kAdc16Chn4a = kAdc16Chn4, /*!< AD4a. */ + kAdc16Chn5a = kAdc16Chn5, /*!< AD5a. */ + kAdc16Chn6a = kAdc16Chn6, /*!< AD6a. */ + kAdc16Chn7a = kAdc16Chn7, /*!< AD7a. */ + kAdc16Chn4b = kAdc16Chn4, /*!< AD4b. */ + kAdc16Chn5b = kAdc16Chn5, /*!< AD5b. */ + kAdc16Chn6b = kAdc16Chn6, /*!< AD6b. */ + kAdc16Chn7b = kAdc16Chn7 /*!< AD7b. */ + +} adc16_chn_t; + +/****************************************************************************** + * Definitions. + *****************************************************************************/ +/*! + * @brief Defines the structure to configure the ADC16 channel. + * + * This type of variable is treated as the command to be set in ADC + * control register, which may execute the ADC's conversion. + */ +typedef struct Adc16ChnConfig +{ + adc16_chn_t chnIdx; /*!< Select the sample channel index. */ + bool convCompletedIntEnable; /*!< Enable the conversion complete interrupt. */ +#if FSL_FEATURE_ADC16_HAS_DIFF_MODE + bool diffConvEnable; /*!< Enable the differential conversion. */ +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ +} adc16_chn_config_t; + +/*! + * @brief Defines the structure to configure the ADC16's converter. + * + * This type of variable is treated as a group of configurations. + * Most of the time, these configurations are a one-time + * setting for converter sampling condition. Usually, they are set before + * executing the ADC16 job. + * @internal gui name="ADC configuration" id="adcCfg" + */ +typedef struct Adc16ConverterConfig +{ + bool lowPowerEnable; /*!< Enable low power. @internal gui name="Low power mode" id="LowPowerMode" */ + adc16_clk_divider_t clkDividerMode; /*!< Select the divider of input clock source. @internal gui name="Clock divider" id="ClockDivider" */ + bool longSampleTimeEnable; /*!< Enable the long sample time. @internal gui name="Long sample time" id="LongSampleTime" */ + adc16_resolution_t resolution; /*!< Select the sample resolution mode. @internal gui name="Resolution" id="Resolution" */ + adc16_clk_src_mode_t clkSrc; /*!< Select the input clock source to converter. @internal gui name="Clock source" id="ClockSource" */ + bool asyncClkEnable; /*!< Enable the asynchronous clock inside the ADC. @internal gui name="Internal async. clock" id="InternalAsyncClock" */ + bool highSpeedEnable; /*!< Enable the high speed mode. @internal gui name="High speed mode" id="HighSpeed" */ + adc16_long_sample_cycle_t longSampleCycleMode; /*!< Select the long sample mode. @internal gui name="Long sample mode" id="LongSampleMode" */ + bool hwTriggerEnable; /*!< Enable hardware trigger function. @internal gui name="Hardware trigger" id="HwTrigger" */ + adc16_ref_volt_src_t refVoltSrc; /*!< Select the reference voltage source. @internal gui name="Voltage reference" id="ReferenceVoltage" */ + bool continuousConvEnable; /*!< Enable continuous conversion mode. @internal gui name="Continuous mode" id="ContinuousMode" */ +#if FSL_FEATURE_ADC16_HAS_DMA + bool dmaEnable; /*!< Enable the DMA for ADC converter. @internal gui name="DMA mode" id="DMASupport" */ +#endif /* FSL_FEATURE_ADC16_HAS_DMA */ +} adc16_converter_config_t; + +/*! + * @brief Defines the structure to configure the ADC16 internal comparator. + * @internal gui name="HW compare configuration" id="adcHwCfg" + */ +typedef struct Adc16HwCmpConfig +{ + bool hwCmpEnable; /*!< Enable the hardware compare function. @internal gui name="Hardware compare" */ + bool hwCmpGreaterThanEnable; /*!< Configure the compare function. @internal gui name="Compare function greater than" */ + /* + false - Configures less than the threshold. The outside and inside range are not inclusive. + The functionality is based on the values + placed in CV1 and CV2. + true - Configures greater than or equal to the threshold. The outside and inside + ranges are inclusive. The functionality is based on the values placed in + CV1 and CV2. + */ + bool hwCmpRangeEnable; /*!< Configure the comparator function. @internal gui name="Compare function range" */ + /* + Configures the comparator function to check if the conversion result of the + input being monitored is either between or outside the range formed by + CV1 and CV2 and determined by the value of hwCmpGreaterThanEnable. + + false - Range function disabled. Only CV1 is compared. + true - Range function enabled. Both CV1 and CV2 are compared. + */ + uint16_t cmpValue1; /*!< Setting value for CV1. @internal gui name="Compare value 1" */ + uint16_t cmpValue2; /*!< Setting value for CV2. @internal gui name="Compare value 2" */ +} adc16_hw_cmp_config_t; + +#if FSL_FEATURE_ADC16_HAS_HW_AVERAGE +/*! + * @brief Defines the structure to configure the ADC16 internal accumulator. + */ +typedef struct Adc16HwAverageConfig +{ + bool hwAverageEnable; /*!< Enable the hardware average function. */ + adc16_hw_average_count_t hwAverageCountMode; /*!< Select the count of conversion result for accumulator. */ +} adc16_hw_average_config_t; + +#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ + + +#if FSL_FEATURE_ADC16_HAS_PGA +/*! + * @brief Defines the structure to configure the ADC16 programmable gain amplifier. + * @internal gui name="ADC PGA configuration" id="adcPgaCfg" + */ +typedef struct Adc16PgaConfig +{ + bool pgaEnable; /*!< Enable the PGA's function. @internal gui name="PGA module" */ + bool runInNormalModeEnable; /*!< Enable PGA working in normal mode, or low power mode defaultly. @internal gui name="Low power mode run" */ + adc16_pga_gain_t pgaGainMode; /*!< Select the PGA Gain factor. @internal gui name="Gain" */ + +#if FSL_FEATURE_ADC16_HAS_PGA_CHOPPING + bool pgaChoppingDisable; /*!< Disable the PGA chopping function. @internal gui name="Chopping control" */ + /* + The PGA employs chopping to remove/reduce offset and 1/f noise and offers an + offset measurement configuration that aids the offset calibration. + */ +#endif /* FSL_FEATURE_ADC16_HAS_PGA_CHOPPING */ +#if FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT + bool runInOffsetMeasurementEnable; /*!< Enable the PGA working in offset measurement mode. @internal gui name="Offset measurement mode" */ + /* + When this feature is enabled, the PGA disconnects itself from the external + inputs and auto-configures into offset measurement mode. With this bit set, + run the ADC in the recommended settings and enable the maximum hardware + averaging to get the PGA offset number. The output is the + (PGA offset * (64+1)) for the given PGA setting. + */ +#endif /* FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT */ +} adc16_pga_config_t; + +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @name ADC16 HAL. + * @{ + */ + + +/*! + * @brief Resets all registers into a known state for the ADC16 module. + * + * This function resets all registers into a known state for the ADC + * module. This known state is the reset value indicated by the Reference + * manual. It is strongly recommended to call this API before any other operation + * when initializing the ADC16 module. + * + * @param base Register base address for the module. + */ +void ADC16_HAL_Init(ADC_Type * base); + +/*! + * @brief Configures the conversion channel for the ADC16 module. + * + * This function configures the channel for the ADC16 module. At any point, + * only one of the configuration groups takes effect. The other channel group of + * the first group (group A, 0) is only for the hardware trigger. Both software and + * hardware trigger can be used to the first group. When in software trigger + * mode, after the available channel is set, the conversion begins to execute. + * + * @param base Register base address for the module. + * @param chnGroup Channel configuration group ID. + * @param configPtr Pointer to configuration structure. + */ +void ADC16_HAL_ConfigChn(ADC_Type * base, uint32_t chnGroup, const adc16_chn_config_t *configPtr); + +/*! + * @brief Checks whether the channel conversion is completed. + * + * This function checks whether the channel conversion for the ADC + * module is completed. + * + * @param base Register base address for the module. + * @param chnGroup Channel configuration group ID. + * @return Assertion of completed conversion mode. + */ +static inline bool ADC16_HAL_GetChnConvCompletedFlag(ADC_Type * base, uint32_t chnGroup) +{ + assert(chnGroup < FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT); + return (1U == ADC_BRD_SC1_COCO(base, chnGroup) ); +} + +/*! + * @brief Configures the sampling converter for the ADC16. + * + * This function configures the sampling converter for the ADC16. + * Most of the time, the configurations are a one-time setting for the + * converter sampling condition. Usually, it is called before + * executing the ADC16 job. + * + * @param base Register base address for the module. + * @param configPtr Pointer to configuration structure. + */ +void ADC16_HAL_ConfigConverter(ADC_Type *base, const adc16_converter_config_t *configPtr); + +/*! + * @brief Configures the hardware comparator function for the ADC16. + * + * This function configures the hardware comparator function for the ADC16. + * These are the settings for the ADC16 comparator. + * + * @param base Register base address for the module. + * @param configPtr Pointer to configuration structure. + */ +void ADC16_HAL_ConfigHwCompare(ADC_Type * base, const adc16_hw_cmp_config_t *configPtr); + +#if FSL_FEATURE_ADC16_HAS_HW_AVERAGE +/*! + * @brief Configures the hardware average function for the ADC16. + * + * This function configures the hardware average function for the ADC16. + * These are the settings for the accumulator inside the ADC16. + * + * @param base Register base address for the module. + * @param configPtr Pointer to configuration structure. + */ +void ADC16_HAL_ConfigHwAverage(ADC_Type * base, const adc16_hw_average_config_t *configPtr); +#endif /* FSL_FEATURE_ADC16_HAS_HW_AVERAGE */ + +/*! + * @brief Gets the raw result data of channel conversion for the ADC16 module. + * + * This function gets the conversion result data for the ADC16 module. + * The return value is the raw data that is not processed. + * + * @param base Register base address for the module. + * @param chnGroup Channel configuration group ID. + * @return Conversion value of RAW. + */ +static inline uint16_t ADC16_HAL_GetChnConvValue(ADC_Type * base, uint32_t chnGroup ) +{ + assert(chnGroup < FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT); + return (uint16_t)(ADC_BRD_R_D(base, chnGroup) ); +} + +/*! + * @brief Checks whether the converter is active for the ADC16 module. + * + * This function checks whether the converter is active for the ADC16 + * module. + * + * @param base Register base address for the module. + * @return Assertion of that the converter is active. + */ +static inline bool ADC16_HAL_GetConvActiveFlag(ADC_Type * base) +{ + return (1U == ADC_BRD_SC2_ADACT(base) ); +} + +#if FSL_FEATURE_ADC16_HAS_MUX_SELECT +/*! + * @brief Selects the channel mux mode for the ADC16 module. + * + * This function selects the channel mux mode for the ADC16 module. + * + * @param base Register base address for the module. + * @param mode Selection of mode enumeration. See to "adc16_chn_mux_mode_t". + */ +static inline void ADC16_HAL_SetChnMuxMode(ADC_Type * base, adc16_chn_mux_mode_t mode) +{ + ADC_BWR_CFG2_MUXSEL(base, ((kAdc16ChnMuxOfA == mode) ? 0U : 1U) ); +} +#endif /* FSL_FEATURE_ADC16_HAS_MUX_SELECT */ + +#if FSL_FEATURE_ADC16_HAS_CALIBRATION +/*! + * @brief Switches to enable the hardware calibration for the ADC16 module. + * + * This function launches the hardware calibration for the ADC16 module. + * + * @param base Register base address for the module. + * @param enable Switcher to asserted the feature. + */ +static inline void ADC16_HAL_SetAutoCalibrationCmd(ADC_Type * base, bool enable) +{ + ADC_BWR_SC3_CAL(base, (enable ? 1U : 0U) ); +} + +/*! + * @brief Gets the hardware calibration status for the ADC16 module. + * + * This function gets the status whether the hardware calibration is active + * for the ADC16 module. The return value holds on as asserted during the hardware + * calibration. Then, it is cleared and dis-asserted after the + * calibration. + * + * @param base Register base address for the module. + * @return Whether the hardware calibration is active or not. + */ +static inline bool ADC16_HAL_GetAutoCalibrationActiveFlag(ADC_Type * base) +{ + return (1U == ADC_BRD_SC3_CAL(base) ); +} + +/*! + * @brief Gets the hardware calibration status for the ADC16 module. + * + * This function gets the status whether the hardware calibration has failed + * for the ADC16 module. The return value is asserted if there is anything wrong + * with the hardware calibration. + * + * @param base Register base address for the module. + * @return Whether the hardware calibration has failed or not. + */ +static inline bool ADC16_HAL_GetAutoCalibrationFailedFlag(ADC_Type * base) +{ + return (1U == ADC_BRD_SC3_CALF(base) ); +} + +/*! + * @brief Gets and calculates the plus side calibration parameter from the auto calibration. + * + * This function gets the values of CLP0 - CLP4 and CLPS internally, + * accumulates them, and returns the value that can be used to be set in the PG + * register directly. Note that this API should be called after the process of + * auto calibration is complete. + * + * @param base Register base address for the module. + * @return value that can be set into PG directly. + */ +uint16_t ADC16_HAL_GetAutoPlusSideGainValue(ADC_Type * base); + +/*! + * @brief Sets the plus side gain calibration value for the ADC16 module. + * + * This function sets the plus side gain calibration value for the ADC16 module. + * + * @param base Register base address for the module. + * @param value Setting value for plus side gain. + */ +static inline void ADC16_HAL_SetPlusSideGainValue(ADC_Type * base, uint16_t value) +{ + ADC_BWR_PG_PG(base, value); +} + +#if FSL_FEATURE_ADC16_HAS_DIFF_MODE + +/*! + * @brief Gets and calculates the minus side calibration parameter from the auto calibration. + * + * This function gets the values of CLM0 - CLM4 and CLMS internally, + * accumulates them, and returns the value that can be used to be set in the MG + * register directly. Note that this API should be called after the process of + * auto calibration is complete. + * + * @param base Register base address for the module. + * @return value that can be set into MG directly. + */ +uint16_t ADC16_HAL_GetAutoMinusSideGainValue(ADC_Type * base); + +/*! + * @brief Sets the minus side gain calibration value for the ADC16 module. + * + * This function sets the minus side gain calibration value for the ADC16 module. + * + * @param base Register base address for the module. + * @param value Setting value for minus side gain. + */ +static inline void ADC16_HAL_SetMinusSideGainValue(ADC_Type * base, uint16_t value) +{ + ADC_BWR_MG_MG(base, value); +} + +#endif /* FSL_FEATURE_ADC16_HAS_DIFF_MODE */ + +#endif /* FSL_FEATURE_ADC16_HAS_CALIBRATION */ + +#if FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION + +/*! + * @brief Gets the offset correction value for the ADC16 module. + * + * This function gets the offset correction value for the ADC16 module. + * When auto calibration is executed, the OFS register holds the new value + * generated by the calibration. It can be left as default or modified + * according to the use case. + * + * @param base Register base address for the module. + * @return current value for OFS. + */ +static inline uint16_t ADC16_HAL_GetOffsetValue(ADC_Type * base) +{ + return (uint16_t)(ADC_BRD_OFS_OFS(base) ); +} + +/*! + * @brief Sets the offset correction value for the ADC16 module. + * + * This function sets the offset correction value for the ADC16 module. The ADC + * offset correction register (OFS) contains the user-selected or calibration-generated + * offset error correction value. The value in the offset correction + * registers (OFS) is subtracted from the conversion and the result is + * transferred into the result registers (Rn). If the result is above the + * maximum or below the minimum result value, it is forced to the appropriate + * limit for the current mode of operation. + * + * @param base Register base address for the module. + * @param value Setting value for OFS. + */ +static inline void ADC16_HAL_SetOffsetValue(ADC_Type * base, uint16_t value) +{ + ADC_BWR_OFS_OFS(base, value); +} + +#endif /* FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION */ + +#if FSL_FEATURE_ADC16_HAS_PGA + +/*! + * @brief Configures the PGA function for ADC16. + * + * This function configures the PGA function for ADC16. + * The settings are mainly for the Programmable Gain Amplifier inside + * the ADC16. + * + * @param base Register base address for the module. + * @param configPtr Pointer to configuration structure. + */ +void ADC16_HAL_ConfigPga(ADC_Type * base, const adc16_pga_config_t *configPtr); + +/*@}*/ + +#endif /* FSL_FEATURE_ADC16_HAS_PGA */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ +#endif +#endif /* __FSL_ADC16_HAL_H__ */ + +/****************************************************************************** + * EOF + *****************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_aoi_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_aoi_hal.h new file mode 100755 index 0000000..749ca4e --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_aoi_hal.h @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#if !defined(__FSL_AOI_HAL_H__) +#define __FSL_AOI_HAL_H__ + +#include <assert.h> +#include <stdbool.h> +#include "fsl_device_registers.h" + +#if FSL_FEATURE_SOC_AOI_COUNT + +/*! + * @addtogroup aoi_hal + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief AOI status return codes. + */ +typedef enum _aoi_status +{ + kStatus_AOI_Success = 0U, /*!< Success. */ + kStatus_AOI_InvalidArgument = 1U, /*!< Invalid argument existed. */ + kStatus_AOI_Failed = 2U /*!< Execution failed. */ +} aoi_status_t; + +/* + * @brief AOI input configurations. + * + * The selection item represents the Boolean evaluations. +*/ +typedef enum _aoi_input_config +{ + kAoiConfigLogicZero = 0x0U, /*!< Forces the input to logical zero. */ + kAoiConfigInputSignal = 0x1U, /*!< Passes the input signal. */ + kAoiConfigInvInputSignal = 0x2U, /*!< Inverts the input signal. */ + kAoiConfigLogicOne = 0x3U /*!< Forces the input to logical one. */ +} aoi_input_config_t; + +/*! + * @brief Defines the product term numbers. + */ +typedef enum _aoi_product_term +{ + kAoiTerm0 = 0x0U, /*!< Product term 0 */ + kAoiTerm1 = 0x1U, /*!< Product term 1 */ + kAoiTerm2 = 0x2U, /*!< Product term 2 */ + kAoiTerm3 = 0x3U /*!< Product term 3 */ +} aoi_product_term_t; + +/*! + * @brief AOI input signal indexes. + */ +typedef enum _aoi_input_signal_index +{ + kAoiInputA = 0x0U, /*!< Input configuration A */ + kAoiInputB = 0x1U, /*!< Input configuration B */ + kAoiInputC = 0x2U, /*!< Input configuration C */ + kAoiInputD = 0x3U /*!< Input configuration D */ +} aoi_input_signal_index_t; + +/*! + * @brief AOI event indexes, where an event is the collection of the four product + * terms (0, 1, 2, and 3) and the four signal inputs (A, B, C, and D). + */ +typedef enum _aoi_event_index +{ + kAoiEvent0 = 0x0U, /*!< Event 0 index */ + kAoiEvent1 = 0x1U, /*!< Event 1 index */ + kAoiEvent2 = 0x2U, /*!< Event 2 index */ + kAoiEvent3 = 0x3U /*!< Event 3 index */ +} aoi_event_index_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initializes the AOI module to the reset state. + * + * This function initializes the module to the reset state. This state is defined in the chip Reference + * Manual, which is the power on reset value. + * + * @param base Register base address for AOI module. + */ +void AOI_HAL_Init(AOI_Type* base); + +/*! +* @brief Resets the configuration registers of a specific AOI event. + * + * This function resets all product term inputs of a selected event to the reset values. + * This state is defined in the chip Reference Manual, which is the power on reset value. + * + * @param base Register base address for AOI module. + * @param event Event of AOI to be reset of type aoi_event_index_t. +*/ +void AOI_HAL_Reset(AOI_Type* base, aoi_event_index_t event); + +/*! + * @brief Defines the Boolean evaluation associated with the selected input in the selected product + * term of the desired event. + * + * This function defines the Boolean evaluation associated with the selected input in the selected + * product term of the desired event. + * + * @param base Register base address for AOI module. + * @param event Number of the event which will be set of type aoi_event_index_t. + * @param productTerm The term which will be set of type aoi_product_term_t. + * @param input The input which will be set of type aoi_input_signal_index_t. + * @param config Selected input configuration of type aoi_input_config_t. + */ +void AOI_HAL_SetSignalLogicUnit(AOI_Type* base, + aoi_event_index_t event, + aoi_product_term_t productTerm, + aoi_input_signal_index_t input, + aoi_input_config_t config); + +/*! + * @brief Gets the Boolean evaluation associated with the selected input in the selected product + * term of the desired event. + * + * This function returns the Boolean evaluation associated with the selected input in the selected + * product term of the desired event. + * + * @param base Register base address for AOI module. + * @param event Number of the event which will be set of type aoi_event_index_t. + * @param productTerm The product term which will be set of type aoi_product_term_t. + * @param input The input which will be set of type aoi_input_signal_index_t. + * @return Selected input configuration of type aoi_input_config_t. + */ +aoi_input_config_t AOI_HAL_GetSignalLogicUnit(AOI_Type* base, + aoi_event_index_t event, + aoi_product_term_t productTerm, + aoi_input_signal_index_t input); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* FSL_FEATURE_SOC_AOI_COUNT */ +#endif /* __FSL_AOI_HAL_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_cadc_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_cadc_hal.h new file mode 100755 index 0000000..5c07c04 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_cadc_hal.h @@ -0,0 +1,710 @@ +/* + * Copyright (c) 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_CADC_HAL_H__ +#define __FSL_CADC_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> +#include <assert.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_CADC_COUNT + +/*! + * @addtogroup cadc_hal + * @{ + */ + +/****************************************************************************** + * Enumerations. + *****************************************************************************/ + +/*! + * @brief CADC status return codes. + */ +typedef enum _cadc_status +{ + kStatus_CADC_Success = 0U, /*!< Success. */ + kStatus_CADC_InvalidArgument = 1U, /*!< Invalid argument existed. */ + kStatus_CADC_Failed = 2U /*!< Execution failed. */ +} cadc_status_t; + +/*! + * @brief Defines the type of enumerating ADC differential channel pair. + * + * Note, "cadc_diff_chn_t" and "cadc_chn_sel_mode_t" can determine to + * select the single ADC sample channel. + */ +typedef enum _cadc_diff_chn +{ + kCAdcDiffChnANA0_1 = 0U, /*!< ConvA's Chn 0 & 1. @internal gui name="ANA 0 & 1" */ + kCAdcDiffChnANA2_3 = 1U, /*!< ConvA's Chn 2 & 3. @internal gui name="ANA 2 & 3" */ + kCAdcDiffChnANA4_5 = 2U, /*!< ConvA's Chn 4 & 5. @internal gui name="ANA 4 & 5" */ + kCAdcDiffChnANA6_7 = 3U, /*!< ConvA's Chn 6 & 7. @internal gui name="ANA 6 & 7" */ + kCAdcDiffChnANB0_1 = 4U, /*!< ConvB's Chn 0 & 1. @internal gui name="ANB 0 & 1" */ + kCAdcDiffChnANB2_3 = 5U, /*!< ConvB's Chn 2 & 3. @internal gui name="ANB 2 & 3" */ + kCAdcDiffChnANB4_5 = 6U, /*!< ConvB's Chn 4 & 5. @internal gui name="ANB 4 & 5" */ + kCAdcDiffChnANB6_7 = 7U /*!< ConvB's Chn 6 & 7. @internal gui name="ANB 6 & 7" */ +} cadc_diff_chn_t; + +/*! + * @brief Defines the type of enumerating ADC channel in differential pair. + * + * Note, "cadc_diff_chn_t" and "cadc_chn_sel_mode_t" can determine + * selecting the single ADC sample channel. + */ +typedef enum _cadc_chn_sel_mode +{ + kCAdcChnSelN = 0U, /*!< Select negative side channel. @internal gui name="Negative channel side" */ + kCAdcChnSelP = 1U, /*!< Select positive side channel. @internal gui name="Positive channel side" */ + kCAdcChnSelBoth = 2U /*!< Select both of them in differential mode.. @internal gui name="Both - differential mode" */ +} cadc_chn_sel_mode_t; + +/*! + * @brief Defines the type of enumerating ADC converter's scan mode. + * + * See the ADC_CTRL1[SMODE] in the chip Reference Manual for detailed information + * about the ADC converter scan mode. + */ +typedef enum _cadc_scan_mode +{ + kCAdcScanOnceSequential = 0U, /*!< Once (single) sequential. @internal gui name="Once sequential" */ + kCAdcScanOnceParallel = 1U, /*!< Once parallel. @internal gui name="Once parallel" */ + kCAdcScanLoopSequential = 2U, /*!< Loop sequential. @internal gui name="Loop sequential" */ + kCAdcScanLoopParallel = 3U, /*!< Loop parallel. @internal gui name="Loop parallel" */ + kCAdcScanTriggeredSequential = 4U, /*!< Triggered sequential. @internal gui name="Triggered sequential" */ + kCAdcScanTriggeredParalled = 5U /*!< Triggered parallel (default). @internal gui name="Triggered parallel" */ +} cadc_scan_mode_t; + +/*! + * @brief Defines the type to enumerate the zero crossing detection mode for each slot. + */ +typedef enum _cadc_zero_crossing_mode +{ + kCAdcZeroCrossingDisable = 0U, /*!< Zero crossing detection disabled. @internal gui name="Disabled" */ + kCAdcZeroCrossingAtRisingEdge = 1U, /*!< Enable for positive to negative sign change. @internal gui name="Rising edge" */ + kCAdcZeroCrossingAtFallingEdge = 2U, /*!< Enable for negative to positive sign change. @internal gui name="Falling edge" */ + kCAdcZeroCrossingAtBothEdge = 3U /*!< Enable for any sign change. @internal gui name="Both edges" */ +} cadc_zero_crossing_mode_t; + +/*! + * @brief Defines the type to enumerate the amplification mode for each slot. + */ +typedef enum _cadc_gain_mode +{ + kCAdcSGainBy1 = 0U, /*!< x1 amplification. @internal gui name="1" */ + kCAdcSGainBy2 = 1U, /*!< x2 amplification. @internal gui name="2" */ + kCAdcSGainBy4 = 2U /*!< x4 amplification. @internal gui name="4" */ +} cadc_gain_mode_t; + +/*! + * @brief Defines the type to enumerate the speed mode for each converter. + * + * These items represent the clock speed at which the ADC converter can operate. + * Faster conversion speeds require greater current consumption. + */ +typedef enum _cadc_conv_speed_mode +{ + kCAdcConvClkLimitBy6_25MHz = 0U, /*!< Conversion clock frequency <= 6.25 MHz; + current consumption per converter = 6 mA. @internal gui name="Max 6.25 MHz" */ + kCAdcConvClkLimitBy12_5MHz = 1U, /*!< Conversion clock frequency <= 12.5 MHz; + current consumption per converter = 10.8 mA. @internal gui name="Max 12.5 MHz" */ + kCAdcConvClkLimitBy18_75MHz = 2U, /*!< Conversion clock frequency <= 18.75 MHz; + current consumption per converter = 18 mA. @internal gui name="Max 18.75 MHz" */ + kCAdcConvClkLimitBy25MHz = 3U /*!< Conversion clock frequency <= 25 MHz; + current consumption per converter = 25.2 mA. @internal gui name="Max 25 MHz" */ +} cadc_conv_speed_mode_t; + +/*! + * @brief Defines the type of DMA trigger source for each converter. + * + * During sequential and simultaneous parallel scan modes, it selects between + * end of scan for ConvA's scan and RDY status as the DMA source. During + * non-simultaneous parallel scan mode it selects between end of scan for + * converters A and B, and the RDY status as the DMA source + */ +typedef enum _cadc_dma_trigger_src +{ + kCAdcDmaTriggeredByEndOfScan = 0U, /*!< DMA trigger source is end of scan interrupt. @internal gui name="End of scan" */ + kCAdcDmaTriggeredByConvReady = 1U /*!< DMA trigger source is RDY status. @internal gui name="Conversion ready status" */ +} cadc_dma_trigger_src_t; + +/****************************************************************************** + * Definitions. + *****************************************************************************/ + +/*! + * @brief Defines a structure to configure the CyclicADC module during initialization. + * + * This structure holds the configuration when initializing the CyclicADC module. + * @internal gui name="CADC configuration" id="cadcInitCfg" + */ +typedef struct CAdcControllerConfig +{ + /* Functional control. */ + bool zeroCrossingIntEnable; /*!< Global zero crossing interrupt enable. @internal gui name="Zero crossing interrupt" */ + bool lowLimitIntEnable; /*!< Global low limit interrupt enable. @internal gui name="Low limit interrupt"*/ + bool highLimitIntEnable; /*!< Global high limit interrupt enable. @internal gui name="High limit interrupt" */ + cadc_scan_mode_t scanMode; /*!< ADC scan mode control. @internal gui name="Scan mode" */ + bool parallelSimultModeEnable; /*!< Parallel scans done simultaneously enable. @internal gui name="Simultaneous parallel scans" */ + cadc_dma_trigger_src_t dmaSrc; /*!< DMA trigger source. @internal gui name="DMA trigger source" */ + + /* Power control. */ + bool autoStandbyEnable; /*!< Auto standby mode enable. @internal gui name="Auto standby mode" */ + uint16_t powerUpDelayCount; /*!< Power up delay. @internal gui name="Power up delay" */ + bool autoPowerDownEnable; /*!< Auto power down mode enable. @internal gui name="Auto power down mode" */ +} cadc_controller_config_t; + +/*! + * @brief Defines a structure to configure each converter in the CyclicADC module. + * + * This structure holds the configuration for each converter in the CyclicADC module. + * Normally, there are two converters, ConvA and ConvB in the cyclic ADC + * module. However, each converter can be configured separately for some features. + * @internal gui name="CADC Converter configuration" id="cadcConvCfg" + */ +typedef struct CAdcConverterConfig +{ + bool dmaEnable; /*!< DMA enable. @internal gui name="DMA" */ + + /* + * When this bit is asserted, the current scan is stopped and no further + * scans can start. Any further SYNC input pulses or software trigger are + * ignored until this bit has been cleared. After the ADC is in stop mode, + * the results registers can be modified by the processor. Any changes to + * the result registers in stop mode are treated as if the analog core + * supplied the data. Therefore, limit checking, zero crossing, and + * associated interrupts can occur when authorized. + */ + bool stopEnable; /*!< Stop mode enable. @internal gui name="Stop mode" */ + + bool syncEnable; /*!< Enable external sync input to trigger conversion. @internal gui name="External synchronization" */ + bool endOfScanIntEnable; /*!< End of scan interrupt enable. @internal gui name="End of scan interrupt" */ + + /* + * For Clock Divisor Select: + * The divider circuit generates the ADC clock by dividing the system clock: + * - When the value is set to 0, the divisor is 2. + * - For all other setting values, the divisor is 1 more than the decimal + * value of the setting value. + * A divider value must be chosen to prevent the ADC clock from exceeding the + * maximum frequency. + */ + uint16_t clkDivValue; /*!< ADC clock divider from the bus clock. @internal gui name="Clock divider" */ + + bool useChnInputAsVrefH; /*!< Use input channel as high reference voltage, such as AN2. @internal gui name="Input channel as high voltage reference" */ + bool useChnInputAsVrefL; /*!< Use input channel as low reference voltage, such as AN3. @internal gui name="Input channel as low voltage reference" */ + cadc_conv_speed_mode_t speedMode; /*!< ADC speed control mode. @internal gui name="Speed mode" */ + + /* + * For ConvA: + * During sequential and parallel simultaneous scan modes, the + * "sampleWindowCount" controls the sampling time of the first sample after + * a scan is initiated on both converters A and B. + * In parallel non-simultaneous mode, this field affects ConvA only. + * In sequential scan mode, this field setting is ignored whenever + * the channel selected for the next sample is on the other converter. In + * other words, during a sequential scan, if a sample converts a ConvA + * channel (ANA0-ANA7) and the next sample converts a ConvB channel + * (ANB0-ANB7) or vice versa, this field is ignored and uses the + * default sampling time (value 0) for the next sample. + * + * For ConvB: + * During parallel non-simultaneous scan mode, the "sampleWindowCount" for + * ConvB is used to control the sampling time of the first sample after + * a scan is initiated. During sequential and parallel simultaneous scan + * modes, "sampleWindowCount" is ignored and the sampling window for both + * converters is controlled by the "sampleWindowCount" for ConvA. + * + * To set the value: + * The value 0 corresponds to a sampling time of 2 ADC clocks. Each increment + * of "sampleWindowCount" corresponds to an additional ADC clock cycle of + * sampling time with a maximum sampling time of 9 ADC clocks. + */ + uint16_t sampleWindowCount; /*!< Sample window count. @internal gui name="Sample window count" */ +} cadc_converter_config_t; + +/*! + * @brief Defines a structure to configure each input channel. + * + * This structure holds the configuration for each input channel. In CcylicADC + * module, the input channels are handled by a differential sample. + * However, the user can still configure the function for each channel when + * set to operate as a single end sample. + * @internal gui name="Channel configuration" id="cadcChnCfg" + */ +typedef struct CAdcChnConfig +{ + cadc_diff_chn_t diffChns; /*!< Select the differential channel pair. @internal gui name="Channel" */ + cadc_chn_sel_mode_t diffSelMode; /*!< Select which channel is indicated in a pair. @internal gui name="Differential mode" */ + cadc_gain_mode_t gainMode; /*!< Gain mode for each channel. @internal gui name="Gain" */ +} cadc_chn_config_t; + +/*! + * @brief Defines a structure to configure each slot. + * + * This structure holds the configuration for each slot in a conversion sequence. + * @internal gui name="Slot configuration" id="cadcSlotCfg" + */ +typedef struct CAdcSlotConfig +{ + bool slotDisable; /*!< Keep the slot unavailable. @internal gui name="Slot" */ + bool syncPointEnable; /*!< Sample waits for an enabled SYNC input to occur. @internal gui name="Synchronization point" */ + bool syncIntEnable; /*!< Scan interrupt enable. @internal gui name="Scan interrupt" */ + + /* Select the input channel for slot. */ + cadc_diff_chn_t diffChns; /*!< Select the differential pair. @internal gui name="Channel pair" id="diffSlotChns" */ + cadc_chn_sel_mode_t diffSel; /*!< Positive or negative channel in differential pair. @internal gui name="Channel select" */ + + /* Event detection mode. */ + cadc_zero_crossing_mode_t zeroCrossingMode; /*!< Select zero crossing detection mode. @internal gui name="Zero cross mode" */ + uint16_t lowLimitValue; /*!< Select low limit for hardware compare. @internal gui name="Low limit compare value" */ + uint16_t highLimitValue;/*!< Select high limit for hardware compare. @internal gui name="High limit compare value" */ + uint16_t offsetValue; /*!< Select sign change limit for hardware compare. @internal gui name="Offset value" */ +} cadc_slot_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Initializes all ADC registers to a known state. + * + * The initial states of ADC registers are set as specified in the chip Reference Manual. + * + * @param base Register base address for the module. + */ +void CADC_HAL_Init(ADC_Type * base); + +/*! + * @brief Configures the common features in cyclic ADC module. + * + * This function configures the common features in cyclic ADC module. For + * detailed items, see the "cadc_controller_config_t". + * + * @param base Register base address for the module. + * @param configPtr Pointer to configuration structure. + */ +void CADC_HAL_ConfigController(ADC_Type * base, const cadc_controller_config_t *configPtr); + +/*! + * @brief Configures the features for the converter A. + * + * This function configures the features for the converter A. For detailed items, + * see the "cadc_converter_config_t". + * + * @param base Register base address for the module. + * @param configPtr Pointer to configuration structure. + */ +void CADC_HAL_ConfigConvA(ADC_Type * base, const cadc_converter_config_t *configPtr); + +/*! + * @brief Configures the features for the conversion B. + * + * This function configures the features for the conversion B. For detailed items, + * see the "cadc_converter_config_t". + * + * @param base Register base address for the module. + * @param configPtr Pointer to configuration structure. + */ +void CADC_HAL_ConfigConvB(ADC_Type * base, const cadc_converter_config_t *configPtr); + +/*! + * @brief Configures the feature for the sample channel. + * + * This function configures the features for the sample channel. For detailed + * items, see the "cadc_chn_config_t". + * + * @param base Register base address for the module. + * @param configPtr Pointer to configuration structure. + */ +void CADC_HAL_ConfigChn(ADC_Type * base, const cadc_chn_config_t *configPtr); + +/*! + * @brief Configures the features for the sample sequence slot. + * + * This function configures the features for the sample sequence slot. For detailed + * items, see the "cadc_slot_config_t". + * + * @param base Register base address for the module. + * @param slotIdx Sample slot index. + * @param configPtr Pointer to configuration structure. + */ +void CADC_HAL_ConfigSeqSlot(ADC_Type * base, uint32_t slotIdx, const cadc_slot_config_t *configPtr); + +/* Command. */ +/*! + * @brief Executes the command that starts conversion of the converter A. + * + * This function executes the command that start the conversion of the converter A + * when using the software trigger. + * + * @param base Register base address for the module. + */ +static inline void CADC_HAL_SetConvAStartCmd(ADC_Type * base) +{ + ADC_BWR_CTRL1_START0(base, 1U); +/* + uint16_t ctrl1 = ADC_RD_CTRL1(base); + ctrl1 |= ADC_CTRL1_START0_MASK; + ADC_WR_CTRL1(base, ctrl1); +*/ +} + +/*! + * @brief Executes the command that start conversion of the converter B. + * + * This function executes the command that start the conversion of the converter B + * when using the software trigger. + * + * @param base Register base address for the module. + */ +static inline void CADC_HAL_SetConvBStartCmd(ADC_Type * base) +{ + ADC_BWR_CTRL2_START1(base, 1U); +/* + uint16_t ctrl2 = ADC_RD_CTRL2(base); + ctrl2 |= ADC_CTRL2_START1_MASK; + ADC_WR_CTRL2(base, ctrl2); +*/ +} + +/* Power switcher for converters. */ +/*! + * @brief Shuts down the conversion power manually for the converter A. + * + * This function shuts down the conversion power manually for the conversion A. + * The conversion stops immediately after calling this function. + * + * @param base Register base address for the module. + * @param enable Switcher to enable the feature or not. + */ +static inline void CADC_HAL_SetConvAPowerDownCmd(ADC_Type * base, bool enable) +{ + ADC_BWR_PWR_PD0(base, (uint16_t)enable); +} + +/*! + * @brief Shuts down the conversion power manually for the converter B. + * + * This function shots downs the conversion power manually for the conversion B. + * The conversion stops immediately after calling this function. + * + * @param base Register base address for the module. + * @param enable Swither to enable the feature or not. + */ +static inline void CADC_HAL_SetConvBPowerDownCmd(ADC_Type * base, bool enable) +{ + ADC_BWR_PWR_PD1(base, (uint16_t)enable); +} + +/* Flags. */ +/* Conversion in progress. */ +/*! + * @brief Gets the flag whether the converter A is in process. + * + * This function gets the flag whether the converter A is in process. + * + * @param base Register base address for the module. + * @return The event is asserted or not. + */ +static inline bool CADC_HAL_GetConvAInProgressFlag(ADC_Type * base) +{ + return ADC_BRD_STAT_CIP0(base); +} + +/*! + * @brief Gets the flag whether the converter B is in process. + * + * This function gets the flag whether the converter B is in process. + * + * @param base Register base address for the module. + * @return The event is asserted or not. + */ +static inline bool CADC_HAL_GetConvBInProgressFlag(ADC_Type * base) +{ + return ADC_BRD_STAT_CIP1(base); +} + +/* End of scan interrupt flag. */ +/*! + * @brief Gets the flag whether the converter A has finished the conversion. + * + * This function gets the flag whether the converter A has finished the conversion. + * + * @param base Register base address for the module. + * @return The event is asserted or not. + */ +static inline bool CADC_HAL_GetConvAEndOfScanIntFlag(ADC_Type * base) +{ + return ADC_BRD_STAT_EOSI0(base); +} + +/*! + * @brief Gets the flag whether the converter B has finished the conversion. + * + * This function gets the flag whether the converter B has finished the conversion. + * + * @param base Register base address for the module. + * @return The event is asserted or not. + */ +static inline bool CADC_HAL_GetConvBEndOfScanIntFlag(ADC_Type * base) +{ + return ADC_BRD_STAT_EOSI1(base); +} + +/*! + * @brief Clears the flag that finishes the conversion of the converter A. + * + * This function clears the flag that finishes the conversion of the converter A. + * + * @param base Register base address for the module. + */ +static inline void CADC_HAL_ClearConvAEndOfScanIntFlag(ADC_Type * base) +{ + ADC_BWR_STAT_EOSI0(base, 1U); +} + +/*! + * @brief Clears the flag that finishes the conversion of the converter B. + * + * This function clears the flag that finishes the conversion of the converter B. + * + * @param base Register base address for the module. + */ +static inline void CADC_HAL_ClearConvBEndOfScanIntFlag(ADC_Type * base) +{ + ADC_BWR_STAT_EOSI1(base, 1U); +} + +/* Zero-crossing interrupt flag. */ +/*! + * @brief Gets the flag whether a sample zero-crossing event has happened. + * + * This function gets the flag whether any sample zero-crossing event has + * happened. + * + * @param base Register base address for the module. + * @return The event is asserted or not. + */ +static inline bool CADC_HAL_GetZeroCrossingIntFlag(ADC_Type * base) +{ + return ADC_BRD_STAT_ZCI(base); +} + +/*! + * @brief Gets the flag whether a sample zero-crossing event has happened. + * + * This function gets the flags whether a sample zero-crossing event has + * happened. + * + * @param base Register base address for the module. + * @param slotIdxMask Mask for indicated slots. + * @return flags whether the event are happened for indicated slots. + */ +static inline uint16_t CADC_HAL_GetSlotZeroCrossingFlag(ADC_Type * base, uint16_t slotIdxMask) +{ + return ( slotIdxMask & ADC_RD_ZXSTAT(base) ); +} + +/*! + * @brief Clears the flags of a sample zero-crossing events. + * + * This function clears the flags of the sample zero-crossing events. + * + * @param base Register base address for the module. + * @param slotIdxMask Mask for indicated slots. + */ +static inline void CADC_HAL_ClearSlotZeroCrossingFlag(ADC_Type * base, uint16_t slotIdxMask) +{ + ADC_WR_ZXSTAT(base, slotIdxMask); +} + +/* Low limit interrupt flag. */ +/*! + * @brief Gets the flag whether any sample value is lower than the low limit value. + * + * This function gets the flag whether any sample value is lower than the low + * limit value. + * + * @param base Register base address for the module. + * @return The event is asserted or not. + */ +static inline bool CADC_HAL_GetLowLimitIntFlag(ADC_Type * base) +{ + return ADC_BRD_STAT_LLMTI(base); +} + +/*! + * @brief Gets the flags whether a sample value is lower than the low limit value. + * + * This function gets the flags whether a samples value is lower than the low + * limit value. + * + * @param base Register base address for the module. + * @param slotIdxMask Mask for indicated slots. + * @return flags whether the event are happened for indicated slots. + */ +static inline uint16_t CADC_HAL_GetSlotLowLimitFlag(ADC_Type * base, uint16_t slotIdxMask) +{ + return (slotIdxMask & ADC_RD_LOLIMSTAT(base)); +} + +/*! + * @brief Clears the flags of the sample low limit event. + * + * This function clears the flags of the sample low limit event. + * + * @param base Register base address for the module. + * @param slotIdxMask Mask for indicated slots. + */ +static inline void CADC_HAL_ClearSlotLowLimitFlag(ADC_Type * base, uint16_t slotIdxMask) +{ + ADC_WR_LOLIMSTAT(base, slotIdxMask); +} + +/* High limit interrupt flag. */ +/*! + * @brief Gets the flag whether any sample value is higher than the high limit value. + * + * This function gets the flag whether any sample value is higher than the high + * limit value. + * + * @param base Register base address for the module. + * @return The event is asserted or not. + */ +static inline bool CADC_HAL_GetHighLimitIntFlag(ADC_Type * base) +{ + return ADC_BRD_STAT_HLMTI(base); +} + +/*! + * @brief Gets the flags whether a sample value is higher than the high limit value. + * + * This function gets the flags whether a sample value is higher than the + * high limit value. + * + * @param base Register base address for the module. + * @param slotIdxMask Mask for indicated slots. + * @return flags whether the event are happened for indicated slots. + */ +static inline uint16_t CADC_HAL_GetSlotHighLimitFlag(ADC_Type * base, uint16_t slotIdxMask) +{ + return (slotIdxMask & ADC_RD_HILIMSTAT(base) ); +} + +/*! + * @brief Clears the flags of the sample high limit event. + * + * This function clears the flags of the sample high limit event. + * + * @param base Register base address for the module. + * @param slotIdxMask Mask for indicated slots. + */ +static inline void CADC_HAL_ClearSlotHighLimitFlag(ADC_Type * base, uint16_t slotIdxMask) +{ + ADC_WR_HILIMSTAT(base, slotIdxMask ); +} + +/*! + * @brief Gets the flags whether a sample value is ready. + * + * This function gets the flags whether a sample value is ready. + * + * @param base Register base address for the module. + * @param slotIdxMask Mask for indicated slots. + * @return flags whether the event are happened for indicated slots. + */ +static inline uint16_t CADC_HAL_GetSlotReadyFlag(ADC_Type * base, uint16_t slotIdxMask) +{ + return (slotIdxMask & ADC_RD_RDY(base) ); +} + +/* ADC Converter's power status. */ +/*! + * @brief Gets the flag whether the converter A is powered down. + * + * This function gets the flag whether the converter A is powered down. + * + * @param base Register base address for the module. + * @return The event is asserted or not. + */ +static inline bool CADC_HAL_GetConvAPowerDownFlag(ADC_Type * base) +{ + return ADC_BRD_PWR_PSTS0(base); +} + +/*! + * @brief Gets the flag whether the converter B is powered down. + * + * This function gets the flag whether the converter B is powered down. + * + * @param base Register base address for the module. + * @return The event is asserted or not. + */ +static inline bool CADC_HAL_GetConvBPowerDownFlag(ADC_Type * base) +{ + return ADC_BRD_PWR_PSTS1(base); +} + +/* Value. */ +/*! + * @brief Gets the sample value. + * + * This function gets the sample value. Note that the 3 LSBs are not available. + * When the differential conversion is executed, the MSB is the sign bit. + * + * @param base Register base address for the module. + * @param slotIdx Index of slot in conversion sequence. + * @return sample value with sign bit in MSB. + */ +static inline uint16_t CADC_HAL_GetSampleValue(ADC_Type * base, uint16_t slotIdx) +{ + return ADC_RD_RSLT(base, slotIdx); +} + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif +#endif /* __FSL_CADC_HAL_H__ */ +/****************************************************************************** + * EOF + *****************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_cmp_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_cmp_hal.h new file mode 100755 index 0000000..1c9fa4d --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_cmp_hal.h @@ -0,0 +1,379 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_CMP_HAL_H__ +#define __FSL_CMP_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> +#include <assert.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_CMP_COUNT + +/*! + * @addtogroup cmp_hal + * @{ + */ + +/****************************************************************************** + * Enumerations + *****************************************************************************/ + +/*! + * @brief CMP status return codes. + */ +typedef enum _cmp_status +{ + kStatus_CMP_Success = 0U, /*!< Success */ + kStatus_CMP_InvalidArgument = 1U, /*!< Invalid argument existed */ + kStatus_CMP_Failed = 2U /*!< Execution failed */ +} cmp_status_t; + +/*! + * @brief Defines the selections of the hard block hysteresis control level. + * + * The hysteresis control level indicates the smallest window between the two + * inputs when asserting the change of output. See the chip + * Data Sheet for detailed electrical characteristics. Generally, the lower level + * represents the smaller window. + */ +typedef enum _cmp_hystersis_mode +{ + kCmpHystersisOfLevel0 = 0U, /*!< Level 0 */ + kCmpHystersisOfLevel1 = 1U, /*!< Level 1 */ + kCmpHystersisOfLevel2 = 2U, /*!< Level 2 */ + kCmpHystersisOfLevel3 = 3U /*!< Level 3 */ +} cmp_hystersis_mode_t; + +/*! + * @brief Defines the selections of the filter sample counter. + * + * The selection item represents the number of consecutive samples that must + * agree prior to the comparator output filter accepting a new output state. + */ +typedef enum _cmp_filter_counter_mode_t +{ + kCmpFilterCountSampleOf0 = 0U, /*!< Disable the filter */ + kCmpFilterCountSampleOf1 = 1U, /*!< One sample must agree */ + kCmpFilterCountSampleOf2 = 2U, /*!< 2 consecutive samples must agree */ + kCmpFilterCountSampleOf3 = 3U, /*!< 3 consecutive samples must agree */ + kCmpFilterCountSampleOf4 = 4U, /*!< 4 consecutive samples must agree */ + kCmpFilterCountSampleOf5 = 5U, /*!< 5 consecutive samples must agree */ + kCmpFilterCountSampleOf6 = 6U, /*!< 6 consecutive samples must agree */ + kCmpFilterCountSampleOf7 = 7U /*!< 7 consecutive samples must agree */ +} cmp_filter_counter_mode_t; + +/*! + * @brief Defines the selections of reference voltage source for the internal DAC. + */ +typedef enum _cmp_dac_ref_volt_src_mode_t +{ + kCmpDacRefVoltSrcOf1 = 0U, /*!< Vin1 - Vref_out */ + kCmpDacRefVoltSrcOf2 = 1U /*!< Vin2 - Vdd */ +} cmp_dac_ref_volt_src_mode_t; + +/*! + * @brief Define the selection of the CMP channel mux. + */ +typedef enum _cmp_chn_mux_mode_t +{ + kCmpInputChn0 = 0U, /*!< Comparator input channel 0. @internal gui name="Input 0" */ + kCmpInputChn1 = 1U, /*!< Comparator input channel 1. @internal gui name="Input 1" */ + kCmpInputChn2 = 2U, /*!< Comparator input channel 2. @internal gui name="Input 2" */ + kCmpInputChn3 = 3U, /*!< Comparator input channel 3. @internal gui name="Input 3" */ + kCmpInputChn4 = 4U, /*!< Comparator input channel 4. @internal gui name="Input 4" */ + kCmpInputChn5 = 5U, /*!< Comparator input channel 5. @internal gui name="Input 5" */ + kCmpInputChn6 = 6U, /*!< Comparator input channel 6. @internal gui name="Input 6" */ + kCmpInputChn7 = 7U, /*!< Comparator input channel 7. @internal gui name="Input 7" */ + kCmpInputChnDac = kCmpInputChn7 /*!< Comparator input channel 7. @internal gui name="DAC output" */ +} cmp_chn_mux_mode_t; + +/****************************************************************************** + * Definitions + *****************************************************************************/ +/*! + * @brief Defines a structure for configuring the comparator in the CMP module. + * + * This structure holds the configuration for the comparator + * inside the CMP module. With the configuration, the CMP can be set as a + * basic comparator without additional features. + * @internal gui name="Basic configuration" id="cmpCfg" + */ +typedef struct CmpComparatorConfig +{ + cmp_hystersis_mode_t hystersisMode; /*!< Set the hysteresis level. @internal gui name="Hysteresis level" id="HysteresisLevel" */ + bool pinoutEnable; /*!< Enable outputting the CMPO to pin. @internal gui name="Out pin" id="OutPin" */ + bool pinoutUnfilteredEnable; /*!< Enable outputting unfiltered result to CMPO. @internal gui name="Unfiltered output pin" id="UnfilteredOutPinEnable" */ + bool invertEnable; /*!< Enable inverting the comparator's result. @internal gui name="Output inversion" id="InvertLogic" */ + bool highSpeedEnable; /*!< Enable working in speed mode. @internal gui name="High speed" id="HighSpeed" */ +#if FSL_FEATURE_CMP_HAS_DMA + bool dmaEnable; /*!< Enable using DMA. @internal gui name="DMA" id="DMA" */ +#endif /* FSL_FEATURE_CMP_HAS_DMA */ + bool risingIntEnable; /*!< Enable using CMPO rising interrupt. @internal gui name="Rising interrupt" id="RisingInt" */ + bool fallingIntEnable; /*!< Enable using CMPO falling interrupt. @internal gui name="Falling interrupt" id="FallingInt" */ + cmp_chn_mux_mode_t plusChnMux; /*!< Set the Plus side input to comparator. @internal gui name="Positive channel" id="PositiveChannel" */ + cmp_chn_mux_mode_t minusChnMux; /*!< Set the Minus side input to comparator. @internal gui name="Negative channel" id="NegativeChannel" */ +#if FSL_FEATURE_CMP_HAS_TRIGGER_MODE + bool triggerEnable; /*!< Enable triggering mode. @internal gui name="Trigger mode" id="TriggerMode" */ +#endif /* FSL_FEATURE_CMP_HAS_TRIGGER_MODE */ + +} cmp_comparator_config_t; + +/*! +* @brief Definition selections of the sample and filter modes in the CMP module. +* +* Comparator sample/filter is available in several modes. Use the enumeration +* to identify the comparator's status: +* +* kCmpContinuousMode - Continuous Mode: + Both window control and filter blocks are completely bypassed. The + comparator output is updated continuously. +* kCmpSampleWithNoFilteredMode - Sample, Non-Filtered Mode: + Window control is completely bypassed. The comparator output is + sampled whenever a rising-edge is detected on the filter block clock + input. The filter clock prescaler can be configured as a + divider from the bus clock. +* kCmpSampleWithFilteredMode - Sample, Filtered Mode: + Similar to "Sample, Non-Filtered Mode", but the filter is active in + this mode. The filter counter value also becomes + configurable. +* kCmpWindowedMode - Windowed Mode: + In Windowed Mode, only output of analog comparator is passed when + the WINDOW signal is high. The last latched value is held when the WINDOW + signal is low. +* kCmpWindowedFilteredMode - Window/Filtered Mode: + This is a complex mode because it uses both window and filtering + features. It also has the highest latency of all modes. This can be + approximated to up to 1 bus clock synchronization in the window function + + ( ( filter counter * filter prescaler ) + 1) bus clock for the + filter function. +*/ +typedef enum _cmp_sample_filter_mode +{ + kCmpContinuousMode = 0U, /*!< Continuous Mode */ + kCmpSampleWithNoFilteredMode = 1U, /*!< Sample, Non-Filtered Mode */ + kCmpSampleWithFilteredMode = 2U, /*!< Sample, Filtered Mode */ + kCmpWindowedMode = 3U, /*!< Window Mode */ + kCmpWindowedFilteredMode = 4U /*!< Window/Filtered Mode */ +} cmp_sample_filter_mode_t; + +/*! +* @brief Defines a structure to configure the window/filter in CMP module. +* +* This structure holds the configuration for the window/filter inside +* the CMP module. With the configuration, the CMP module can operate in +* advanced mode. +* @internal gui name="Filter configuration" id="filterCfg" +*/ +typedef struct CmpSampleFilterConfig +{ + cmp_sample_filter_mode_t workMode; /*!< Sample/Filter's work mode. @internal gui name="Work mode" id="WorkMode" */ + bool useExtSampleOrWindow; /*!< Switcher to use external WINDOW/SAMPLE signal. @internal gui name="External sample/window signal" id="ExtSampleWinSignal" */ + uint8_t filterClkDiv; /*!< Filter's prescaler which divides from the bus clock. @internal gui name="Filter divider" id="FiltClkDiv" */ + cmp_filter_counter_mode_t filterCount; /*!< Sample count for filter. See "cmp_filter_counter_mode_t". @internal gui name="Filter sample count" id="FiltCnt" */ +} cmp_sample_filter_config_t; + +/*! + * @brief Defines a structure to configure the internal DAC in the CMP module. + * + * This structure holds the configuration for the DAC + * inside the CMP module. With the configuration, the internal DAC + * provides a reference voltage level and is chosen as the CMP input. + * @internal gui name="DAC configuration" id="dacCfg" + */ +typedef struct CmpDacConfig +{ + bool dacEnable; /*!< Enable the internal 6-bit DAC. @internal gui name="D/A converter" id="DacEnable" */ + cmp_dac_ref_volt_src_mode_t refVoltSrcMode; /*!< Select the reference voltage source for internal DAC. @internal gui name="Input reference" id="Reference" */ + uint8_t dacValue; /*!< Set the value for internal DAC. @internal gui name="Output level value" id="DacValue" */ +} cmp_dac_config_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Resets the CMP registers to a known state. + * + * This function resets the CMP registers to a known state. This state is + * defined in the chip Reference Manual, which is power on reset value. + * + * @param base Register base address for the module. + */ +void CMP_HAL_Init(CMP_Type * base); + +/*! + * @brief Configures the CMP comparator function. + * + * This function configures the CMP comparator function. + * + * @param base Register base address for the module. + * @param configPtr Pointer to configuration structure. See to "cmp_comparator_config_t". + */ +void CMP_HAL_ConfigComparator(CMP_Type * base, const cmp_comparator_config_t *configPtr); + +/*! + * @brief Configures the CMP DAC function. + * + * This function configures the CMP DAC function. + * + * @param base Register base address for the module. + * @param configPtr Pointer to configuration structure. See to "cmp_dac_config_t". + */ +void CMP_HAL_ConfigDacChn(CMP_Type * base, const cmp_dac_config_t *configPtr); + +/*! + * @brief Configures the CMP sample or the filter function. + * + * This function configures the CMP sample or filter function. + * + * @param base Register base address for the module. + * @param configPtr Pointer to configuration structure. See to "cmp_sample_filter_config_t". + */ +void CMP_HAL_ConfigSampleFilter(CMP_Type * base, const cmp_sample_filter_config_t *configPtr); + +/*! + * @brief Enables the comparator in the CMP module. + * + * This function enables the comparator in the CMP module. The analog + * comparator is the core component in the CMP module. Only when it is enabled, all + * other functions for advanced features are meaningful. + * + * @param base Register base address for the module. + */ +static inline void CMP_HAL_Enable(CMP_Type * base) +{ + CMP_BWR_CR1_EN(base, 1U); +} + +/*! + * @brief Disables the comparator in the CMP module. + * + * This function disables the comparator in the CMP module. The analog + * comparator is the core component in the CMP module. When it is disabled, it + * remains in the off state and consumes no power. + * + * @param base Register base address for the module. + */ +static inline void CMP_HAL_Disable(CMP_Type * base) +{ + CMP_BWR_CR1_EN(base, 0U); +} + +/*! + * @brief Gets the comparator logic output in the CMP module. + * + * This function gets the comparator logic output in the CMP module. + * It returns the current value of the analog comparator output. The value + * is reset to 0 and read as de-asserted value when the CMP module is + * disabled. When setting to invert mode, the comparator logic output is + * inverted as well. + * + * @param base Register base address for the module. + * @return The logic output is assert or not. + */ +static inline bool CMP_HAL_GetOutputLogic(CMP_Type * base) +{ + return ( 1U == CMP_BRD_SCR_COUT(base) ); +} + +/*! + * @brief Gets the logic output falling edge event in the CMP module. + * + * This function gets the logic output falling edge event in the CMP module. + * It detects a falling-edge on COUT and returns the asserted state when the + * falling-edge on COUT has occurred. + * + * @param base Register base address for the module. + * @return The falling-edge on COUT has occurred or not. + */ +static inline bool CMP_HAL_GetOutputFallingFlag(CMP_Type * base) +{ + return ( 1U == CMP_BRD_SCR_CFF(base) ); +} + +/*! + * @brief Clears the logic output falling edge event in the CMP module. + * + * This function clears the logic output falling edge event in the CMP module. + * + * @param base Register base address for the module. + */ +static inline void CMP_HAL_ClearOutputFallingFlag(CMP_Type * base) +{ + CMP_BWR_SCR_CFF(base, 1U); +} + +/*! + * @brief Gets the logic output rising edge event in the CMP module. + * + * This function gets the logic output rising edge event in the CMP module. + * It detects a rising-edge on COUT and returns the asserted state when the + * rising-edge on COUT has occurred. + * + * @param base Register base address for the module. + * @return The rising-edge on COUT has occurred or not. + */ +static inline bool CMP_HAL_GetOutputRisingFlag(CMP_Type * base) +{ + return ( 1U == CMP_BRD_SCR_CFR(base) ); +} + +/*! + * @brief Clears the logic output rising edge event in the CMP module. + * + * This function clears the logic output rising edge event in the CMP module. + * + * @param base Register base address for the module. + */ +static inline void CMP_HAL_ClearOutputRisingFlag(CMP_Type * base) +{ + CMP_BWR_SCR_CFR(base, 1U); +} + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif +#endif /* __FSL_CMP_HAL_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_cop_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_cop_hal.h new file mode 100755 index 0000000..236afa7 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_cop_hal.h @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_COP_HAL_H__ +#define __FSL_COP_HAL_H__ + +#include <string.h> +#include <stdint.h> +#include <stdbool.h> +#include <assert.h> +#include "fsl_device_registers.h" + +/*! + * @addtogroup cop_hal + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @brief COP clock source selection.*/ +typedef enum _cop_clock_source { + kCopLpoClock, /*!< LPO clock,1K HZ. @internal gui name="LPO" */ +#if FSL_FEATURE_COP_HAS_MORE_CLKSRC + kCopMcgIrClock, /*!< MCG IRC Clock. @internal gui name="MCGIRCLK"*/ + kCopOscErClock, /*!< OSCER Clock. @internal gui name="OSCERCLK"*/ +#endif + kCopBusClock /*!< BUS clock. @internal gui name="Bus clock"*/ +}cop_clock_source_t; + +/*! @brief Define the value of the COP timeout cycles */ +typedef enum _cop_timeout_cycles { + kCopTimeout_short_2to5_or_long_2to13 = 1U, /*!< 2 to 5 clock cycles when clock source is LPO or in short timeout mode otherwise 2 to 13 clock cycles @internal gui name="2^5 or 2^13 clock" */ + kCopTimeout_short_2to8_or_long_2to16 = 2U, /*!< 2 to 8 clock cycles when clock source is LPO or in short timeout mode otherwise 2 to 16 clock cycles @internal gui name="2^8 or 2^16 clock" */ + kCopTimeout_short_2to10_or_long_2to18 = 3U /*!< 2 to 10 clock cycles when clock source is LPO or in short timeout mode otherwise 2 to 18 clock cycles @internal gui name="2^10 or 2^18 clock" */ +}cop_timeout_cycles_t; + +#if FSL_FEATURE_COP_HAS_LONGTIME_MODE +/*! @breif Define the COP's timeout mode */ +typedef enum _cop_timeout_mode{ + kCopShortTimeoutMode = 0U, /*!< COP selects long timeout @internal gui name="Short timeout" */ + kCopLongTimeoutMode = 1U /*!< COP selects short timeout @internal gui name="Long timeout" */ +}cop_timeout_mode_t; +#endif + +/*! + * @brief Data structure to initialize the COP. + * + * This structure is used to initialize the COP during the cop_init function call. + * It contains all COP configurations. + * @internal gui name="COP configuration" id="copCfg" + */ +typedef struct CopConfig{ + bool copWindowModeEnable; /*!< Set COP watchdog run mode---Window mode or Normal mode @internal gui name="Windowed mode" id="WindowedMode" */ +#if FSL_FEATURE_COP_HAS_LONGTIME_MODE + cop_timeout_mode_t copTimeoutMode; /*!< Set COP watchdog timeout mode---Long timeout or Short timeout @internal gui name="Timeout mode" id="TimeoutMode" */ + bool copStopModeEnable; /*!< Set COP enable or disable in STOP mode @internal gui name="Stop mode" id="StopMode" */ + bool copDebugModeEnable; /*!< Set COP enable or disable in DEBUG mode @internal gui name="Debug mode" id="DebugMode" >*/ +#endif + cop_clock_source_t copClockSource; /*!< Set COP watchdog clock source @internal gui name="Clock source" id="ClockSource" */ + cop_timeout_cycles_t copTimeout; /*!< Set COP watchdog timeout value @internal gui name="Timeout value" id="TimeoutValue" */ +}cop_config_t; + +/*! @brief cop status return codes.*/ +typedef enum _cop_status { + kStatus_COP_Success = 0x0U, /*!< COP operation Succeed */ + kStatus_COP_Fail = 0x01, /*!< COP operation Failed */ + kStatus_COP_NotInitlialized = 0x2U, /*!< COP is not initialized yet */ + kStatus_COP_NullArgument = 0x3U, /*!< Argument is NULL */ +}cop_status_t; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name COP HAL. + * @{ + */ + + +/*! + * @brief Configures the COP Watchdog. + * + * The COP control register is write once after reset. + * + * @param base The COP peripheral base address + * @param configPtr configure COP control register + */ +void COP_HAL_SetConfig(SIM_Type * base, const cop_config_t *configPtr); + +/*! + * @brief Enables the COP Watchdog. + * + * After reset the COP is enabled. + * + */ +static inline void COP_HAL_Enable(void) +{ + +} + +/*! + * @brief Disables the COP Watchdog. + * + * This function disables the COP Watchdog and + * should be called after reset if your application does not need the COP Watchdog. + * + * @param base The COP peripheral base address + */ +static inline void COP_HAL_Disable(SIM_Type * base) +{ + SIM_BWR_COPC_COPT(base, 0U); +} + +/*! + * @brief Determines whether the COP is enabled. + * + * This function checks whether the COP is running. + * + * @param base The COP peripheral base address + * @return State of the module + * @retval true COP is enabled + * @retval false COP is disabled + */ +static inline bool COP_HAL_IsEnable(SIM_Type * base) +{ + return ((bool)SIM_BRD_COPC_COPT(base)); +} + +/*! + * @brief Servicing the COP Watchdog. + * + * This function resets the COP timeout by writing 0x55 then 0xAA. + * Writing any other value generates a system reset. + * The writing operations should be atomic. + * @param base The COP peripheral base address + */ +static inline void COP_HAL_Refresh(SIM_Type * base) +{ + SIM_WR_SRVCOP(base, 0x55U); + SIM_WR_SRVCOP(base, 0xaaU); +} + +/*! + * @brief Resets the system. + * + * This function resets the system. + * @param base The COP peripheral base address + */ +static inline void COP_HAL_ResetSystem(SIM_Type * base) +{ + SIM_WR_SRVCOP(base, 0U); +} + +/*! + * @brief Restores the COP module to the reset value. + * + * This function restores the COP module to the reset value. + * + * @param base The COP peripheral base address + */ +void COP_HAL_Init(SIM_Type * base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __FSL_COP_HAL_H__*/ +/******************************************************************************* + * EOF + *******************************************************************************/ diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_crc_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_crc_hal.h new file mode 100755 index 0000000..3bd8644 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_crc_hal.h @@ -0,0 +1,530 @@ +/* + * Copyright (c) 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#if !defined(__FSL_CRC_HAL_H__) +#define __FSL_CRC_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_CRC_COUNT + +/*! @addtogroup crc_hal*/ +/*! @{*/ + +/*! @file*/ + +/*!***************************************************************************** + * Definitions + ******************************************************************************/ + +/*! + * @brief CRC status return codes. + */ +typedef enum _crc_status +{ + kStatus_CRC_Success = 0U, /*!< Success. */ + kStatus_CRC_InvalidArgument = 1U, /*!< Invalid argument existed. */ + kStatus_CRC_Failed = 2U /*!< Execution failed. */ +} crc_status_t; + +/*! + * @brief Define type of enumerating transpose modes for CRC peripheral. + */ +typedef enum _crc_transpose +{ + kCrcNoTranspose = 0U, /*!< No transposition. @internal gui name="No Transpose" */ + kCrcTransposeBits = 1U, /*!< Bits in bytes are transposed; bytes are not transposed. @internal gui name="Transpose Bits" */ + kCrcTransposeBoth = 2U, /*!< Both bits in bytes and bytes are transposed. @internal gui name="Transpose Bits in Bytes and Bytes" */ + kCrcTransposeBytes = 3U /*!< Only bytes are transposed; no bits in a byte are transposed. @internal gui name="Transpose Bytes" */ +}crc_transpose_t; + +/*! + * @brief Define type of enumerating CRC protocol widths for CRC peripheral. + */ +typedef enum _crc_prot_width +{ + kCrc16Bits = 0U, /*!< 16-bit CRC protocol. @internal gui name="16 bits" */ + kCrc32Bits = 1U, /*!< 32-bit CRC protocol. @internal gui name="32 bits" */ +}crc_prot_width_t; + +/*!***************************************************************************** + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! @name CRC-related feature APIs*/ + +/*! + * @brief This function initializes the module to a known state. + * + * @param base The CRC peripheral base address. + */ +void CRC_HAL_Init(CRC_Type * base); + +/*! + * @brief Returns the current CRC result from the data register. + * + * @param base The CRC peripheral base address. + * @return Returns a 32-bit value. + */ +static inline uint32_t CRC_HAL_GetDataReg(CRC_Type * base) +{ +#if FSL_FEATURE_CRC_HAS_CRC_REG + return CRC_RD_CRC(base); +#else + return CRC_RD_DATA(base); +#endif +} + +/*! + * @brief Returns the upper 16 bits of the current CRC result from the data register. + * + * @param base The CRC peripheral base address. + * @return Returns a 16-bit value. + */ +static inline uint16_t CRC_HAL_GetDataHReg(CRC_Type * base) +{ +#if FSL_FEATURE_CRC_HAS_CRC_REG + return CRC_RD_CRCH(base); +#else + return CRC_RD_DATAH(base); +#endif +} + +/*! + * @brief Returns the lower 16 bits of the current CRC result from the data register. + * + * @param base The CRC peripheral base address. + * @return Returns a 16-bit value. + */ +static inline uint16_t CRC_HAL_GetDataLReg(CRC_Type * base) +{ +#if FSL_FEATURE_CRC_HAS_CRC_REG + return CRC_RD_CRCL(base); +#else + return CRC_RD_DATAL(base); +#endif +} + +/*! + * @brief Sets the CRC data register (4 bytes). + * + * @param base The CRC peripheral base address. + * @param value New data for CRC computation. This parameter is a 32-bit value. + */ +static inline void CRC_HAL_SetDataReg(CRC_Type * base, uint32_t value) +{ +#if FSL_FEATURE_CRC_HAS_CRC_REG + CRC_WR_CRC(base, value); +#else + CRC_WR_DATA(base, value); +#endif +} + +/*! + * @brief Sets the CRC data register (upper 2 bytes). + * + * @param base The CRC peripheral base address. + * @param value New data for CRC computation. This parameter is a 16-bit value. + */ +static inline void CRC_HAL_SetDataHReg(CRC_Type * base, uint16_t value) +{ +#if FSL_FEATURE_CRC_HAS_CRC_REG + CRC_WR_CRCH(base, value); +#else + CRC_WR_DATAH(base, value); +#endif +} + +/*! + * @brief Sets the CRC data register (lower 2 bytes). + * + * @param base The CRC peripheral base address. + * @param value New data for CRC computation. This parameter is a 16-bit value. + */ +static inline void CRC_HAL_SetDataLReg(CRC_Type * base, uint16_t value) +{ +#if FSL_FEATURE_CRC_HAS_CRC_REG + CRC_WR_CRCL(base, value); +#else + CRC_WR_DATAL(base, value); +#endif +} + +/*! + * @brief Sets the CRC data register (HL byte). + * + * @param base The CRC peripheral base address. + * @param value New data for CRC computation. This parameter is a 8-bit value. + */ +static inline void CRC_HAL_SetDataHLReg(CRC_Type * base, uint8_t value) +{ +#if FSL_FEATURE_CRC_HAS_CRC_REG + CRC_WR_CRCHL(base, value); +#else + CRC_WR_DATAHL(base, value); +#endif +} + +/*! + * @brief Sets the CRC data register (HU byte). + * + * @param base The CRC peripheral base address. + * @param value New data for CRC computation. This parameter is a 8-bit value. + */ +static inline void CRC_HAL_SetDataHUReg(CRC_Type * base, uint8_t value) +{ +#if FSL_FEATURE_CRC_HAS_CRC_REG + CRC_WR_CRCHU(base, value); +#else + CRC_WR_DATAHU(base, value); +#endif +} + +/*! + * @brief Sets the CRC data register (LL byte). + * + * @param base The CRC peripheral base address. + * @param value New data for CRC computation. This parameter is a 8-bit value. + */ +static inline void CRC_HAL_SetDataLLReg(CRC_Type * base, uint8_t value) +{ +#if FSL_FEATURE_CRC_HAS_CRC_REG + CRC_WR_CRCLL(base, value); +#else + CRC_WR_DATALL(base, value); +#endif +} + +/*! + * @brief Sets the CRC data register (LU byte). + * + * @param base The CRC peripheral base address. + * @param value New data for CRC computation. This parameter is a 8-bit value. + */ +static inline void CRC_HAL_SetDataLUReg(CRC_Type * base, uint8_t value) +{ +#if FSL_FEATURE_CRC_HAS_CRC_REG + CRC_WR_CRCLU(base, value); +#else + CRC_WR_DATALU(base, value); +#endif +} + +/*! + * @brief Returns the polynomial register value. + * + * @param base The CRC peripheral base address. + * @return Returns a 32-bit value. + */ +static inline uint32_t CRC_HAL_GetPolyReg(CRC_Type * base) +{ + return CRC_RD_GPOLY(base); +} + +/*! + * @brief Returns the upper 16 bits of polynomial register. + * + * @param base The CRC peripheral base address. + * @return Returns a 16-bit value. + */ +static inline uint16_t CRC_HAL_GetPolyHReg(CRC_Type * base) +{ + return CRC_RD_GPOLYH(base); +} + +/*! + * @brief Returns the lower 16 bits of polynomial register. + * + * @param base The CRC peripheral base address. + * @return Returns a 16-bit value. + */ +static inline uint16_t CRC_HAL_GetPolyLReg(CRC_Type * base) +{ + return CRC_RD_GPOLYL(base); +} + +/*! + * @brief Sets the polynomial register. + * + * @param base The CRC peripheral base address. + * @param value Polynomial value. This parameter is a 32-bit value. + */ +static inline void CRC_HAL_SetPolyReg(CRC_Type * base, uint32_t value) +{ + CRC_WR_GPOLY(base, value); +} + +/*! + * @brief Sets the upper 16 bits of polynomial register. + * + * @param base The CRC peripheral base address. + * @param value Polynomial value. This parameter is a 16-bit value. + */ +static inline void CRC_HAL_SetPolyHReg(CRC_Type * base, uint16_t value) +{ + CRC_WR_GPOLYH(base, value); +} + +/*! + * @brief Sets the lower 16 bits of polynomial register. + * + * @param base The CRC peripheral base address. + * @param value Polynomial value. This parameter is a 16-bit value. + */ +static inline void CRC_HAL_SetPolyLReg(CRC_Type * base, uint16_t value) +{ + CRC_WR_GPOLYL(base, value); +} + +/*! + * @brief Returns the CRC control register. + * + * @param base The CRC peripheral base address. + * @return Returns a 32-bit value. + */ +static inline uint32_t CRC_HAL_GetCtrlReg(CRC_Type * base) +{ + return CRC_RD_CTRL(base); +} + +/*! + * @brief Sets the CRC control register. + * + * @param base The CRC peripheral base address. + * @param value Control register value. This parameter is a 32-bit value. + */ +static inline void CRC_HAL_SetCtrlReg(CRC_Type * base, uint32_t value) +{ + CRC_WR_CTRL(base, value); +} + +/*! + * @brief Gets the CRC seed mode. + * + * @param base The CRC peripheral base address. + * @return CRC seed mode + * -true: Seed mode is enabled + * -false: Data mode is enabled + */ +static inline bool CRC_HAL_GetSeedOrDataMode(CRC_Type * base) +{ + return (bool)CRC_BRD_CTRL_WAS(base); +} + +/*! + * @brief Sets the CRC seed mode. + * + * @param base The CRC peripheral base address. + * @param enable Enable or disable seed mode. + -true: use CRC data register for seed values + -false: use CRC data register for data values + */ +static inline void CRC_HAL_SetSeedOrDataMode(CRC_Type * base, bool enable) +{ + CRC_BWR_CTRL_WAS(base, enable); +} + +/*! + * @brief Gets the CRC transpose type for writes. + * + * @param base The CRC peripheral base address. + * @return CRC input transpose type for writes. + */ +static inline crc_transpose_t CRC_HAL_GetWriteTranspose(CRC_Type * base) +{ + return (crc_transpose_t)CRC_BRD_CTRL_TOT(base); +} + +/*! + * @brief Sets the CRC transpose type for writes. + * + * @param base The CRC peripheral base address. + * @param transp The CRC input transpose type. + */ +static inline void CRC_HAL_SetWriteTranspose(CRC_Type * base, crc_transpose_t transp) +{ + CRC_BWR_CTRL_TOT(base, transp); +} + +/*! + * @brief Gets the CRC transpose type for reads. + * + * @param base The CRC peripheral base address. + * @return CRC output transpose type. + */ +static inline crc_transpose_t CRC_HAL_GetReadTranspose(CRC_Type * base) +{ + return (crc_transpose_t)CRC_BRD_CTRL_TOTR(base); +} + +/*! + * @brief Sets the CRC transpose type for reads. + * + * @param base The CRC peripheral base address. + * @param transp The CRC output transpose type. + */ +static inline void CRC_HAL_SetReadTranspose(CRC_Type * base, crc_transpose_t transp) +{ + CRC_BWR_CTRL_TOTR(base, transp); +} + +/*! + * @brief Gets the CRC XOR mode. + * + * Some CRC protocols require the final checksum to be XORed with 0xFFFFFFFF + * or 0xFFFF. XOR mode enables "on the fly" complementing of read data. + * + * @param base The CRC peripheral base address. + * @return CRC XOR mode + * -true: XOR mode is enabled + * -false: XOR mode is disabled + */ +static inline bool CRC_HAL_GetXorMode(CRC_Type * base) +{ + return (bool)CRC_BRD_CTRL_FXOR(base); +} + +/*! + * @brief Sets the CRC XOR mode. + * + * Some CRC protocols require the final checksum to be XORed with 0xFFFFFFFF + * or 0xFFFF. XOR mode enables "on the fly" complementing of read data. + * + * @param base The CRC peripheral base address. + * @param enable Enable or disable XOR mode. + */ +static inline void CRC_HAL_SetXorMode(CRC_Type * base, bool enable) +{ + CRC_BWR_CTRL_FXOR(base, enable); +} + +/*! + * @brief Gets the CRC protocol width. + * + * @param base The CRC peripheral base address. + * @return CRC protocol width + * -kCrc16Bits: 16-bit CRC protocol + * -kCrc32Bits: 32-bit CRC protocol + */ +static inline crc_prot_width_t CRC_HAL_GetProtocolWidth(CRC_Type * base) +{ + return (crc_prot_width_t)CRC_BRD_CTRL_TCRC(base); +} + +/*! + * @brief Sets the CRC protocol width. + * + * @param base The CRC peripheral base address. + * @param width The CRC protocol width + * -kCrc16Bits: 16-bit CRC protocol + * -kCrc32Bits: 32-bit CRC protocol + */ +static inline void CRC_HAL_SetProtocolWidth(CRC_Type * base, crc_prot_width_t width) +{ + CRC_BWR_CTRL_TCRC(base, width); +} + +/*! + * @brief CRC_HAL_GetCrc32 + * + * This method appends 32-bit data to the current CRC calculation + * and returns new result. If the newSeed is true, seed set and + * result are calculated from the seed new value (new CRC calculation). + * + * @param base The CRC peripheral base address. + * @param data input data for CRC calculation + * @param newSeed Sets new CRC calculation. + * - true: New seed set and used for new calculation. + * - false: seed argument ignored, continues old calculation. + * @param seed New seed if newSeed is true, else ignored + * @return new CRC result. + */ +uint32_t CRC_HAL_GetCrc32(CRC_Type * base, uint32_t data, bool newSeed, uint32_t seed); + +/*! + * @brief CRC_HAL_GetCrc16 + * + * This method appends the 16-bit data to the current CRC calculation + * and returns a new result. If the newSeed is true, seed set and + * result are calculated from the seed new value (new CRC calculation). + * + * @param base The CRC peripheral base address. + * @param data input data for CRC calculation + * @param newSeed Sets new CRC calculation. + * - true: New seed set and used for new calculation. + * - false: seed argument ignored, continues old calculation. + * @param seed New seed if newSeed is true, else ignored + * @return new CRC result. + */ +uint32_t CRC_HAL_GetCrc16(CRC_Type * base, uint16_t data, bool newSeed, uint32_t seed); + +/*! + * @brief CRC_HAL_GetCrc8 + * + * This method appends the 8-bit data to the current CRC calculation + * and returns the new result. If the newSeed is true, seed set and + * result are calculated from the seed new value (new CRC calculation). + * + * @param base The CRC peripheral base address. + * @param data input data for CRC calculation + * @param newSeed Sets new CRC calculation. + * - true: New seed set and used for new calculation. + * - false: seed argument ignored, continues old calculation. + * @param seed New seed if newSeed is true, else ignored + * @return new CRC result. + */ +uint32_t CRC_HAL_GetCrc8(CRC_Type * base, uint8_t data, bool newSeed, uint32_t seed); + +/*! + * @brief CRC_HAL_GetCrcResult + * + * This method returns the current result of the CRC calculation. + * The result is the ReadTranspose dependent. + * + * @param base The CRC peripheral base address. + * @return result of CRC calculation. + */ +uint32_t CRC_HAL_GetCrcResult(CRC_Type * base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif +#endif /* __FSL_CRC_HAL_H__*/ diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_dac_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_dac_hal.h new file mode 100755 index 0000000..c1d4c1c --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_dac_hal.h @@ -0,0 +1,393 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_DAC_HAL_H__ +#define __FSL_DAC_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> +#include <assert.h> +#include "fsl_device_registers.h" + +#if FSL_FEATURE_SOC_DAC_COUNT + +/*! + * @addtogroup dac_hal + * @{ + */ + +/****************************************************************************** + * Enumerations + *****************************************************************************/ + +/*! + * @brief DAC status return codes. + */ +typedef enum _dac_status +{ + kStatus_DAC_Success = 0U, /*!< Success. */ + kStatus_DAC_InvalidArgument = 1U, /*!< Invalid argument existed. */ + kStatus_DAC_Failed = 2U /*!< Execution failed. */ +} dac_status_t; + +/*! + * @brief Defines the type of selection for DAC module's reference voltage source. + * + * See the appropriate SoC Reference Manual for actual connections. + */ +typedef enum _dac_ref_volt_src_mode +{ + kDacRefVoltSrcOfVref1 = 0U, /*!< Select DACREF_1 as the reference voltage. @internal gui name="Reference 1" */ + kDacRefVoltSrcOfVref2 = 1U /*!< Select DACREF_2 as the reference voltage. @internal gui name="Reference 2" */ +} dac_ref_volt_src_mode_t; + +/*! + * @brief Defines the type of selection for DAC module trigger mode. + */ +typedef enum _dac_trigger_mode +{ + kDacTriggerByHardware = 0U, /*!< Select hardware trigger. @internal gui name="HW" */ + kDacTriggerBySoftware = 1U /*!< Select software trigger. @internal gui name="SW" */ +} dac_trigger_mode_t; + +/*! + * @brief Defines the type of selection for buffer watermark mode. + * + * If the buffer feature for DAC module is enabled, a watermark event will + * occur when the buffer index hits the watermark. + */ +typedef enum _dac_buff_watermark_mode +{ + kDacBuffWatermarkFromUpperAs1Word = 0U, /*!< Select 1 word away from the upper limit of buffer. @internal gui name="1 word in normal, 2 words in FIFO mode" */ + kDacBuffWatermarkFromUpperAs2Word = 1U, /*!< Select 2 word away from the upper limit of buffer. @internal gui name="2 word in normal, 4 words in FIFO mode" */ + kDacBuffWatermarkFromUpperAs3Word = 2U, /*!< Select 3 word away from the upper limit of buffer. @internal gui name="3 word in normal, 8 words in FIFO mode" */ + kDacBuffWatermarkFromUpperAs4Word = 3U /*!< Select 4 word away from the upper limit of buffer. @internal gui name="4 word in normal, 14 words in FIFO mode" */ +} dac_buff_watermark_mode_t; + +/*! + * @brief Defines the type of selection for buffer work mode. + * + * These are the work modes when the DAC buffer is enabled.\n + * \li Normal mode - When the buffer index hits the upper level, it + * starts (0) on the next trigger. + * \li Swing mode - When the buffer index hits the upper level, it goes backward to + * the start and is reduced one-by-one on the next trigger. When the buffer index + * hits the start, it goes backward to the upper level and increases one-by-one + * on the next trigger. + * \li One-Time-Scan mode - The buffer index can only be increased on the next trigger. + * When the buffer index hits the upper level, it is not updated by the trigger. + * \li FIFO mode - In FIFO mode, the buffer is organized as a FIFO. For a valid + * write to any item, the data will be put into the FIFO. The written index + * in buffer should be an EVEN number; otherwise, the write will be ignored. + */ +typedef enum _dac_buff_work_mode +{ + kDacBuffWorkAsNormalMode = 0U /*!< Buffer works as Normal. @internal gui name="Normal" */ +/* For 1-bit DACBFMD. */ +#if DAC_C1_DACBFMD_WIDTH==1 + ,kDacBuffWorkAsOneTimeScanMode = 1U /*!< Buffer works as one time scan. @internal gui name="" */ +/* For 2-bit DACBFMD. */ +#elif DAC_C1_DACBFMD_WIDTH==2 +#if FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE + ,kDacBuffWorkAsSwingMode = 1U /*!< Buffer works as swing. @internal gui name="Swing mode" */ +#endif /* FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE */ + ,kDacBuffWorkAsOneTimeScanMode = 2U /*!< Buffer works as one time scan. @internal gui name="One-time scan" */ +#if FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE + ,kDacBuffWorkAsFIFOMode = 3U /*!< Buffer works as FIFO. @internal gui name="FIFO" */ +#endif /* FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE */ +#endif /* DAC_C1_DACBFMD_WIDTH */ +} dac_buff_work_mode_t; + +/****************************************************************************** + * Definitions + *****************************************************************************/ +/*! + * @brief Defines the type of structure for configuring the DAC converter. + * @internal gui name="Basic configuration" id="dacCfg" + */ +typedef struct DacConverterConfig +{ + dac_ref_volt_src_mode_t dacRefVoltSrc; /*!< Select the reference voltage source. @internal gui name="Voltage reference" id="VoltageReference" */ + bool lowPowerEnable; /*!< Enable the low power mode. @internal gui name="Low power mode" id="LowPowerMode" */ +} dac_converter_config_t; + +/*! + * @brief Defines the type of structure for configuring the DAC buffer. + * @internal gui name="Buffer configuration" id="dacBuffCfg" + */ +typedef struct DacBufferConfig +{ + bool bufferEnable; /*!< Enable the buffer function. @internal gui name="Buffer" id="Buffer" */ + dac_trigger_mode_t triggerMode; /*!< Select the trigger mode. @internal gui name="Trigger mode" id="TriggerMode" */ + /* Buffer interrupt. */ +#if FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION + bool idxWatermarkIntEnable; + /*!< Switcher to enable interrupt when buffer index hits the watermark. @internal gui name="Watermark interrupt" id="WatermarkInterrupt" */ + dac_buff_watermark_mode_t watermarkMode; + /*!< Selection of watermark setting. See "dac_buff_watermark_mode_t". @internal gui name="Watermark mode" id="WatermarkMode" */ +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */ + bool idxStartIntEnable; + /*!< Switcher to enable interrupt when buffer index hits the start (0). @internal gui name="Buffer bottom interrupt" id="BufferBottomInterrupt" */ + bool idxUpperIntEnable; + /*!< Switcher to enable interrupt when buffer index hits the upper limit. @internal gui name="Buffer top interrupt" id="BufferTopInterrupt" */ + bool dmaEnable; /*!< Switcher to enable DMA request by original interrupts. @internal gui name="DMA" id="DMASupport" */ + dac_buff_work_mode_t buffWorkMode; + /*!< Selection of buffer's work mode. See "dac_buff_work_mode_t". @internal gui name="Buffer mode" id="BufferMode" */ + uint8_t upperIdx; /*!< Setting of the buffer's upper limit, 0-15. @internal gui name="Upper limit" id="UpperLimit" */ +} dac_buffer_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Resets all configurable registers to be in the reset state for DAC. + * + * This function resets all configurable registers to be in the reset state for DAC. + * It should be called before configuring the DAC module. + * + * @param base The DAC peripheral base address. + */ +void DAC_HAL_Init(DAC_Type * base); + +/*--------------------------------------------------------------------------* +* DAC converter. +*--------------------------------------------------------------------------*/ +/*! + * @brief Configures the converter for DAC. + * + * This function configures the converter for DAC. The features it covers are a + * one-time setting in the application. + * + * @param base The DAC peripheral base address. + * @param configPtr The pointer to configure structure. + */ +void DAC_HAL_ConfigConverter(DAC_Type * base, const dac_converter_config_t *configPtr); + +/*--------------------------------------------------------------------------* +* DAC buffer. +*--------------------------------------------------------------------------*/ + +/*! + * @brief Configures the buffer for DAC. + * + * This function configures the converter for DAC. The features it covers are used + * for the buffer. + * + * @param base The DAC peripheral base address. + * @param configPtr The pointer to configure structure. + */ +void DAC_HAL_ConfigBuffer(DAC_Type * base, const dac_buffer_config_t *configPtr); + +/*! + * @brief Sets the 12-bit value for the DAC items in the buffer. + * + * This function sets the value assembled by the low 8 bits and high 4 + * bits of 12-bit DAC item in the buffer. + * + * @param base The DAC peripheral base address. + * @param idx Buffer index. + * @param value Setting value. + */ +void DAC_HAL_SetBuffValue(DAC_Type * base, uint8_t idx, uint16_t value); + +/*! + * @brief Clears the flag of the DAC buffer read pointer. + * + * This function clears the flag of the DAC buffer read pointer when it hits the + * bottom position. + * + * @param base The DAC peripheral base address. + */ +static inline void DAC_HAL_ClearBuffIdxUpperFlag(DAC_Type * base) +{ + DAC_BWR_SR_DACBFRPBF(base, 0U); +} + +/*! + * @brief Gets the flag of the DAC buffer read pointer when it hits the bottom position. + * + * This function gets the flag of DAC buffer read pointer when it hits the + * bottom position. + * + * @param base The DAC peripheral base address. + * @return Assertion of indicated event. + */ +static inline bool DAC_HAL_GetBuffIdxUpperFlag(DAC_Type * base) +{ + return ( 1U == DAC_BRD_SR_DACBFRPBF(base) ); +} + +/*! + * @brief Clears the flag of the DAC buffer read pointer when it hits the top position. + * + * This function clears the flag of the DAC buffer read pointer when it hits the + * top position. + * + * @param base The DAC peripheral base address. + */ +static inline void DAC_HAL_ClearBuffIdxStartFlag(DAC_Type * base) +{ + DAC_BWR_SR_DACBFRPTF(base, 0U); +} + +/*! + * @brief Gets the flag of the DAC buffer read pointer when it hits the top position. + * + * This function gets the flag of the DAC buffer read pointer when it hits the + * top position. + * + * @param base The DAC peripheral base address. + * @return Assertion of indicated event. + */ +static inline bool DAC_HAL_GetBuffIdxStartFlag(DAC_Type * base) +{ + return ( 1U == DAC_BRD_SR_DACBFRPTF(base) ); +} + +#if FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION + +/*! + * @brief Gets the flag of the DAC buffer read pointer when it hits the watermark position. + * + * This function gets the flag of the DAC buffer read pointer when it hits the + * watermark position. + * + * @param base The DAC peripheral base address. + * @return Assertion of indicated event. + */ +static inline bool DAC_HAL_GetBuffIdxWatermarkFlag(DAC_Type * base) +{ + return ( 1U == DAC_BRD_SR_DACBFWMF(base) ); +} + +/*! + * @brief Clears the flag of the DAC buffer read pointer when it hits the watermark position. + * + * This function clears the flag of the DAC buffer read pointer when it hits the + * watermark position. + * + * @param base The DAC peripheral base address. + */ +static inline void DAC_HAL_ClearBuffIdxWatermarkFlag(DAC_Type * base) +{ + DAC_BWR_SR_DACBFWMF(base, 0U); +} +#endif /* FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION */ + +/*! + * @brief Enables the Programmable Reference Generator. + * + * This function enables the Programmable Reference Generator. Then, the + * DAC system is enabled. + * + * @param base The DAC peripheral base address. + */ +static inline void DAC_HAL_Enable(DAC_Type * base) +{ + DAC_BWR_C0_DACEN(base, 1U); +} + +/*! + * @brief Disables the Programmable Reference Generator. + * + * This function disables the Programmable Reference Generator. Then, the + * DAC system is disabled. + * + * @param base The DAC peripheral base address. + */ +static inline void DAC_HAL_Disable(DAC_Type * base) +{ + DAC_BWR_C0_DACEN(base, 0U); +} + +/*! + * @brief Triggers the converter with software. + * + * This function triggers the converter with software. If the DAC software + * trigger is selected and buffer enabled, calling this API advances the + * buffer read pointer once. + * + * @param base The DAC peripheral base address. + */ +static inline void DAC_HAL_SetSoftTriggerCmd(DAC_Type * base) +{ + /* DAC_BWR_C0_DACSWTRG(base, 1U); */ + /* For supporting some chips with no bit-band access. */ + DAC_SET_C0(base, DAC_C0_DACSWTRG_MASK); +} + +/*! + * @brief Sets the buffer index for the DAC module. + * + * This function sets the current buffer index for the DAC module. + * + * @param base the DAC peripheral base address. + * @param idx Setting buffer index. + */ +static inline void DAC_HAL_SetBuffCurIdx(DAC_Type * base, uint8_t idx) +{ + assert(idx < DAC_DATL_COUNT); + DAC_BWR_C2_DACBFRP(base, idx); +} + +/*! + * @brief Gets the buffer index for the DAC module. + * + * This function gets the current buffer index for the DAC module. + * + * @param base the DAC peripheral base address. + * @return Current index of buffer. + */ +static inline uint8_t DAC_HAL_GetBuffCurIdx(DAC_Type * base) +{ + return DAC_BRD_C2_DACBFRP(base); +} + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* __FSL_DAC_HAL_H__ */ + +/****************************************************************************** + * EOF + *****************************************************************************/ + + +#endif diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_dma_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_dma_hal.h new file mode 100755 index 0000000..f006b8a --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_dma_hal.h @@ -0,0 +1,496 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_DMA_HAL_H__ +#define __FSL_DMA_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> +#include <assert.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_DMA_COUNT + +/*! + * @addtogroup dma_hal + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief DMA status */ +typedef enum _dma_status +{ + kStatus_DMA_Success = 0U, + kStatus_DMA_InvalidArgument = 1U, /*!< Parameter is not available for the current + configuration. */ + kStatus_DMA_Fail = 2U /*!< Function operation failed. */ +} dma_status_t; + +/*! @brief DMA transfer size type*/ +typedef enum _dma_transfer_size { + kDmaTransfersize32bits = 0x0U, /*!< 32 bits are transferred for every read/write */ + kDmaTransfersize8bits = 0x1U, /*!< 8 bits are transferred for every read/write */ + kDmaTransfersize16bits = 0x2U /*!< 16b its are transferred for every read/write */ +} dma_transfer_size_t; + +/*! @brief Configuration type for the DMA modulo */ +typedef enum _dma_modulo { + kDmaModuloDisable = 0x0U, + kDmaModulo16Bytes = 0x1U, + kDmaModulo32Bytes = 0x2U, + kDmaModulo64Bytes = 0x3U, + kDmaModulo128Bytes = 0x4U, + kDmaModulo256Bytes = 0x5U, + kDmaModulo512Bytes = 0x6U, + kDmaModulo1KBytes = 0x7U, + kDmaModulo2KBytes = 0x8U, + kDmaModulo4KBytes = 0x9U, + kDmaModulo8KBytes = 0xaU, + kDmaModulo16KBytes = 0xbU, + kDmaModulo32KBytes = 0xcU, + kDmaModulo64KBytes = 0xdU, + kDmaModulo128KBytes = 0xeU, + kDmaModulo256KBytes = 0xfU, +} dma_modulo_t; + +/*! @brief DMA channel link type */ +typedef enum _dma_channel_link_type { + kDmaChannelLinkDisable = 0x0U, /*!< No channel link */ + kDmaChannelLinkChan1AndChan2 = 0x1U, /*!< Perform a link to channel 1 after each cycle-steal + transfer followed by a link and to channel 2 after the + BCR decrements to zeros. */ + kDmaChannelLinkChan1 = 0x2U, /*!< Perform a link to channel 1 after each cycle-steal + transfer. */ + kDmaChannelLinkChan1AfterBCR0 = 0x3U /*!< Perform a link to channel1 after the BCR decrements + to zero. */ +} dma_channel_link_type_t; + +/*! @brief Data structure for data structure configuration */ +typedef struct DmaChannelLinkConfig { + dma_channel_link_type_t linkType; /*!< Channel link type */ + uint32_t channel1; /*!< Channel 1 configuration */ + uint32_t channel2; /*!< Channel 2 configuration */ +} dma_channel_link_config_t; + +/*! @brief Data structure to get status of the DMA channel status */ +typedef struct DmaErrorStatus { + uint32_t dmaBytesToBeTransffered; /*!< Bytes to be transferred */ + bool dmaTransDone; /*!< DMA channel transfer is done. */ + bool dmaBusy; /*!< DMA is running. */ + bool dmaPendingRequest; /*!< A transfer remains. */ + bool dmaDestBusError; /*!< Bus error on destination address */ + bool dmaSourceBusError; /*!< Bus error on source address */ + bool dmaConfigError; /*!< Configuration error */ +} dma_error_status_t; + +/*! @brief Type for DMA transfer. */ +typedef enum _dma_transfer_type { + kDmaPeripheralToMemory, /*!< Transfer from the peripheral to memory */ + kDmaMemoryToPeripheral, /*!< Transfer from the memory to peripheral */ + kDmaMemoryToMemory, /*!< Transfer from the memory to memory */ + kDmaPeripheralToPeripheral /*!< Transfer from the peripheral to peripheral */ +} dma_transfer_type_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name DMA HAL channel configuration + * @{ + */ + +/*! + * @brief Sets all registers of the channel to 0. + * + * @param base DMA base. + * @param channel DMA channel. + */ +void DMA_HAL_Init(DMA_Type * base, uint32_t channel); + +/*! + * @brief Basic DMA transfer configuration. + * + * @param base DMA base. + * @param channel DMA channel. + * @param size Size to be transferred on each DMA write/read. Source/Dest share the same write/read + * size. + * @param type Transfer type. + * @param sourceAddr Source address. + * @param destAddr Destination address. + * @param length Bytes to be transferred. + */ +void DMA_HAL_ConfigTransfer( + DMA_Type * base, uint32_t channel, dma_transfer_size_t size, dma_transfer_type_t type, + uint32_t sourceAddr, uint32_t destAddr, uint32_t length); + +/*! + * @brief Configures the source address. + * + * Each SAR contains the byte address used by the DMA to read data. The SARn is typically + * aligned on a 0-modulo-size boundary-that is on the natural alignment of the source data. + * Bits 31-20 of this register must be written with one of the only four allowed values. Each of these + * allowed values corresponds to a valid region of the devices' memory map. The allowed values + * are: + * 0x000x_xxxx + * 0x1FFx_xxxx + * 0x200x_xxxx + * 0x400x_xxxx + * After they are written with one of the allowed values, bits 31-20 read back as the written value. + * After they are written with any other value, bits 31-20 read back as an indeterminate value. + * + * This function enables the request for a specified channel. + * + * @param base DMA base. + * @param channel DMA channel. + * @param address memory address pointing to the source address. + */ +static inline void DMA_HAL_SetSourceAddr( + DMA_Type * base, uint32_t channel, uint32_t address) +{ + assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS); + DMA_WR_SAR(base, channel, address); +} + +/*! + * @brief Configures the source address. + * + * Each DAR contains the byte address used by the DMA to read data. The DARn is typically + * aligned on a 0-modulo-size boundary-that is on the natural alignment of the source data. + * Bits 31-20 of this register must be written with one of the only four allowed values. Each of these + * allowed values corresponds to a valid region of the devices' memory map. The allowed values + * are: + * 0x000x_xxxx + * 0x1FFx_xxxx + * 0x200x_xxxx + * 0x400x_xxxx + * After they are written with one of the allowed values, bits 31-20 read back as the written value. + * After they are written with any other value, bits 31-20 read back as an indeterminate value. + * + * This function enables the request for specified channel. + * + * @param base DMA base. + * @param channel DMA channel. + * @param address Destination address. + */ +static inline void DMA_HAL_SetDestAddr( + DMA_Type * base, uint32_t channel, uint32_t address) +{ + assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS); + DMA_WR_DAR(base, channel, address); +} + +/*! + * @brief Configures the bytes to be transferred. + * + * Transfer bytes must be written with a value equal to or less than 0F_FFFFh. After being written + * with a value in this range, bits 23-20 of the BCR read back as 1110b. A write to the BCR with a value + * greater than 0F_FFFFh causes a configuration error when the channel starts to execute. After + * they are written with a value in this range, bits 23-20 of BCR read back as 1111b. + * + * @param base DMA base. + * @param channel DMA channel. + * @param count bytes to be transferred. + */ +static inline void DMA_HAL_SetTransferCount( + DMA_Type * base, uint32_t channel, uint32_t count) +{ + assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS); + DMA_BWR_DSR_BCR_BCR(base, channel, count); +} + +/*! + * @brief Gets the left bytes not to be transferred. + * + * @param base DMA base. + * @param channel DMA channel. + * @return unfinished bytes. + */ +static inline uint32_t DMA_HAL_GetUnfinishedByte(DMA_Type * base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS); + return DMA_RD_DSR_BCR(base, channel) & DMA_DSR_BCR_BCR_MASK; +} + +/*! + * @brief Enables the interrupt for the DMA channel after the work is done. + * + * This function enables the request for specified channel. + * + * @param base DMA base. + * @param channel DMA channel. + * @param enable True means enable interrupt, false means disable. + */ +static inline void DMA_HAL_SetIntCmd(DMA_Type * base, uint8_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS); + DMA_BWR_DCR_EINT(base, channel, enable); +} + +/*! + * @brief Configures the DMA transfer mode to cycle steal or continuous modes. + * + * If continuous mode is enabled, DMA continuously makes write/read transfers until BCR decrement to + * 0. If continuous mode is disabled, DMA write/read is only triggered on every request. + *s + * @param base DMA base. + * @param channel DMA channel. + * @param enable 1 means cycle-steal mode, 0 means continuous mode. + */ +static inline void DMA_HAL_SetCycleStealCmd( + DMA_Type * base, uint8_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS); + DMA_BWR_DCR_CS(base, channel, enable); +} + +/*! + * @brief Configures the auto-align feature. + * + * If auto-align is enabled, the appropriate address register increments, regardless of whether it is a source increment or + * a destination increment. + * + * @param base DMA base. + * @param channel DMA channel. + * @param enable 0 means disable auto-align. 1 means enable auto-align. + */ +static inline void DMA_HAL_SetAutoAlignCmd( + DMA_Type * base, uint8_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS); + DMA_BWR_DCR_AA(base, channel, enable); +} + +/*! + * @brief Configures the a-sync DMA request feature. + * + * Enables/disables the a-synchronization mode in a STOP mode for each DMA channel. + * + * @param base DMA base. + * @param channel DMA channel. + * @param enable 0 means disable DMA request a-sync. 1 means enable DMA request -. + */ +static inline void DMA_HAL_SetAsyncDmaRequestCmd( + DMA_Type * base, uint8_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS); + DMA_BWR_DCR_EADREQ(base, channel, enable); +} + +/*! + * @brief Enables/disables the source increment. + * + * Controls whether the source address increments after each successful transfer. If enabled, the + * SAR increments by 1,2,4 as determined by the transfer size. + * + * @param base DMA base. + * @param channel DMA channel. + * @param enable Enabled/Disable increment. + */ +static inline void DMA_HAL_SetSourceIncrementCmd( + DMA_Type * base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS); + DMA_BWR_DCR_SINC(base, channel, enable); +} + +/*! + * @brief Enables/disables destination increment. + * + * Controls whether the destination address increments after each successful transfer. If enabled, the + * DAR increments by 1,2,4 as determined by the transfer size. + * + * @param base DMA base. + * @param channel DMA channel. + * @param enable Enabled/Disable increment. + */ +static inline void DMA_HAL_SetDestIncrementCmd( + DMA_Type * base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS); + DMA_BWR_DCR_DINC(base, channel, enable); +} + +/*! + * @brief Configures the source transfer size. + * + * @param base DMA base. + * @param channel DMA channel. + * @param transfersize enum type for transfer size. + */ +static inline void DMA_HAL_SetSourceTransferSize( + DMA_Type * base, uint32_t channel, dma_transfer_size_t transfersize) +{ + assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS); + DMA_BWR_DCR_SSIZE(base, channel, transfersize); +} + +/*! + * @brief Configures the destination transfer size. + * + * @param base DMA base. + * @param channel DMA channel. + * @param transfersize enum type for transfer size. + */ +static inline void DMA_HAL_SetDestTransferSize( + DMA_Type * base, uint32_t channel, dma_transfer_size_t transfersize) +{ + assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS); + DMA_BWR_DCR_DSIZE(base, channel, transfersize); +} + +/*! + * @brief Triggers the start. + * + * When the DMA begins the transfer, the START bit is cleared automatically after one module clock and always + * reads as logic 0. + * + * @param base DMA base. + * @param channel DMA channel. + * @param enable Enable/disable trigger start. + */ +static inline void DMA_HAL_SetTriggerStartCmd(DMA_Type * base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS); + DMA_BWR_DCR_START(base, channel, enable); +} + +/*! + * @brief Configures the modulo for the source address. + * + * @param base DMA base. + * @param channel DMA channel. + * @param modulo enum data type for source modulo. + */ +static inline void DMA_HAL_SetSourceModulo( + DMA_Type * base, uint32_t channel, dma_modulo_t modulo) +{ + assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS); + DMA_BWR_DCR_SMOD(base, channel, modulo); +} + +/*! + * @brief Configures the modulo for the destination address. + * + * @param base DMA base. + * @param channel DMA channel. + * @param modulo enum data type for dest modulo. + */ +static inline void DMA_HAL_SetDestModulo( + DMA_Type * base, uint32_t channel, dma_modulo_t modulo) +{ + assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS); + DMA_BWR_DCR_DMOD(base, channel, modulo); +} + +/*! + * @brief Enables/disables the DMA request. + * + * @param base DMA base. + * @param channel DMA channel. + * @param enable Enable/disable dma request. + */ +static inline void DMA_HAL_SetDmaRequestCmd( + DMA_Type * base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS); + DMA_BWR_DCR_ERQ(base, channel, enable); +} + +/*! + * @brief Configures the DMA request state after the work is done. + * + * Disables/enables the DMA request after a DMA DONE is generated. If it works in the loop mode, this bit + * should not be set. + * @param base DMA base address. + * @param channel DMA channel. + * @param enable 0 means DMA request would not be disabled after work done. 1 means disable. + */ +static inline void DMA_HAL_SetDisableRequestAfterDoneCmd( + DMA_Type * base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS); + DMA_BWR_DCR_D_REQ(base, channel, enable); + +} + +/*! + * @brief Configures the channel link feature. + * + * @param base DMA base address. + * @param channel DMA channel. + * @param mode Mode of channel link in DMA. + */ +void DMA_HAL_SetChanLink( + DMA_Type * base, uint8_t channel, dma_channel_link_config_t *mode); + +/*! + * @brief Clears the status of the DMA channel. + * + * This function clears the status for a specified DMA channel. The error status and done status + * are cleared. + * @param base DMA base address. + * @param channel DMA channel. + */ +static inline void DMA_HAL_ClearStatus(DMA_Type * base, uint8_t channel) +{ + assert(channel < FSL_FEATURE_DMA_DMAMUX_CHANNELS); + DMA_BWR_DSR_BCR_DONE(base, channel, 1U); +} + +/*! + * @brief Gets the DMA controller channel status. + * + * Gets the status of the DMA channel. The user can get the error status, as to whether the descriptor is finished or there are bytes left. + * @param base DMA base address. + * @param channel DMA channel. + * @return Status of the DMA channel. + */ +dma_error_status_t DMA_HAL_GetStatus(DMA_Type * base, uint8_t channel); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif +#endif /* __FSL_DMA_HAL_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_dmamux_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_dmamux_hal.h new file mode 100755 index 0000000..728db3e --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_dmamux_hal.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_DMAMUX_HAL_H__ +#define __FSL_DMAMUX_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> +#include <assert.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_DMAMUX_COUNT + +/*! + * @addtogroup dmamux_hal + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! + * @brief A constant for the length of the DMA hardware source. This structure is used inside + * the DMA driver. + */ +typedef enum _dmamux_source { + kDmamuxDmaRequestSource = 64U /*!< Maximum number of the DMA requests allowed for the DMA mux. */ +} dmamux_dma_request_source; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name DMAMUX HAL function + * @{ + */ + +/*! + * @brief Initializes the DMAMUX module to the reset state. + * + * Initializes the DMAMUX module to the reset state. + * + * @param base Register base address for DMAMUX module. + */ +void DMAMUX_HAL_Init(DMAMUX_Type * base); + +/*! + * @brief Enables/Disables the DMAMUX channel. + * + * Enables the hardware request. If enabled, the hardware request is sent to + * the corresponding DMA channel. + * + * @param base Register base address for DMAMUX module. + * @param channel DMAMUX channel number. + * @param enable Enables (true) or Disables (false) DMAMUX channel. + */ +static inline void DMAMUX_HAL_SetChannelCmd(DMAMUX_Type * base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + DMAMUX_BWR_CHCFG_ENBL(base, channel, enable); +} + +#if (FSL_FEATURE_DMAMUX_HAS_TRIG == 1) +/*! + * @brief Enables/Disables the period trigger. + * + * @param base Register base address for DMAMUX module. + * @param channel DMAMUX channel number. + * @param enable Enables (true) or Disables (false) period trigger. + */ +static inline void DMAMUX_HAL_SetPeriodTriggerCmd(DMAMUX_Type * base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + DMAMUX_BWR_CHCFG_TRIG(base, channel, enable); +} +#endif + +/*! + * @brief Configures the DMA request for the DMAMUX channel. + * + * Sets the trigger source for the DMA channel. The trigger source is in the file + * fsl_dma_request.h. + * + * @param base Register base address for DMAMUX module. + * @param channel DMAMUX channel number. + * @param source DMA request source. + */ +static inline void DMAMUX_HAL_SetTriggerSource(DMAMUX_Type * base, uint32_t channel, uint8_t source) +{ + assert(channel < FSL_FEATURE_DMAMUX_MODULE_CHANNEL); + DMAMUX_BWR_CHCFG_SOURCE(base, channel, source); +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif +#endif /* __FSL_DMAMUX_HAL_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_dspi_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_dspi_hal.h new file mode 100755 index 0000000..af18b69 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_dspi_hal.h @@ -0,0 +1,917 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#if !defined(__FSL_DSPI_HAL_H__) +#define __FSL_DSPI_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> +#include "fsl_device_registers.h" + +#if FSL_FEATURE_SOC_DSPI_COUNT + +/*! + * @addtogroup dspi_hal + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Defines constant value arrays for the baud rate pre-scalar and scalar divider values.*/ +static const uint32_t s_baudratePrescaler[] = { 2, 3, 5, 7 }; +static const uint32_t s_baudrateScaler[] = { 2, 4, 6, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, + 4096, 8192, 16384, 32768 }; + +static const uint32_t s_delayPrescaler[] = { 1, 3, 5, 7 }; +static const uint32_t s_delayScaler[] = { 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, + 4096, 8192, 16384, 32768, 65536 }; + + +/*! @brief Error codes for the DSPI driver.*/ +typedef enum _dspi_status +{ + kStatus_DSPI_Success = 0, + kStatus_DSPI_SlaveTxUnderrun, /*!< DSPI Slave Tx Under run error*/ + kStatus_DSPI_SlaveRxOverrun, /*!< DSPI Slave Rx Overrun error*/ + kStatus_DSPI_Timeout, /*!< DSPI transfer timed out*/ + kStatus_DSPI_Busy, /*!< DSPI instance is already busy performing a + transfer.*/ + kStatus_DSPI_NoTransferInProgress, /*!< Attempt to abort a transfer when no transfer + was in progress*/ + kStatus_DSPI_InvalidBitCount, /*!< bits-per-frame value not valid*/ + kStatus_DSPI_InvalidInstanceNumber, /*!< DSPI instance number does not match current count*/ + kStatus_DSPI_OutOfRange, /*!< DSPI out-of-range error */ + kStatus_DSPI_InvalidParameter, /*!< DSPI invalid parameter error */ + kStatus_DSPI_NonInit, /*!< DSPI driver does not initialize, not ready */ + kStatus_DSPI_Initialized, /*!< DSPI driver has initialized, cannot re-initialize*/ + kStatus_DSPI_DMAChannelInvalid, /*!< DSPI driver could not request DMA channel(s) */ + kStatus_DSPI_Error, /*!< DSPI driver error */ + kStatus_DSPI_EdmaStcdUnaligned32Error /*!< DSPI Edma driver STCD unaligned to 32byte error */ +} dspi_status_t; + +/*! @brief DSPI master or slave configuration*/ +typedef enum _dspi_master_slave_mode { + kDspiMaster = 1, /*!< DSPI peripheral operates in master mode*/ + kDspiSlave = 0 /*!< DSPI peripheral operates in slave mode*/ +} dspi_master_slave_mode_t; + +/*! @brief DSPI clock polarity configuration for a given CTAR*/ +typedef enum _dspi_clock_polarity { + kDspiClockPolarity_ActiveHigh = 0, /*!< Active-high DSPI clock (idles low)*/ + kDspiClockPolarity_ActiveLow = 1 /*!< Active-low DSPI clock (idles high)*/ +} dspi_clock_polarity_t; + +/*! @brief DSPI clock phase configuration for a given CTAR*/ +typedef enum _dspi_clock_phase { + kDspiClockPhase_FirstEdge = 0, /*!< Data is captured on the leading edge of the SCK and + changed on the following edge.*/ + kDspiClockPhase_SecondEdge = 1 /*!< Data is changed on the leading edge of the SCK and + captured on the following edge.*/ +} dspi_clock_phase_t; + +/*! @brief DSPI data shifter direction options for a given CTAR*/ +typedef enum _dspi_shift_direction { + kDspiMsbFirst = 0, /*!< Data transfers start with most significant bit.*/ + kDspiLsbFirst = 1 /*!< Data transfers start with least significant bit.*/ +} dspi_shift_direction_t; + +/*! @brief DSPI Clock and Transfer Attributes Register (CTAR) selection*/ +typedef enum _dspi_ctar_selection { + kDspiCtar0 = 0, /*!< CTAR0 selection option for master or slave mode @internal gui name="CTAR0" */ + kDspiCtar1 = 1 /*!< CTAR1 selection option for master mode only @internal gui name="CTAR1" */ +} dspi_ctar_selection_t; + +/*! @brief DSPI Peripheral Chip Select (PCS) Polarity configuration.*/ +typedef enum _dspi_pcs_polarity_config { + kDspiPcs_ActiveHigh = 0, /*!< PCS Active High (idles low) @internal gui name="Active high" */ + kDspiPcs_ActiveLow = 1 /*!< PCS Active Low (idles high) @internal gui name="Active low" */ +} dspi_pcs_polarity_config_t; + +/*! @brief DSPI Peripheral Chip Select (PCS) configuration (which PCS to configure)*/ +typedef enum _dspi_which_pcs_config { + kDspiPcs0 = 1 << 0, /*!< PCS[0] @internal gui name="PCS0" */ + kDspiPcs1 = 1 << 1, /*!< PCS[1] @internal gui name="PCS1" */ + kDspiPcs2 = 1 << 2, /*!< PCS[2] @internal gui name="PCS2" */ + kDspiPcs3 = 1 << 3, /*!< PCS[3] @internal gui name="PCS3" */ + kDspiPcs4 = 1 << 4, /*!< PCS[4] @internal gui name="PCS4" */ + kDspiPcs5 = 1 << 5 /*!< PCS[5] @internal gui name="PCS5" */ +} dspi_which_pcs_config_t; + +/*! + * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in Modified Transfer + * Format. This field is valid only when CPHA bit in CTAR register is 0. + */ +typedef enum _dspi_master_sample_point { + kDspiSckToSin_0Clock = 0, /*!< 0 system clocks between SCK edge and SIN sample*/ + kDspiSckToSin_1Clock = 1, /*!< 1 system clock between SCK edge and SIN sample*/ + kDspiSckToSin_2Clock = 2 /*!< 2 system clocks between SCK edge and SIN sample*/ +} dspi_master_sample_point_t; + +/*! @brief DSPI Tx FIFO Fill and Rx FIFO Drain DMA or Interrupt configuration */ +typedef enum _dspi_dma_or_int_mode { + kDspiGenerateIntReq = 0, /*!< Desired flag generates an Interrupt request */ + kDspiGenerateDmaReq = 1 /*!< Desired flag generates a DMA request */ +} dspi_dma_or_int_mode_t; + +/*! @brief DSPI status flags and interrupt request enable*/ +typedef enum _dspi_status_and_interrupt_request { + kDspiTxComplete = SPI_RSER_TCF_RE_SHIFT, /*!< TCF status/interrupt enable */ + kDspiTxAndRxStatus = SPI_SR_TXRXS_SHIFT, /*!< TXRXS status only, no interrupt*/ + kDspiEndOfQueue = SPI_RSER_EOQF_RE_SHIFT, /*!< EOQF status/interrupt enable*/ + kDspiTxFifoUnderflow = SPI_RSER_TFUF_RE_SHIFT, /*!< TFUF status/interrupt enable*/ + kDspiTxFifoFillRequest = SPI_RSER_TFFF_RE_SHIFT, /*!< TFFF status/interrupt enable*/ + kDspiRxFifoOverflow = SPI_RSER_RFOF_RE_SHIFT, /*!< RFOF status/interrupt enable*/ + kDspiRxFifoDrainRequest = SPI_RSER_RFDF_RE_SHIFT /*!< RFDF status/interrupt enable*/ +} dspi_status_and_interrupt_request_t; + +/*! @brief DSPI delay type selection*/ +typedef enum _dspi_delay_type { + kDspiPcsToSck = 1, /*!< PCS-to-SCK delay */ + kDspiLastSckToPcs = 2, /*!< Last SCK edge to PCS delay */ + kDspiAfterTransfer = 3, /*!< Delay between transfers */ +} dspi_delay_type_t; + +/*! + * @brief DSPI data format settings configuration structure + * + * This structure contains the data format settings. These settings apply to a specific + * CTARn register, which the user must provide in this structure. + */ +typedef struct DspiDataFormatConfig { + uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16 */ + dspi_clock_polarity_t clkPolarity; /*!< Active high or low clock polarity*/ + dspi_clock_phase_t clkPhase; /*!< Clock phase setting to change and capture data*/ + dspi_shift_direction_t direction; /*!< MSB or LSB data shift direction + This setting relevant only in master mode and + can be ignored in slave mode */ +} dspi_data_format_config_t; + +/*! + * @brief DSPI baud rate divisors settings configuration structure. + * + * Note: These settings are relevant only in master mode. + * This structure contains the baud rate divisor settings, which provides the user with the option + * to explicitly set these baud rate divisors. In addition, the user must also set the + * CTARn register with the divisor settings. + */ +typedef struct DspiBaudRateDivisors { + bool doubleBaudRate; /*!< Double Baud rate parameter setting */ + uint32_t prescaleDivisor; /*!< Baud Rate Pre-scalar parameter setting*/ + uint32_t baudRateDivisor; /*!< Baud Rate scaler parameter setting */ +} dspi_baud_rate_divisors_t; + +/*! + * @brief DSPI command and data configuration structure + * + * Note: This structure is used with the PUSHR register, which + * provides the means to write to the Tx FIFO. Data written to this register is + * transferred to the Tx FIFO. Eight or sixteen-bit write accesses to the PUSHR transfer all + * 32 register bits to the Tx FIFO. The register structure is different in master and slave + * modes. In master mode, the register provides 16-bit command and 16-bit data to the Tx + * FIFO. In slave mode only 16-bit data may be written (this may be contrary to some + * older documentation which erroneously states that a 32-bit value may be written). + */ +typedef struct DspiCommandDataConfig { + bool isChipSelectContinuous; /*!< Option to enable the continuous assertion of chip select + between transfers*/ + dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes + Register (CTAR) to use for CTAS*/ + dspi_which_pcs_config_t whichPcs; /*!< The desired PCS signal to use for the data transfer*/ + bool isEndOfQueue; /*!< Signals that the current transfer is the last in the queue*/ + bool clearTransferCount; /*!< Clears SPI_TCNT field; cleared before transmission starts*/ +} dspi_command_config_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Configuration + * @{ + */ + +/*! + * @brief Restores the DSPI to reset the configuration. + * + * This function basically resets all of the DSPI registers to their default setting including + * disabling the module. + * + * @param base Module base pointer of type SPI_Type. + */ +void DSPI_HAL_Init(SPI_Type * base); + +/*! + * @brief Enables the DSPI peripheral and sets the MCR MDIS to 0. + * + * @param base Module base pointer of type SPI_Type. + */ +static inline void DSPI_HAL_Enable(SPI_Type * base) +{ + SPI_BWR_MCR_MDIS(base, 0); +} + +/*! + * @brief Disables the DSPI peripheral, sets MCR MDIS to 1. + * + * @param base Module base pointer of type SPI_Type. + */ +static inline void DSPI_HAL_Disable(SPI_Type * base) +{ + SPI_BWR_MCR_MDIS(base, 1); +} + +/*! + * @brief Sets the DSPI baud rate in bits per second. + * + * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest + * possible baud rate without exceeding the desired baud rate, and returns the calculated + * baud rate in bits-per-second. It requires that the caller also provide the frequency of the + * module source clock (in Hertz). + * + * @param base Module base pointer of type SPI_Type. + * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of the type + * dspi_ctar_selection_t + * @param bitsPerSec The desired baud rate in bits per second + * @param sourceClockInHz Module source input clock in Hertz + * @return The actual calculated baud rate + */ +uint32_t DSPI_HAL_SetBaudRate(SPI_Type * base, dspi_ctar_selection_t whichCtar, + uint32_t bitsPerSec, uint32_t sourceClockInHz); + +/*! + * @brief Configures the baud rate divisors manually. + * + * This function allows the caller to manually set the baud rate divisors in the event that + * these dividers are known and the caller does not wish to call the DSPI_HAL_SetBaudRate function. + * + * @param base Module base pointer of type SPI_Type. + * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type + * dspi_ctar_selection_t + * @param divisors Pointer to a structure containing the user defined baud rate divisor settings + */ +void DSPI_HAL_SetBaudDivisors(SPI_Type * base, + dspi_ctar_selection_t whichCtar, + const dspi_baud_rate_divisors_t * divisors); + +/*! + * @brief Configures the DSPI for master or slave. + * + * @param base Module base pointer of type SPI_Type. + * @param mode Mode setting (master or slave) of type dspi_master_slave_mode_t + */ +static inline void DSPI_HAL_SetMasterSlaveMode(SPI_Type * base, dspi_master_slave_mode_t mode) +{ + SPI_BWR_MCR_MSTR(base, (uint32_t)mode); +} + +/*! + * @brief Returns whether the DSPI module is in master mode. + * + * @param base Module base pointer of type SPI_Type. + * @return Returns true if the module is in master mode or false if the module is in slave mode. + */ +static inline bool DSPI_HAL_IsMaster(SPI_Type * base) +{ + return (bool)SPI_RD_MCR_MSTR(base); +} + +/*! + * @brief Configures the DSPI for the continuous SCK operation. + * + * @param base Module base pointer of type SPI_Type. + * @param enable Enables (true) or disables(false) continuous SCK operation. + */ +static inline void DSPI_HAL_SetContinuousSckCmd(SPI_Type * base, bool enable) +{ + SPI_BWR_MCR_CONT_SCKE(base, (enable == true)); +} + +#if FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE +/*! + * @brief Configures the DSPI peripheral chip select strobe enable. Configures the PCS[5] to be the + * active-low PCS Strobe output. + * + * PCS[5] is a special case that can be configured as an active low PCS strobe or as a Peripheral + * Chip Select in master mode. When configured as a strobe, it provides a signal to an external + * demultiplexer to decode PCS[0] to PCS[4] signals into as many as 128 glitch-free PCS signals. + * + * @param base Module base pointer of type SPI_Type. + * @param enable Enable (true) PCS[5] to operate as the peripheral chip select (PCS) strobe + * If disable (false), PCS[5] operates as a peripheral chip select + */ +static inline void DSPI_HAL_SetPcsStrobeCmd(SPI_Type * base, bool enable) +{ + SPI_BWR_MCR_PCSSE(base, (enable == true)); +} +#endif + +/*! + * @brief Configures the DSPI received FIFO overflow overwrite enable. + * + * When enabled, this function allows incoming receive data to overwrite the existing data in the + * receive shift register when the Rx FIFO is full. Otherwise when disabled, the incoming data + * is ignored when the RX FIFO is full. + * + * @param base Module base pointer of type SPI_Type. + * @param enable If enabled (true), allows incoming data to overwrite Rx FIFO contents when full, + * else incoming data is ignored. + */ +static inline void DSPI_HAL_SetRxFifoOverwriteCmd(SPI_Type * base, bool enable) +{ + SPI_BWR_MCR_ROOE(base, (enable == true)); +} + +/*! + * @brief Configures the DSPI peripheral chip select polarity. + * + * This function takes in the desired peripheral chip select (PCS) and it's + * corresponding desired polarity and configures the PCS signal to operate with the + * desired characteristic. + * + * @param base Module base pointer of type SPI_Type. + * @param pcs The particular peripheral chip select (parameter value is of type + * dspi_which_pcs_config_t) for which we wish to apply the active high or active + * low characteristic. + * @param activeLowOrHigh The setting for either "active high, inactive low (0)" or + * "active low, inactive high(1)" of type dspi_pcs_polarity_config_t. + */ +void DSPI_HAL_SetPcsPolarityMode(SPI_Type * base, dspi_which_pcs_config_t pcs, + dspi_pcs_polarity_config_t activeLowOrHigh); + +/*! + * @brief Enables (or disables) the DSPI FIFOs. + * + * This function allows the caller to disable/enable the Tx and Rx FIFOs (independently). + * Note that to disable, the caller must pass in a logic 0 (false) for the particular FIFO + * configuration. To enable, the caller must pass in a logic 1 (true). + * + * @param base Module base pointer of type SPI_Type. + * @param enableTxFifo Disables (false) the TX FIFO, else enables (true) the TX FIFO + * @param enableRxFifo Disables (false) the RX FIFO, else enables (true) the RX FIFO + */ +void DSPI_HAL_SetFifoCmd(SPI_Type * base, bool enableTxFifo, bool enableRxFifo); + +/*! + * @brief Flushes the DSPI FIFOs. + * + * @param base Module base pointer of type SPI_Type. + * @param enableFlushTxFifo Flushes (true) the Tx FIFO, else do not flush (false) the Tx FIFO + * @param enableFlushRxFifo Flushes (true) the Rx FIFO, else do not flush (false) the Rx FIFO + */ +void DSPI_HAL_SetFlushFifoCmd(SPI_Type * base, bool enableFlushTxFifo, bool enableFlushRxFifo); + + +/*! + * @brief Configures the time when the DSPI master samples SIN in the Modified Transfer Format. + * + * This function controls when the DSPI master samples SIN (data in) in the Modified Transfer + * Format. Note that this is valid only when the CPHA bit in the CTAR register is 0. + * + * @param base Module base pointer of type SPI_Type. + * @param samplePnt selects when the data in (SIN) is sampled, of type dspi_master_sample_point_t. + * This value selects either 0, 1, or 2 system clocks between the SCK edge + * and the SIN (data in) sample. + */ +static inline void DSPI_HAL_SetDatainSamplepointMode(SPI_Type * base, + dspi_master_sample_point_t samplePnt) +{ + SPI_BWR_MCR_SMPL_PT(base, samplePnt); +} + +/*! + * @brief Starts the DSPI transfers, clears HALT bit in MCR. + * + * This function call called whenever the module is ready to begin data transfers in either master + * or slave mode. + * + * @param base Module base pointer of type SPI_Type. + */ +static inline void DSPI_HAL_StartTransfer(SPI_Type * base) +{ + SPI_BWR_MCR_HALT(base, 0); +} + +/*! + * @brief Stops (halts) DSPI transfers, sets HALT bit in MCR. + * + * This function call stops data transfers in either master or slave mode. + * + * @param base Module base pointer of type SPI_Type. + */ +static inline void DSPI_HAL_StopTransfer(SPI_Type * base) +{ + SPI_BWR_MCR_HALT(base, 1); +} + +/*! + * @brief Configures the data format for a particular CTAR. + * + * This function configures the bits-per-frame, polarity, phase, and shift direction for a + * particular CTAR. An example use case is as follows: + @code + dspi_data_format_config_t dataFormat; + dataFormat.bitsPerFrame = 16; + dataFormat.clkPolarity = kDspiClockPolarity_ActiveLow; + dataFormat.clkPhase = kDspiClockPhase_FirstEdge; + dataFormat.direction = kDspiMsbFirst; + DSPI_HAL_SetDataFormat(instance, kDspiCtar0, &dataFormat); + @endcode + * + * @param base Module base pointer of type SPI_Type. + * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type + * dspi_ctar_selection_t. + * @param config Pointer to structure containing user defined data format configuration settings. + * @return An error code or kStatus_DSPI_Success + */ +dspi_status_t DSPI_HAL_SetDataFormat(SPI_Type * base, + dspi_ctar_selection_t whichCtar, + const dspi_data_format_config_t * config); + +/*! + * @brief Manually configures the delay prescaler and scaler for a particular CTAR. + * + * This function configures the PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), + * after SCK delay pre-scalar (PASC) and scalar (ASC), and the delay + * after transfer pre-scalar (PDT)and scalar (DT). + * + * These delay names are available in type dspi_delay_type_t. + * + * The user passes which delay they want to configure along with the prescaler and scaler value. + * This allows the user to directly set the prescaler/scaler values if they have + * pre-calculated them or if they simply wish to manually increment either value. + * + * @param base Module base pointer of type SPI_Type. + * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type + * dspi_ctar_selection_t. + * @param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3). + * @param scaler The scaler delay value (can be any integer between 0 to 15). + * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t + */ +void DSPI_HAL_SetDelay(SPI_Type * base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, + uint32_t scaler, dspi_delay_type_t whichDelay); + +/*! + * @brief Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds. + * + * This function calculates the values for: + * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or + * After SCK delay pre-scalar (PASC) and scalar (ASC), or + * Delay after transfer pre-scalar (PDT)and scalar (DT). + * + * These delay names are available in type dspi_delay_type_t. + * + * The user passes which delay they want to configure along with the desired delay value in + * nanoseconds. The function calculates the values needed for the prescaler and scaler and + * returning the actual calculated delay as an exact delay match may not be possible. In this + * case, the closest match is calculated without going below the desired delay value input. + * It is possible to input a very large delay value that exceeds the capability of the part, in + * which case the maximum supported delay is returned. It is to the higher level + * peripheral driver to alert the user of an out of range delay input. + * + * @param base Module base pointer of type SPI_Type. + * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type + * dspi_ctar_selection_t. + * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t + * @param sourceClockInHz Module source input clock in Hertz + * @param delayInNanoSec The desired delay value in nanoseconds. + * @return The actual calculated delay value. + */ +uint32_t DSPI_HAL_CalculateDelay(SPI_Type * base, dspi_ctar_selection_t whichCtar, + dspi_delay_type_t whichDelay, uint32_t sourceClockInHz, + uint32_t delayInNanoSec); + +/*! + * @brief Gets the DSPI master PUSHR data register address for DMA operation. + * + * This function gets the DSPI master PUSHR data register address as this value is needed for + * DMA operation. + * + * @param base Module base pointer of type SPI_Type. + * @return The DSPI master PUSHR data register address. + */ +static inline uint32_t DSPI_HAL_GetMasterPushrRegAddr(SPI_Type * base) +{ + return (uint32_t)(&SPI_PUSHR_REG(base)); +} + +/*! + * @brief Gets the DSPI slave PUSHR data register address for DMA operation. + * + * This function gets the DSPI slave PUSHR data register address as this value is needed for + * DMA operation. + * + * @param base Module base pointer of type SPI_Type. + * @return The DSPI slave PUSHR data register address. + */ +static inline uint32_t DSPI_HAL_GetSlavePushrRegAddr(SPI_Type * base) +{ + return (uint32_t)(&SPI_PUSHR_SLAVE_REG(base)); +} + +/*! + * @brief Gets the DSPI POPR data register address for DMA operation. + * + * This function gets the DSPI POPR data register address as this value is needed for + * DMA operation. + * + * @param base Module base pointer of type SPI_Type. + * @return The DSPI POPR data register address. + */ +static inline uint32_t DSPI_HAL_GetPoprRegAddr(SPI_Type * base) +{ + return (uint32_t)(&SPI_POPR_REG(base)); +} +/*@}*/ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Configures the DSPI Tx FIFO fill request to generate DMA or interrupt requests. + * + * This function configures the DSPI Tx FIFO Fill flag to generate either + * an interrupt or DMA request. The user passes in which request they'd like to generate + * of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request. + * Note, when disabling the request, the request type is don't care. + @code + DSPI_HAL_SetTxFifoFillDmaIntMode(base, kDspiGenerateDmaReq, true); <- to enable DMA + DSPI_HAL_SetTxFifoFillDmaIntMode(base, kDspiGenerateIntReq, true); <- to enable Interrupt + DSPI_HAL_SetTxFifoFillDmaIntMode(base, kDspiGenerateIntReq, false); <- to disable + @endcode + * @param base Module base pointer of type SPI_Type. + * @param mode Configures the DSPI Tx FIFO Fill to generate an interrupt or DMA request + * @param enable Enable (true) or disable (false) the DSPI Tx FIFO Fill flag to generate requests + */ +void DSPI_HAL_SetTxFifoFillDmaIntMode(SPI_Type * base, dspi_dma_or_int_mode_t mode, bool enable); + +/*! + * @brief Configures the DSPI Rx FIFO Drain request to generate DMA or interrupt requests. + * + * This function configures the DSPI Rx FIFO Drain flag to generate either + * an interrupt or a DMA request. The user passes in which request they'd like to generate + * of type dspi_dma_or_int_mode_t and whether or not they wish to enable this request. + * Note, when disabling the request, the request type is don't care. + @code + DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateDmaReq, true); <- to enable DMA + DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateIntReq, true); <- to enable Interrupt + DSPI_HAL_SetRxFifoDrainDmaIntMode(base, kDspiGenerateIntReq, false); <- to disable + @endcode + * @param base Module base pointer of type SPI_Type. + * @param mode Configures the Rx FIFO Drain to generate an interrupt or DMA request + * @param enable Enable (true) or disable (false) the Rx FIFO Drain flag to generate requests + */ +void DSPI_HAL_SetRxFifoDrainDmaIntMode(SPI_Type * base, dspi_dma_or_int_mode_t mode, bool enable); + +/*! + * @brief Configures the DSPI interrupts. + * + * This function configures the various interrupt sources of the DSPI. The parameters are + * base, interrupt source, and enable/disable setting. + * The interrupt source is a typedef enumeration whose value is the bit position of the + * interrupt source setting within the RSER register. In the DSPI, all interrupt + * configuration settings are in one register. The typedef enum equates each + * interrupt source to the bit position defined in the device header file. + * The function uses these bit positions in its algorithm to enable/disable the + * interrupt source, where interrupt source is the dspi_status_and_interrupt_request_t type. + * Note, for Tx FIFO Fill and Rx FIFO Drain requests, use the functions: + * DSPI_HAL_SetTxFifoFillDmaIntMode and DSPI_HAL_SetRxFifoDrainDmaIntMode respectively as + * these requests can generate either an interrupt or DMA request. + @code + DSPI_HAL_SetIntMode(base, kDspiTxComplete, true); <- example use-case + @endcode + * + * @param base Module base pointer of type SPI_Type. + * @param interruptSrc The interrupt source, of type dspi_status_and_interrupt_request_t + * @param enable Enable (true) or disable (false) the interrupt source to generate requests + */ +void DSPI_HAL_SetIntMode(SPI_Type * base, + dspi_status_and_interrupt_request_t interruptSrc, + bool enable); + +/*! + * @brief Gets DSPI interrupt configuration, returns if interrupt request is enabled or disabled. + * + * This function returns the requested interrupt source setting (enabled or disabled, of + * type bool). The parameters to pass in are base and interrupt source. It utilizes the + * same enumeration definitions for the interrupt sources as described in the interrupt config + * function. The function uses these bit positions in its algorithm to obtain the desired + * interrupt source setting. + * Note, for Tx FIFO Fill and Rx FIFO Drain requests, this returns whether or not their + * requests are enabled. + @code + getInterruptSetting = DSPI_HAL_GetIntMode(base, kDspiTxComplete); + @endcode + * + * @param base Module base pointer of type SPI_Type. + * @param interruptSrc The interrupt source, of type dspi_status_and_interrupt_request_t + * @return Configuration of interrupt request: enable (true) or disable (false). + */ +static inline bool DSPI_HAL_GetIntMode(SPI_Type * base, + dspi_status_and_interrupt_request_t interruptSrc) +{ + return ((SPI_RD_RSER(base) >> interruptSrc) & 0x1); +} + +/*@}*/ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the DSPI status flag state. + * + * The status flag is defined in the same enumeration as the interrupt source enable because the bit + * position of the interrupt source and corresponding status flag are the same in the RSER and + * SR registers. The function uses these bit positions in its algorithm to obtain the desired + * flag state, similar to the dspi_get_interrupt_config function. + @code + getStatus = DSPI_HAL_GetStatusFlag(base, kDspiTxComplete); + @endcode + * + * @param base Module base pointer of type SPI_Type. + * @param statusFlag The status flag, of type dspi_status_and_interrupt_request_t + * @return State of the status flag: asserted (true) or not-asserted (false) + */ +static inline bool DSPI_HAL_GetStatusFlag(SPI_Type * base, + dspi_status_and_interrupt_request_t statusFlag) +{ + return ((SPI_RD_SR(base) >> statusFlag) & 0x1); +} + +/*! + * @brief Clears the DSPI status flag. + * + * This function clears the desired status bit by using a write-1-to-clear. The user passes in + * the base and the desired status bit to clear. The list of status bits is defined in the + * dspi_status_and_interrupt_request_t. The function uses these bit positions in its algorithm + * to clear the desired flag state. Example usage: + @code + DSPI_HAL_ClearStatusFlag(base, kDspiTxComplete); + @endcode + * + * @param base Module base pointer of type SPI_Type. + * @param statusFlag The status flag, of type dspi_status_and_interrupt_request_t + */ +static inline void DSPI_HAL_ClearStatusFlag(SPI_Type * base, + dspi_status_and_interrupt_request_t statusFlag) +{ + SPI_WR_SR(base, (0x1U << statusFlag)); +} + +/*@}*/ + +/*! + * @name Data transfer + * @{ + */ + +/*! + * @brief Reads data from the data buffer. + * + * @param base Module base pointer of type SPI_Type. + * @return The data from the read data buffer + */ +static inline uint32_t DSPI_HAL_ReadData(SPI_Type * base) +{ + return SPI_RD_POPR(base); +} + +/*! + * @brief Writes data into the data buffer, slave mode. + * + * In slave mode, up to 16-bit words may be written. + * + * @param base Module base pointer of type SPI_Type. + * @param data The data to send + */ +static inline void DSPI_HAL_WriteDataSlavemode(SPI_Type * base, uint32_t data) +{ + SPI_WR_PUSHR_SLAVE(base, data); +} + +/*! + * @brief Writes data into the data buffer, slave mode and waits till data was transmitted and + * return. + * + * In slave mode, up to 16-bit words may be written. The function first clears transmit complete + * flag then writes data into data register, and finally wait tills the data is transmitted. + * + * @param base Module base pointer of type SPI_Type. + * @param data The data to send + */ +void DSPI_HAL_WriteDataSlavemodeBlocking(SPI_Type * base, uint32_t data); + +/*! + * @brief Writes data into the data buffer, master mode. + * + * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion + * provides characteristics of the data such as: optional continuous chip select + * operation between transfers, the desired Clock and Transfer Attributes register to use for the + * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current + * transfer is the last in the queue, and whether to clear the transfer count (normally needed when + * sending the first frame of a data packet). This is an example: + @code + dspi_command_config_t commandConfig; + commandConfig.isChipSelectContinuous = true; + commandConfig.whichCtar = kDspiCtar0; + commandConfig.whichPcs = kDspiPcs1; + commandConfig.clearTransferCount = false; + commandConfig.isEndOfQueue = false; + DSPI_HAL_WriteDataMastermode(base, &commandConfig, dataWord); + @endcode + * + * @param base Module base pointer of type SPI_Type. + * @param command Pointer to command structure + * @param data The data word to be sent + */ +void DSPI_HAL_WriteDataMastermode(SPI_Type * base, + dspi_command_config_t * command, + uint16_t data); + +/*! + * @brief Writes data into the data buffer, master mode and waits till complete to return. + * + * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion + * provides characteristics of the data such as: optional continuous chip select + * operation between transfers, the desired Clock and Transfer Attributes register to use for the + * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current + * transfer is the last in the queue, and whether to clear the transfer count (normally needed when + * sending the first frame of a data packet). This is an example: + @code + dspi_command_config_t commandConfig; + commandConfig.isChipSelectContinuous = true; + commandConfig.whichCtar = kDspiCtar0; + commandConfig.whichPcs = kDspiPcs1; + commandConfig.clearTransferCount = false; + commandConfig.isEndOfQueue = false; + DSPI_HAL_WriteDataMastermodeBlocking(base, &commandConfig, dataWord); + @endcode + * + * Note that this function does not return until after the transmit is complete. Also note that + * the DSPI must be enabled and running in order to transmit data (MCR[MDIS] & [HALT] = 0). + * Since the SPI is a synchronous protocol, receive data is available when transmit completes. + * + * @param base Module base pointer of type SPI_Type. + * @param command Pointer to command structure + * @param data The data word to be sent + */ +void DSPI_HAL_WriteDataMastermodeBlocking(SPI_Type * base, + dspi_command_config_t * command, + uint16_t data); + +/*! + * @brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data + * buffer, master mode. + * + * In this function, the user must append the 16-bit data to the 16-bit command info then + * provide the total 32-bit word as the data to send. + * The command portion provides characteristics of the data such as: optional continuous chip select + * operation between transfers, the desired Clock and Transfer Attributes register to use for the + * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current + * transfer is the last in the queue, and whether to clear the transfer count (normally needed when + * sending the first frame of a data packet). The user is responsible for appending this command + * with the data to send. This is an example: + @code + dataWord = <16-bit command> | <16-bit data>; + DSPI_HAL_WriteCmdDataMastermode(base, dataWord); + @endcode + * + * @param base Module base pointer of type SPI_Type. + * @param data The data word (command and data combined) to be sent + */ +static inline void DSPI_HAL_WriteCmdDataMastermode(SPI_Type * base, uint32_t data) +{ + SPI_WR_PUSHR(base, data); +} + +/*! + * @brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data + * buffer, master mode and waits till complete to return. + * + * In this function, the user must append the 16-bit data to the 16-bit command info then + * provide the total 32-bit word as the data to send. + * The command portion provides characteristics of the data such as: optional continuous chip select + * operation between transfers, the desired Clock and Transfer Attributes register to use for the + * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current + * transfer is the last in the queue, and whether to clear the transfer count (normally needed when + * sending the first frame of a data packet). The user is responsible for appending this command + * with the data to send. This is an example: + @code + dataWord = <16-bit command> | <16-bit data>; + DSPI_HAL_WriteCmdDataMastermodeBlocking(base, dataWord); + @endcode + * + * Note that this function does not return until after the transmit is complete. Also note that + * the DSPI must be enabled and running in order to transmit data (MCR[MDIS] & [HALT] = 0). + * Since the SPI is a synchronous protocol, receive data is available when transmit completes. + * + * @param base Module base pointer of type SPI_Type. + * @param data The data word (command and data combined) to be sent + */ +void DSPI_HAL_WriteCmdDataMastermodeBlocking(SPI_Type * base, uint32_t data); + +/*! + * @brief Gets the transfer count. + * + * This function returns the current value of the DSPI Transfer Count Register. + * + * @param base Module base pointer of type SPI_Type. + * @return The current transfer count + */ +static inline uint32_t DSPI_HAL_GetTransferCount(SPI_Type * base) +{ + return SPI_RD_TCR_SPI_TCNT(base); +} + +/*! + * @brief Pre-sets the transfer count. + * + * This function allows the caller to pre-set the DSI Transfer Count Register to a desired value up + * to 65535; Incrementing past this resets the counter back to 0. + * + * @param base Module base pointer of type SPI_Type. + * @param presetValue The desired pre-set value for the transfer counter + */ +static inline void DSPI_HAL_PresetTransferCount(SPI_Type * base, uint16_t presetValue) +{ + SPI_BWR_TCR_SPI_TCNT(base, presetValue); +} + +/*! + * @brief Returns the DSPI command word formatted to the PUSHR data register bit field. + * + * This function allows the caller to pass in the data command structure and returns the command + * word formatted according to the DSPI PUSHR register bit field placement. The user can then + * "OR" the returned command word with the desired data to send and use the function + * DSPI_HAL_WriteCmdDataMastermode or DSPI_HAL_WriteCmdDataMastermodeBlocking to write the + * entire 32-bit command data word to the PUSHR. + * This helps improve performance in cases where the command structure is constant. + * For example, the user calls this function before starting a transfer to generate the + * command word. When they are ready to transmit the data, they would OR this formatted command + * word with the desired data to transmit. + * This process increases transmit performance when compared to calling send functions such as + * DSPI_HAL_WriteDataMastermode which format the command word each time a data word is + * to be sent. + * + * @param base Module base pointer of type SPI_Type. + * @param command Pointer to command structure + * @return The command word formatted to the PUSHR data register bit field + */ +uint32_t DSPI_HAL_GetFormattedCommand(SPI_Type * base, dspi_command_config_t * command); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_FEATURE_SOC_DSPI_COUNT */ +#endif /* __FSL_DSPI_HAL_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_edma_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_edma_hal.h new file mode 100755 index 0000000..d29ca9d --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_edma_hal.h @@ -0,0 +1,1319 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __EDMA_HAL_H__ +#define __EDMA_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> +#include <assert.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_EDMA_COUNT + +/*! + * @addtogroup edma_hal + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Error code for the eDMA Driver. */ +typedef enum _edma_status { + kStatus_EDMA_Success = 0U, + kStatus_EDMA_InvalidArgument = 1U, /*!< Parameter is invalid. */ + kStatus_EDMA_Fail = 2U /*!< Failed operation. */ +} edma_status_t; + +/*! @brief eDMA channel arbitration algorithm used for selection among channels. */ +typedef enum _edma_channel_arbitration { + kEDMAChnArbitrationFixedPriority = 0U, /*!< Fixed Priority arbitration is used for selection + among channels. @internal gui name="Fixed priority" */ + kEDMAChnArbitrationRoundrobin /*!< Round-Robin arbitration is used for selection among + channels. @internal gui name="Round-Robin" */ +} edma_channel_arbitration_t; + +/*! @brief eDMA channel priority setting */ +typedef enum _edma_chn_priority { + kEDMAChnPriority0 = 0U, + kEDMAChnPriority1, + kEDMAChnPriority2, + kEDMAChnPriority3, + kEDMAChnPriority4, + kEDMAChnPriority5, + kEDMAChnPriority6, + kEDMAChnPriority7, + kEDMAChnPriority8, + kEDMAChnPriority9, + kEDMAChnPriority10, + kEDMAChnPriority11, + kEDMAChnPriority12, + kEDMAChnPriority13, + kEDMAChnPriority14, + kEDMAChnPriority15 +} edma_channel_priority_t; + +#if (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 0x1U) +/*! @brief eDMA group arbitration algorithm used for selection among channels. */ +typedef enum _edma_group_arbitration +{ + kEDMAGroupArbitrationFixedPriority = 0U, /*!< Fixed Priority arbitration is used for + selection among eDMA groups. @internal gui name="Fixed priority" */ + kEDMAGroupArbitrationRoundrobin /*!< Round-Robin arbitration is used for selection + among eDMA channels. @internal gui name="Round-Robin" */ +} edma_group_arbitration_t; + +/*! @brief eDMA group priority setting */ +typedef enum _edma_group_priority { + kEDMAGroup0PriorityLowGroup1PriorityHigh, /*!< eDMA group 0's priority is lower priority. + eDMA group 1's priority is higher priority. @internal gui name="Group 1 high priority" */ + kEDMAGroup0PriorityHighGroup1PriorityLow /*!< eDMA group 0's priority is higher priority. + eDMA group 1's priority is lower priority. @internal gui name="Group 0 high priority" */ +} edma_group_priority_t; +#endif + +/*! @brief eDMA modulo configuration */ +typedef enum _edma_modulo { + kEDMAModuloDisable = 0U, + kEDMAModulo2bytes, + kEDMAModulo4bytes, + kEDMAModulo8bytes, + kEDMAModulo16bytes, + kEDMAModulo32bytes, + kEDMAModulo64bytes, + kEDMAModulo128bytes, + kEDMAModulo256bytes, + kEDMAModulo512bytes, + kEDMAModulo1Kbytes, + kEDMAModulo2Kbytes, + kEDMAModulo4Kbytes, + kEDMAModulo8Kbytes, + kEDMAModulo16Kbytes, + kEDMAModulo32Kbytes, + kEDMAModulo64Kbytes, + kEDMAModulo128Kbytes, + kEDMAModulo256Kbytes, + kEDMAModulo512Kbytes, + kEDMAModulo1Mbytes, + kEDMAModulo2Mbytes, + kEDMAModulo4Mbytes, + kEDMAModulo8Mbytes, + kEDMAModulo16Mbytes, + kEDMAModulo32Mbytes, + kEDMAModulo64Mbytes, + kEDMAModulo128Mbytes, + kEDMAModulo256Mbytes, + kEDMAModulo512Mbytes, + kEDMAModulo1Gbytes, + kEDMAModulo2Gbytes +} edma_modulo_t; + +/*! @brief eDMA transfer configuration */ +typedef enum _edma_transfer_size { + kEDMATransferSize_1Bytes = 0x0U, + kEDMATransferSize_2Bytes = 0x1U, + kEDMATransferSize_4Bytes = 0x2U, + kEDMATransferSize_16Bytes = 0x4U, + kEDMATransferSize_32Bytes = 0x5U +} edma_transfer_size_t; + +/*! + * @brief eDMA transfer size configuration. + * + * This structure configures the basic source/destination transfer attribute. + * This figure shows the eDMA's transfer model:\n + * _________________________________________________ \n + * | Transfer Size | | \n + * Minor Loop |_______________| Major loop Count 1 | \n + * Count | Transfer Size | | \n + * ____________|_______________|____________________|--> Minor loop complete \n + * ____________________________________ \n + * | | | \n + * |_______________| Major Loop Count 2 | \n + * | | | \n + * |_______________|____________________|--> Minor loop Complete \n + * + * ---------------------------------------------------------> Major loop complete \n + * + */ +typedef struct EDMATransferConfig { + uint32_t srcAddr; /*!< Memory address pointing to the source data. */ + uint32_t destAddr; /*!< Memory address pointing to the destination data. */ + edma_transfer_size_t srcTransferSize; /*!< Source data transfer size. */ + edma_transfer_size_t destTransferSize; /*!< Destination data transfer size. */ + int16_t srcOffset; /*!< Sign-extended offset applied to the current source address to + form the next-state value as each source read/write is + completed. */ + int16_t destOffset; + uint32_t srcLastAddrAdjust; /*!< Last source address adjustment. */ + uint32_t destLastAddrAdjust; /*!< Last destination address adjustment. Note here it is only + valid when scatter/gather feature is not enabled. */ + edma_modulo_t srcModulo; /*!< Source address modulo. */ + edma_modulo_t destModulo; /*!< Destination address modulo. */ + uint32_t minorLoopCount; /*!< Minor bytes transfer count. Number of bytes to be transferred + in each service request of the channel. */ + uint16_t majorLoopCount; /*!< Major iteration count. */ +} edma_transfer_config_t; + +/*! @brief eDMA channel configuration. */ +typedef enum _edma_channel_indicator { + kEDMAChannel0 = 0U, /*!< Channel 0. */ + kEDMAChannel1 = 1U, + kEDMAChannel2 = 2U, + kEDMAChannel3 = 3U, +#if (FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U) + kEDMAChannel4 = 4U, + kEDMAChannel5 = 5U, + kEDMAChannel6 = 6U, + kEDMAChannel7 = 7U, + kEDMAChannel8 = 8U, + kEDMAChannel9 = 9U, + kEDMAChannel10 = 10U, + kEDMAChannel11 = 11U, + kEDMAChannel12 = 12U, + kEDMAChannel13 = 13U, + kEDMAChannel14 = 14U, + kEDMAChannel15 = 15U, +#endif +#if (FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U) + kEDMAChannel16 = 16U, + kEDMAChannel17 = 17U, + kEDMAChannel18 = 18U, + kEDMAChannel19 = 19U, + kEDMAChannel20 = 20U, + kEDMAChannel21 = 21U, + kEDMAChannel22 = 22U, + kEDMAChannel23 = 23U, + kEDMAChannel24 = 24U, + kEDMAChannel25 = 25U, + kEDMAChannel26 = 26U, + kEDMAChannel27 = 27U, + kEDMAChannel28 = 28U, + kEDMAChannel29 = 29U, + kEDMAChannel30 = 30U, + kEDMAChannel31 = 31U, +#endif + kEDMAAllChannel = 64U +} edma_channel_indicator_t; + +/*! @brief eDMA TCD Minor loop mapping configuration */ +typedef struct EDMAMinorLoopOffsetConfig { + bool enableSrcMinorloop; /*!< Enable(true) or Disable(false) source minor loop offset. */ + bool enableDestMinorloop; /*!< Enable(true) or Disable(false) destination minor loop offset. */ + uint32_t offset; /*!< Offset for minor loop mapping. */ +} edma_minorloop_offset_config_t; + +/*! @brief Error status of the eDMA module */ +typedef struct EDMAErrorStatusAll { + uint8_t errorChannel; /*!< Error channel number of the cancelled channel number */ + bool destinationBusError; /*!< Bus error on destination address */ + bool sourceBusError; /*!< Bus error on the SRC address */ + bool scatterOrGatherConfigurationError; /*!< Error on the Scatter/Gather address */ + bool nbyteOrCiterConfigurationError; /*!< NBYTES/CITER configuration error */ + bool destinationOffsetError; /*!< Destination offset error */ + bool destinationAddressError; /*!< Destination address error */ + bool sourceOffsetError; /*!< Source offset error */ + bool sourceAddressError; /*!< Source address error */ + + bool channelPriorityError; /*!< Channel priority error */ +#if FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1 + bool groupPriorityError; /*!< Group priority error */ +#endif + bool transferCancelledError; /*!< Transfer cancelled */ + bool orOfAllError; /*!< Logical OR all ERR status bits */ +} edma_error_status_all_t; + +/*! @brief Bandwidth control configuration */ +typedef enum _edma_bandwidth_config { + kEDMABandwidthStallNone = 0U, /*!< No eDMA engine stalls. */ + kEDMABandwidthStall4Cycle = 2U, /*!< eDMA engine stalls for 4 cycles after each read/write. */ + kEDMABandwidthStall8Cycle = 3U /*!< eDMA engine stalls for 8 cycles after each read/write. */ +} edma_bandwidth_config_t; + +/*! @brief eDMA TCD */ +typedef struct EDMASoftwareTcd { + uint32_t SADDR; + uint16_t SOFF; + uint16_t ATTR; + uint32_t NBYTES; + uint32_t SLAST; + uint32_t DADDR; + uint16_t DOFF; + uint16_t CITER; + uint32_t DLAST_SGA; + uint16_t CSR; + uint16_t BITER; +} edma_software_tcd_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA HAL driver module level operation + * @{ + */ + +/*! + * @brief Initializes eDMA module to known state. + * + * @param base Register base address for eDMA module. + */ +void EDMA_HAL_Init(DMA_Type * base); + +/*! + * @brief Cancels the remaining data transfer. + * + * This function stops the executing channel and forces the minor loop + * to finish. The cancellation takes effect after the last write of the + * current read/write sequence. The CX clears itself after the cancel has + * been honored. This cancel retires the channel normally as if the minor + * loop had completed. + * + * @param base Register base address for eDMA module. + */ +void EDMA_HAL_CancelTransfer(DMA_Type * base); + +/*! + * @brief Cancels the remaining data transfer and treats it as an error condition. + * + * This function stops the executing channel and forces the minor loop + * to finish. The cancellation takes effect after the last write of the + * current read/write sequence. The CX clears itself after the cancel has + * been honored. This cancel retires the channel normally as if the minor + * loop had completed. Additional thing is to treat this operation as an error + * condition. + * + * @param base Register base address for eDMA module. + */ +void EDMA_HAL_ErrorCancelTransfer(DMA_Type * base); + +/*! + * @brief Halts/Un-halts the DMA Operations. + * + * This function stalls/un-stalls the start of any new channels. Executing channels are allowed + * to be completed. + * + * @param base Register base address for eDMA module. + * @param halt Halts (true) or un-halts (false) eDMA transfer. + */ +static inline void EDMA_HAL_SetHaltCmd(DMA_Type * base, bool halt) +{ + DMA_BWR_CR_HALT(base, halt); +} + +/*! + * @brief Halts or does not halt the eDMA module when an error occurs. + * + * An error causes the HALT bit to be set. Subsequently, all service requests are ignored until the + * HALT bit is cleared. + * + * @param base Register base address for eDMA module. + * @param haltOnError Halts (true) or not halt (false) eDMA module when an error occurs. + */ +static inline void EDMA_HAL_SetHaltOnErrorCmd(DMA_Type * base, bool haltOnError) +{ + DMA_BWR_CR_HOE(base, haltOnError); +} + +/*! + * @brief Enables/Disables the eDMA DEBUG mode. + * + * This function enables/disables the eDMA Debug mode. + * When in debug mode, the DMA stalls the start of a new + * channel. Executing channels are allowed to complete. Channel execution resumes + * either when the system exits debug mode or when the EDBG bit is cleared. + * + * @param base Register base address for eDMA module. + * @param enable Enables (true) or Disable (false) eDMA module debug mode. + */ +static inline void EDMA_HAL_SetDebugCmd(DMA_Type * base, bool enable) +{ + DMA_BWR_CR_EDBG(base, enable); +} +/* @} */ + +/*! + * @name eDMA HAL driver channel priority and arbitration configuration. + * @{ + */ +/*! + * @brief Sets the preempt and preemption feature for the eDMA channel. + * + * This function sets the preempt and preemption features. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @param preempt eDMA channel can't suspend a lower priority channel (true). eDMA channel can + * suspend a lower priority channel (false). + * @param preemption eDMA channel can be temporarily suspended by the service request of a higher + * priority channel (true). eDMA channel can't be suspended by a higher priority channel (false). + */ +static inline void EDMA_HAL_SetChannelPreemptMode( + DMA_Type * base, uint32_t channel, bool preempt, bool preemption) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + DMA_BWR_DCHPRIn_DPA(base, channel, preempt); + DMA_BWR_DCHPRIn_ECP(base, channel, preemption); +} + +/*! + * @brief Sets the eDMA channel priority. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @param priority Priority of the DMA channel. Different channels should have different priority + * setting inside a group. + */ +static inline void EDMA_HAL_SetChannelPriority( + DMA_Type * base, uint32_t channel, edma_channel_priority_t priority) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + DMA_BWR_DCHPRIn_CHPRI(base, channel, priority); +} +/*! + * @brief Sets the channel arbitration algorithm. + * + * @param base Register base address for eDMA module. + * @param channelArbitration Round-Robin way for fixed priority way. + */ +static inline void EDMA_HAL_SetChannelArbitrationMode( + DMA_Type * base, edma_channel_arbitration_t channelArbitration) +{ + DMA_BWR_CR_ERCA(base, channelArbitration); +} + +#if (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 0x1U) +/*! + * @brief Configures the group priority. + * + * This function configures the priority for group 0 and group 1. + * + * @param base Register base address for eDMA module. + * @param groupPriority Group priority configuration. Note that each group get its own + * group priority. + */ +void EDMA_HAL_SetGroupPriority(DMA_Type * base, edma_group_priority_t groupPriority); + +/*! + * @brief Sets the eDMA group arbitration algorithm. + * + * @param base Register base address for eDMA module. + * @param groupArbitration Group arbitration way. Fixed-Priority way or Round-Robin way. + */ +static inline void EDMA_HAL_SetGroupArbitrationMode( + DMA_Type * base, edma_group_arbitration_t groupArbitration) +{ + DMA_BWR_CR_ERGA(base, groupArbitration); +} +#endif +/* @} */ + +/*! + * @name eDMA HAL driver configuration and operation. + * @{ + */ +/*! + * @brief Enables/Disables the minor loop mapping. + * + * This function enables/disables the minor loop mapping feature. + * If enabled, the NBYTES is redefined to include the individual enable fields and the NBYTES field. The + * individual enable fields allow the minor loop offset to be applied to the source address, the + * destination address, or both. The NBYTES field is reduced when either offset is enabled. + * + * @param base Register base address for eDMA module. + * @param enable Enables (true) or Disable (false) minor loop mapping. + */ +static inline void EDMA_HAL_SetMinorLoopMappingCmd(DMA_Type * base, bool enable) +{ + DMA_BWR_CR_EMLM(base, enable); +} + +/*! + * @brief Enables or disables the continuous transfer mode. + * + * This function enables or disables the continuous transfer. If set, a minor loop channel link + * does not go through the channel arbitration before being activated again. Upon minor loop + * completion, the channel activates again if that channel has a minor loop channel link enabled and + * the link channel is itself. + * + * @param base Register base address for eDMA module. + * @param continuous Enables (true) or Disable (false) continuous transfer mode. + */ +static inline void EDMA_HAL_SetContinuousLinkCmd(DMA_Type * base, bool continuous) +{ + DMA_BWR_CR_CLM(base, continuous); +} + +/*! + * @brief Gets the error status of the eDMA module. + * + * @param base Register base address for eDMA module. + * @return Detailed information of the error type in the eDMA module. + */ +edma_error_status_all_t EDMA_HAL_GetErrorStatus(DMA_Type * base); + +/*! + * @brief Enables/Disables the error interrupt for channels. + * + * @param base Register base address for eDMA module. + * @param enable Enable(true) or Disable (false) error interrupt. + * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels' error interrupt + * will be enabled/disabled. + */ +void EDMA_HAL_SetErrorIntCmd(DMA_Type * base, bool enable, edma_channel_indicator_t channel); + +/*! + * @brief Gets the eDMA error interrupt status. + * + * @param base Register base address for eDMA module. + * @return 32 bit variable indicating error channels. If error happens on eDMA channel n, the bit n + * of this variable is '1'. If not, the bit n of this variable is '0'. + */ +static inline uint32_t EDMA_HAL_GetErrorIntStatusFlag(DMA_Type * base) +{ + return DMA_RD_ERR(base); +} + +/*! + * @brief Clears the error interrupt status for the eDMA channel or channels. + * + * @param base Register base address for eDMA module. + * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels' error interrupt + * status will be cleared. + */ +static inline void EDMA_HAL_ClearErrorIntStatusFlag( + DMA_Type * base, edma_channel_indicator_t channel) +{ + DMA_WR_CERR(base, channel); +} + +/*! + * @brief Enables/Disables the DMA request for the channel or all channels. + * + * @param base Register base address for eDMA module. + * @param enable Enable(true) or Disable (false) DMA request. + * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels DMA request + * are enabled/disabled. + */ +void EDMA_HAL_SetDmaRequestCmd(DMA_Type * base, edma_channel_indicator_t channel,bool enable); + +/*! + * @brief Gets the eDMA channel DMA request status. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @return Hardware request is triggered in this eDMA channel (true) or not be triggered in this + * channel (false). + */ +static inline bool EDMA_HAL_GetDmaRequestStatusFlag(DMA_Type * base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + return (((uint32_t)DMA_RD_HRS(base) >> channel) & 1U); +} + +/*! + * @brief Clears the done status for a channel or all channels. + * + * @param base Register base address for eDMA module. + * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels' done status will + * be cleared. + */ +static inline void EDMA_HAL_ClearDoneStatusFlag(DMA_Type * base, edma_channel_indicator_t channel) +{ + DMA_WR_CDNE(base, channel); +} + +/*! + * @brief Triggers the eDMA channel. + * + * @param base Register base address for eDMA module. + * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels are tirggere. + */ +static inline void EDMA_HAL_TriggerChannelStart(DMA_Type * base, edma_channel_indicator_t channel) +{ + DMA_WR_SSRT(base, channel); +} + +/*! + * @brief Gets the eDMA channel interrupt request status. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @return Interrupt request happens in this eDMA channel (true) or not happen in this + * channel (false). + */ +static inline bool EDMA_HAL_GetIntStatusFlag(DMA_Type * base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + + return (((uint32_t)DMA_RD_INT(base) >> channel) & 1U); +} + +/*! + * @brief Clears the interrupt status for the eDMA channel or all channels. + * + * @param base Register base address for eDMA module. + * @param channel Channel indicator. If kEDMAAllChannel is selected, all channels' interrupt + * status will be cleared. + */ +static inline void EDMA_HAL_ClearIntStatusFlag( + DMA_Type * base, edma_channel_indicator_t channel) +{ + DMA_WR_CINT(base, channel); +} + +#if (FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT > 0x0U) +/*! + * @brief Enables/Disables an asynchronous request in stop mode. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @param enable Enable (true) or Disable (false) async DMA request. + */ +void EDMA_HAL_SetAsyncRequestInStopModeCmd(DMA_Type * base, uint32_t channel, bool enable); +#endif + +/* @} */ + +/*! + * @name eDMA HAL driver hardware TCD configuration functions. + * @{ + */ + +/*! + * @brief Clears all registers to 0 for the hardware TCD. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + */ +void EDMA_HAL_HTCDClearReg(DMA_Type * base, uint32_t channel); + +/*! + * @brief Configures the source address for the hardware TCD. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @param address The pointer to the source memory address. + */ +static inline void EDMA_HAL_HTCDSetSrcAddr(DMA_Type * base, uint32_t channel, uint32_t address) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + DMA_WR_SADDR(base, channel, address); +} + +/*! + * @brief Configures the source address signed offset for the hardware TCD. + * + * Sign-extended offset applied to the current source address to form the next-state value as each + * source read is complete. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @param offset signed-offset for source address. + */ +static inline void EDMA_HAL_HTCDSetSrcOffset(DMA_Type * base, uint32_t channel, int16_t offset) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + DMA_WR_SOFF(base, channel, offset); +} + +/*! + * @brief Configures the transfer attribute for the eDMA channel. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @param srcModulo enumeration type for an allowed source modulo. The value defines a specific address range + * specified as the value after the SADDR + SOFF calculation is performed on the original register + * value. Setting this field provides the ability to implement a circular data. For data queues + * requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD + * field should be set to the appropriate value for the queue, freezing the desired number of upper + * address bits. The value programmed into this field specifies the number of the lower address bits + * allowed to change. For a circular queue application, the SOFF is typically set to the transfer + * size to implement post-increment addressing with SMOD function restricting the addresses to a + * 0-modulo-size range. + * @param destModulo Enum type for an allowed destination modulo. + * @param srcTransferSize Enum type for source transfer size. + * @param destTransferSize Enum type for destination transfer size. + */ +void EDMA_HAL_HTCDSetAttribute( + DMA_Type * base, uint32_t channel, + edma_modulo_t srcModulo, edma_modulo_t destModulo, + edma_transfer_size_t srcTransferSize, edma_transfer_size_t destTransferSize); + +/*! + * @brief Configures the nbytes for the eDMA channel. + * + * Note here that user need firstly configure the minor loop mapping feature and then call this + * function. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @param nbytes Number of bytes to be transferred in each service request of the channel + */ +void EDMA_HAL_HTCDSetNbytes(DMA_Type * base, uint32_t channel, uint32_t nbytes); + +/*! + * @brief Gets the nbytes configuration data for the hardware TCD. + * + * This function decides whether the minor loop mapping is enabled or whether the source/dest + * minor loop mapping is enabled. Then, the nbytes are returned accordingly. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @return nbytes configuration according to minor loop setting. + */ +uint32_t EDMA_HAL_HTCDGetNbytes(DMA_Type * base, uint32_t channel); + +/*! + * @brief Configures the minor loop offset for the hardware TCD. + * + * Configures both the enable bits and the offset value. If neither source nor destination offset is enabled, + * offset is not configured. Note here if source or destination offset is required, the eDMA module + * EMLM bit will be set in this function. User need to know this side effect. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @param config Configuration data structure for the minor loop offset + */ +void EDMA_HAL_HTCDSetMinorLoopOffset( + DMA_Type * base, uint32_t channel, edma_minorloop_offset_config_t *config); + +/*! + * @brief Configures the last source address adjustment for the hardware TCD. + * + * Adjustment value added to the source address at the completion of the major iteration count. This + * value can be applied to restore the source address to the initial value, or adjust the address to + * reference the next data structure. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @param size adjustment value + */ +static inline void EDMA_HAL_HTCDSetSrcLastAdjust(DMA_Type * base, uint32_t channel, int32_t size) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + DMA_WR_SLAST(base, channel, size); +} + +/*! + * @brief Configures the destination address for the hardware TCD. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @param address The pointer to the destination address. + */ +static inline void EDMA_HAL_HTCDSetDestAddr(DMA_Type * base, uint32_t channel, uint32_t address) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + DMA_WR_DADDR(base, channel, address); +} + +/*! + * @brief Configures the destination address signed offset for the hardware TCD. + * + * Sign-extended offset applied to the current source address to form the next-state value as each + * destination write is complete. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @param offset signed-offset + */ +static inline void EDMA_HAL_HTCDSetDestOffset(DMA_Type * base, uint32_t channel, int16_t offset) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + DMA_WR_DOFF(base, channel, offset); +} + +/*! + * @brief Configures the last source address adjustment. + * + * This function adds an adjustment value added to the source address at the completion of the major + * iteration count. This value can be applied to restore the source address to the initial value, or + * adjust the address to reference the next data structure. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @param adjust adjustment value + */ +static inline void EDMA_HAL_HTCDSetDestLastAdjust( + DMA_Type * base, uint32_t channel, uint32_t adjust) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + DMA_WR_DLAST_SGA(base, channel, adjust); +} + +/*! + * @brief Configures the memory address for the next transfer TCD for the hardware TCD. + * + * + * This function enables the scatter/gather feature for the hardware TCD and configures the next + * TCD's address. This address points to the beginning of a 0-modulo-32 byte region containing + * the next transfer TCD to be loaded into this channel. The channel reload is performed as the + * major iteration count completes. The scatter/gather address must be 0-modulo-32-byte. Otherwise, + * a configuration error is reported. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @param stcd The pointer to the TCD to be linked to this hardware TCD. + */ +void EDMA_HAL_HTCDSetScatterGatherLink( + DMA_Type * base, uint32_t channel, edma_software_tcd_t *stcd); + +/*! + * @brief Configures the bandwidth for the hardware TCD. + * + * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the + * minor loop, it continuously generates read/write sequences until the minor count is exhausted. + * This field forces the eDMA to stall after the completion of each read/write access to control the + * bus request bandwidth seen by the crossbar switch. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @param bandwidth enum type for bandwidth control + */ +static inline void EDMA_HAL_HTCDSetBandwidth( + DMA_Type * base, uint32_t channel, edma_bandwidth_config_t bandwidth) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + DMA_BWR_CSR_BWC(base, channel, bandwidth); +} + +/*! + * @brief Configures the major channel link the hardware TCD. + * + * If the major link is enabled, after the major loop counter is exhausted, the eDMA engine initiates a + * channel service request at the channel defined by these six bits by setting that channel start + * bits. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @param majorChannel channel number for major link + * @param enable Enables (true) or Disables (false) channel major link. + */ +static inline void EDMA_HAL_HTCDSetChannelMajorLink( + DMA_Type * base, uint32_t channel, uint32_t majorChannel, bool enable) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + DMA_BWR_CSR_MAJORLINKCH(base, channel, majorChannel); + DMA_BWR_CSR_MAJORELINK(base, channel, enable); +} + +/*! + * @brief Enables/Disables the scatter/gather feature for the hardware TCD. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @param enable Enables (true) /Disables (false) scatter/gather feature. + */ +static inline void EDMA_HAL_HTCDSetScatterGatherCmd( + DMA_Type * base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + DMA_BWR_CSR_ESG(base, channel, enable); +} + +/*! + * @brief Disables/Enables the DMA request after the major loop completes for the hardware TCD. + * + * If disabled, the eDMA hardware automatically clears the corresponding DMA request when the + * current major iteration count reaches zero. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @param disable Disable (true)/Enable (true) DMA request after TCD complete. + */ +static inline void EDMA_HAL_HTCDSetDisableDmaRequestAfterTCDDoneCmd( + DMA_Type * base, uint32_t channel, bool disable) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + DMA_BWR_CSR_DREQ(base, channel, disable); +} + +/*! + * @brief Enables/Disables the half complete interrupt for the hardware TCD. + * + * If set, the channel generates an interrupt request by setting the appropriate bit in the + * interrupt register when the current major iteration count reaches the halfway point. Specifically, + * the comparison performed by the eDMA engine is (CITER == (BITER >> 1)). This half-way point + * interrupt request is provided to support the double-buffered schemes or other types of data movement + * where the processor needs an early indication of the transfer's process. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @param enable Enable (true) /Disable (false) half complete interrupt. + */ +static inline void EDMA_HAL_HTCDSetHalfCompleteIntCmd( + DMA_Type * base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + DMA_BWR_CSR_INTHALF(base, channel, enable); +} + +/*! + * @brief Enables/Disables the interrupt after the major loop completes for the hardware TCD. + * + * If enabled, the channel generates an interrupt request by setting the appropriate bit in the + * interrupt register when the current major iteration count reaches zero. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @param enable Enable (true) /Disable (false) interrupt after TCD done. + */ +static inline void EDMA_HAL_HTCDSetIntCmd( + DMA_Type * base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + DMA_BWR_CSR_INTMAJOR(base, channel, enable); +} + +/*! + * @brief Triggers the start bits for the hardware TCD. + * + * The eDMA hardware automatically clears this flag after the channel begins execution. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + */ +static inline void EDMA_HAL_HTCDTriggerChannelStart(DMA_Type * base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + DMA_BWR_CSR_START(base, channel, true); +} + +/*! + * @brief Checks whether the channel is running for the hardware TCD. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @return True stands for running. False stands for not. + */ +static inline bool EDMA_HAL_HTCDGetChannelActiveStatus(DMA_Type * base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL); + return DMA_BRD_CSR_ACTIVE(base, channel); +} + +/*! + * @brief Sets the channel minor link for the hardware TCD. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @param linkChannel Channel to be linked on minor loop complete. + * @param enable Enable (true)/Disable (false) channel minor link. + */ +void EDMA_HAL_HTCDSetChannelMinorLink( + DMA_Type * base, uint32_t channel, uint32_t linkChannel, bool enable); + +/*! + * @brief Sets the major iteration count according to minor loop channel link setting. + * + * Note here that user need to first set the minor loop channel link and then call this function. + * The execute flow inside this function is dependent on the minor loop channel link setting. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @param count major loop count + */ +void EDMA_HAL_HTCDSetMajorCount(DMA_Type * base, uint32_t channel, uint32_t count); + +/*! + * @brief Gets the number of bytes already transferred for the hardware TCD. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @return data bytes already transferred + */ +uint32_t EDMA_HAL_HTCDGetFinishedBytes(DMA_Type * base, uint32_t channel); + +/*! + * @brief Gets the number of bytes haven't transferred for the hardware TCD. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @return data bytes already transferred + */ +uint32_t EDMA_HAL_HTCDGetUnfinishedBytes(DMA_Type * base, uint32_t channel); + +/*! + * @brief Gets the channel done status. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @return If channel done. + */ +static inline bool EDMA_HAL_HTCDGetDoneStatusFlag(DMA_Type * base, uint32_t channel) +{ + return DMA_BRD_CSR_DONE(base,channel); +} + +/* @} */ + +/*! + * @name EDMA HAL driver software TCD configuration functions. + * @{ + */ +/*! + * @brief Configures the source address for the software TCD. + * + * @param stcd The pointer to the software TCD. + * @param address The source memory address. + */ +static inline void EDMA_HAL_STCDSetSrcAddr(edma_software_tcd_t *stcd, uint32_t address) +{ + assert(stcd); + stcd->SADDR = DMA_SADDR_SADDR(address); +} + +/*! + * @brief Configures the source address signed offset for the software TCD. + * + * Sign-extended offset applied to the current source address to form the next-state value as each + * source read is complete. + * + * @param stcd The pointer to the software TCD. + * @param offset signed-offset for source address. + */ +static inline void EDMA_HAL_STCDSetSrcOffset(edma_software_tcd_t *stcd, int16_t offset) +{ + assert(stcd); + stcd->SOFF = DMA_SOFF_SOFF(offset); +} + +/*! + * @brief Configures the transfer attribute for software TCD. + * + * @param stcd The pointer to the software TCD. + * @param srcModulo enum type for an allowed source modulo. The value defines a specific address range + * specified as the value after the SADDR + SOFF calculation is performed on the original register + * value. Setting this field provides the ability to implement a circular data. For data queues + * requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the SMOD + * field should be set to the appropriate value for the queue, freezing the desired number of upper + * address bits. The value programmed into this field specifies the number of the lower address bits + * allowed to change. For a circular queue application, the SOFF is typically set to the transfer + * size to implement post-increment addressing with SMOD function restricting the addresses to a + * 0-modulo-size range. + * @param destModulo Enum type for an allowed destination modulo. + * @param srcTransferSize Enum type for source transfer size. + * @param destTransferSize Enum type for destinatio transfer size. + */ +void EDMA_HAL_STCDSetAttribute( + edma_software_tcd_t *stcd, + edma_modulo_t srcModulo, edma_modulo_t destModulo, + edma_transfer_size_t srcTransferSize, edma_transfer_size_t destTransferSize); + +/*! + * @brief Configures the nbytes for software TCD. + * + * Note here that user need firstly configure the minor loop mapping feature and then call this + * function. + * + * @param base Register base address for eDMA module. + * @param stcd The pointer to the software TCD. + * @param nbytes Number of bytes to be transferred in each service request of the channel + */ +void EDMA_HAL_STCDSetNbytes(DMA_Type * base, edma_software_tcd_t *stcd, uint32_t nbytes); + +/*! + * @brief Configures the minorloop offset for the software TCD. + * + * Configures both the enable bits and the offset value. If neither source nor dest offset is enabled, + * offset is not configured. Note here if source or destination offset is requred, the eDMA module + * EMLM bit will be set in this function. User need to know this side effect. + * + * @param base Register base address for eDMA module. + * @param stcd The pointer to the software TCD. + * @param config Configuration data structure for the minorloop offset + */ +void EDMA_HAL_STCDSetMinorLoopOffset( + DMA_Type * base, edma_software_tcd_t *stcd, edma_minorloop_offset_config_t *config); + +/*! + * @brief Configures the last source address adjustment for the software TCD. + * + * Adjustment value added to the source address at the completion of the major iteration count. This + * value can be applied to restore the source address to the initial value, or adjust the address to + * reference the next data structure. + * + * @param stcd The pointer to the software TCD. + * @param size adjustment value + */ +static inline void EDMA_HAL_STCDSetSrcLastAdjust(edma_software_tcd_t *stcd, int32_t size) +{ + assert(stcd); + stcd->SLAST = (stcd->SLAST & ~DMA_SLAST_SLAST_MASK) | DMA_SLAST_SLAST(size); +} + +/*! + * @brief Configures the destination address for the software TCD. + * + * @param stcd The pointer to the software TCD. + * @param address The pointer to the destination addresss. + */ +static inline void EDMA_HAL_STCDSetDestAddr(edma_software_tcd_t *stcd, uint32_t address) +{ + assert(stcd); + stcd->DADDR = DMA_DADDR_DADDR(address); +} + +/*! + * @brief Configures the destination address signed offset for the software TCD. + * + * Sign-extended offset applied to the current source address to form the next-state value as each + * destination write is complete. + * + * @param stcd The pointer to the software TCD. + * @param offset signed-offset + */ +static inline void EDMA_HAL_STCDSetDestOffset(edma_software_tcd_t *stcd, int16_t offset) +{ + assert(stcd); + stcd->DOFF = DMA_DOFF_DOFF(offset); +} + +/*! + * @brief Configures the last source address adjustment. + * + * This function add an adjustment value added to the source address at the completion of the major + * iteration count. This value can be applied to restore the source address to the initial value, or + * adjust the address to reference the next data structure. + * + * @param stcd The pointer to the software TCD. + * @param adjust adjustment value + */ +static inline void EDMA_HAL_STCDSetDestLastAdjust( + edma_software_tcd_t *stcd, uint32_t adjust) +{ + assert(stcd); + stcd->DLAST_SGA = DMA_DLAST_SGA_DLASTSGA(adjust); +} + +/*! + * @brief Configures the memory address for the next transfer TCD for the software TCD. + * + * + * This function enable the scatter/gather feature for the software TCD and configure the next + * TCD's address.This address points to the beginning of a 0-modulo-32 byte region containing + * the next transfer TCD to be loaded into this channel. The channel reload is performed as the + * major iteration count completes. The scatter/gather address must be 0-modulo-32-byte. Otherwise, + * a configuration error is reported. + * + * @param stcd The pointer to the software TCD. + * @param nextStcd The pointer to the TCD to be linked to this software TCD. + */ +void EDMA_HAL_STCDSetScatterGatherLink( + edma_software_tcd_t *stcd, edma_software_tcd_t *nextStcd); + +/*! + * @brief Configures the bandwidth for the software TCD. + * + * Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the + * minor loop, it continuously generates read/write sequences until the minor count is exhausted. + * This field forces the eDMA to stall after the completion of each read/write access to control the + * bus request bandwidth seen by the crossbar switch. + * + * @param stcd The pointer to the software TCD. + * @param bandwidth enum type for bandwidth control + */ +static inline void EDMA_HAL_STCDSetBandwidth( + edma_software_tcd_t *stcd, edma_bandwidth_config_t bandwidth) +{ + assert(stcd); + stcd->CSR = (stcd->CSR & ~DMA_CSR_BWC_MASK) | DMA_CSR_BWC(bandwidth); +} + +/*! + * @brief Configures the major channel link the software TCD. + * + * If the majorlink is enabled, after the major loop counter is exhausted, the eDMA engine initiates a + * channel service request at the channel defined by these six bits by setting that channel start + * bits. + * + * @param stcd The pointer to the software TCD. + * @param majorChannel channel number for major link + * @param enable Enables (true) or Disables (false) channel major link. + */ +static inline void EDMA_HAL_STCDSetChannelMajorLink( + edma_software_tcd_t *stcd, uint32_t majorChannel, bool enable) +{ + assert(stcd); + stcd->CSR = (stcd->CSR & ~DMA_CSR_MAJORLINKCH_MASK) | DMA_CSR_MAJORLINKCH(majorChannel); + stcd->CSR = (stcd->CSR & ~DMA_CSR_MAJORELINK_MASK) | + ((uint32_t)enable << DMA_CSR_MAJORELINK_SHIFT); +} + + +/*! + * @brief Enables/Disables the scatter/gather feature for the software TCD. + * + * @param stcd The pointer to the software TCD. + * @param enable Enables (true) /Disables (false) scatter/gather feature. + */ +static inline void EDMA_HAL_STCDSetScatterGatherCmd( + edma_software_tcd_t *stcd, bool enable) +{ + assert(stcd); + stcd->CSR = (stcd->CSR & ~DMA_CSR_ESG_MASK) | ((uint32_t)enable << DMA_CSR_ESG_SHIFT); +} + + +/*! + * @brief Disables/Enables the DMA request after the major loop completes for the software TCD. + * + * If disabled, the eDMA hardware automatically clears the corresponding DMA request when the + * current major iteration count reaches zero. + * + * @param stcd The pointer to the software TCD. + * @param disable Disable (true)/Enable (true) dma request after TCD complete. + */ +static inline void EDMA_HAL_STCDSetDisableDmaRequestAfterTCDDoneCmd( + edma_software_tcd_t *stcd, bool disable) +{ + assert(stcd); + stcd->CSR = (stcd->CSR & ~DMA_CSR_DREQ_MASK) | ((uint32_t)disable << DMA_CSR_DREQ_SHIFT); +} + +/*! + * @brief Enables/Disables the half complete interrupt for the software TCD. + * + * If set, the channel generates an interrupt request by setting the appropriate bit in the + * interrupt register when the current major iteration count reaches the halfway point. Specifically, + * the comparison performed by the eDMA engine is (CITER == (BITER >> 1)). This half-way point + * interrupt request is provided to support the double-buffered schemes or other types of data movement + * where the processor needs an early indication of the transfer's process. + * + * @param stcd The pointer to the software TCD. + * @param enable Enable (true) /Disable (false) half complete interrupt. + */ +static inline void EDMA_HAL_STCDSetHalfCompleteIntCmd( + edma_software_tcd_t *stcd, bool enable) +{ + assert(stcd); + stcd->CSR = (stcd->CSR & ~DMA_CSR_INTHALF_MASK) | ((uint32_t)enable << DMA_CSR_INTHALF_SHIFT); +} + +/*! + * @brief Enables/Disables the interrupt after the major loop completes for the software TCD. + * + * If enabled, the channel generates an interrupt request by setting the appropriate bit in the + * interrupt register when the current major iteration count reaches zero. + * + * @param stcd The pointer to the software TCD. + * @param enable Enable (true) /Disable (false) interrupt after TCD done. + */ +static inline void EDMA_HAL_STCDSetIntCmd(edma_software_tcd_t *stcd, bool enable) +{ + assert(stcd); + stcd->CSR = (stcd->CSR & ~DMA_CSR_INTMAJOR_MASK) | ((uint32_t)enable << DMA_CSR_INTMAJOR_SHIFT); +} + +/*! + * @brief Triggers the start bits for the software TCD. + * + * The eDMA hardware automatically clears this flag after the channel begins execution. + * + * @param stcd The pointer to the software TCD. + */ +static inline void EDMA_HAL_STCDTriggerChannelStart(edma_software_tcd_t *stcd) +{ + assert(stcd); + stcd->CSR |= DMA_CSR_START_MASK; +} + +/*! + * @brief Set Channel minor link for software TCD. + * + * @param stcd The pointer to the software TCD. + * @param linkChannel Channel to be linked on minor loop complete. + * @param enable Enable (true)/Disable (false) channel minor link. + */ +void EDMA_HAL_STCDSetChannelMinorLink( + edma_software_tcd_t *stcd, uint32_t linkChannel, bool enable); + +/*! + * @brief Sets the major iteration count according to minor loop channel link setting. + * + * Note here that user need to first set the minor loop channel link and then call this function. + * The execute flow inside this function is dependent on the minor loop channel link setting. + * + * @param stcd The pointer to the software TCD. + * @param count major loop count + */ +void EDMA_HAL_STCDSetMajorCount(edma_software_tcd_t *stcd, uint32_t count); + +/*! + * @brief Copy the software TCD configuration to the hardware TCD. + * + * @param base Register base address for eDMA module. + * @param channel eDMA channel number. + * @param stcd The pointer to the software TCD. + */ +void EDMA_HAL_PushSTCDToHTCD(DMA_Type * base, uint32_t channel, edma_software_tcd_t *stcd); + +/*! + * @brief Set the basic transfer for software TCD. + * + * This function is used to setup the basic transfer for software TCD. The minor loop setting is not + * involved here cause minor loop's configuration will lay a impact on the global eDMA setting. And + * the source minor loop offset is relevant to the dest minor loop offset. For these reasons, minor + * loop offset configuration is treated as an advanced configuration. User can call the + * EDMA_HAL_STCDSetMinorLoopOffset() to configure the minor loop offset feature. + * + * @param base Register base address for eDMA module. + * @param stcd The pointer to the software TCD. + * @param config The pointer to the transfer configuration structure. + * @param enableInt Enables (true) or Disables (false) interrupt on TCD complete. + * @param disableDmaRequest Disables (true) or Enable (false) dma request on TCD complete. + */ +edma_status_t EDMA_HAL_STCDSetBasicTransfer( + DMA_Type * base, edma_software_tcd_t *stcd, edma_transfer_config_t *config, + bool enableInt, bool disableDmaRequest); + + +/* @} */ + + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif +#endif /* __EDMA_HAL_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ + + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_enc_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_enc_hal.h new file mode 100755 index 0000000..d828afb --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_enc_hal.h @@ -0,0 +1,1406 @@ +/******************************************************************************* +* +* Copyright [2014-]2014 Freescale Semiconductor, Inc. + +* +* This software is owned or controlled by Freescale Semiconductor. +* Use of this software is governed by the Freescale License +* distributed with this Material. +* See the LICENSE file distributed for more details. +* +* +*******************************************************************************/ + +#ifndef __FSL_ENC_HAL_H__ +#define __FSL_ENC_HAL_H__ + +#include <assert.h> +#include <stdint.h> +#include <stdbool.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_ENC_COUNT + +/*! + * @addtogroup enc_hal + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Encoder status */ +typedef enum _enc_status_t { + kStatus_ENC_Success = 0U, /*!< Encoder success status.*/ + kStatus_ENC_Error = 1U, /*!< Encoder error status.*/ + kStatus_ENC_InvalidArgument = 2U /*!< Encoder invalid argument.*/ +} enc_status_t; + +/*! @brief Encoder operation modes*/ +typedef enum _enc_operation_mode_t { + kEncNormalMode = 0U, /*!< Normal mode (transition signal counting).*/ + kEncModuloCountingMode = 1U, /*!< Modulo counting mode.*/ + kEncSignalPhaseCountMode = 2U /*!< Signal phase count mode (pulse counting).*/ +} enc_operation_mode_t; + +/*! @brief Encoder status flags */ +typedef enum _enc_status_flag { + kEncCmpFlag = 0U, /*!< Encoder Compare status flag.*/ + kEncHomeSignalFlag = 1U, /*!< Encoder HOME Signal transition status flag.*/ + kEncWatchdogTimeoutFlag = 2U, /*!< Encoder Watchdog timeout status flag.*/ + kEncIndexPulseFlag = 3U, /*!< Encoder INDEX Pulse transition status flag.*/ + kEncRollunderFlag = 4U, /*!< Encoder Roll-under status flag.*/ + kEncRolloverFlag = 5U, /*!< Encoder Roll-over status flag.*/ + kEncSimultaneousFlag = 6U, /*!< Encoder Simultaneous PHA and PHB change status flag.*/ + kEncCountDirectionFlag = 7U /*!< Encoder Last count direction status flag.*/ +} enc_status_flag_t; + +/*! @brief Encoder interrupts*/ +typedef enum _enc_int_source_t { + kEncIntCmp = 0U, /*!< Compare interrupt source.*/ + kEncIntHomeSignal = 1U, /*!< HOME signal interrupt source.*/ + kEncIntWatchdogTimeout = 2U, /*!< Watchdog timeout interrupt source.*/ + kEncIntIndexPulse = 3U, /*!< INDEX pulse interrupt source.*/ + kEncIntRollunder = 4U, /*!< Roll-under position counter interrupt source.*/ + kEncIntRollover = 5U, /*!< Roll-over position counter interrupt source.*/ + kEncIntSimultaneous = 6U /*!< Simultaneous PHASEA and PHASEB change interrupt source.*/ +} enc_int_source_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Configuration + * @{ + */ + +/*! + * @brief Resets all configurable registers to be in the reset state for ENC. + * + * This function resets all configurable registers to be in the reset state for ENC. + * It should be called before configuring the ENC module. + * + * @param base The ENC peripheral base address. + */ +void ENC_HAL_Init(ENC_Type* base); + +/*! + * @brief Switches to enable the Compare interrupt. + * + * This function allows the user to enable/disable compare interrupt. + * + * @param base The ENC module base address. + * @param enable Bool parameter to enable/disable. + */ +static inline void ENC_HAL_SetCmpIntCmd(ENC_Type* base, bool enable) +{ + ENC_BWR_CTRL_CMPIE(base, (enable ? 1U : 0U)); +} + +/*! + * @brief Gets the Compare Interrupt configuration setting. + * + * This function allows the user to get the compare interrupt + * configuration setting. + * + * @param base The ENC module base address. + * @return The state of compare interrupt setting. + */ +static inline bool ENC_HAL_GetCmpIntCmd(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL_CMPIE(base); +} + +/*! + * @brief Gets the Compare Interrupt Request configuration setting. + * + * This function returns the configuration setting of the compare interrupt + * request. This bit is set when a match occurs between the counter and + * the COMP value. It will remain set until cleared by software. + * + * @param base The ENC module base address. + * @return Bit setting of the compare interrupt request bit. + */ +static inline bool ENC_HAL_GetCmpIntFlag(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL_CMPIRQ(base); +} + +/*! + * @brief Clears the Compare Interrupt Request bit pending. + * + * This function clears the compare interrupt request bit. + * + * @param base The ENC module base address. + */ +static inline void ENC_HAL_ClearCmpIntFlag(ENC_Type* base) +{ + ENC_BWR_CTRL_CMPIRQ(base, 1U); +} + +/*! + * @brief Switches to enable the Watchdog. + * + * This function allows the user to enable watchdog timer. Allow operation + * of the watchdog timer monitoring the PHESEA and PHASEB inputs for motor + * movement. + * + * @param base The ENC module base address. + * @param enable Bool parameter to enable/disable. + */ +static inline void ENC_HAL_SetWatchdogCmd(ENC_Type* base, bool enable) +{ + ENC_BWR_CTRL_WDE(base, (enable ? 1U : 0U)); +} + +/*! + * @brief Gets the Watchdog configuration setting. + * + * This function allows the user to get the watchdog configuration setting. + * + * @param base The ENC module base address. + * @return The state of watchdog. + */ +static inline bool ENC_HAL_GetWatchdogCmd(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL_WDE(base); +} + +/*! + * @brief Switches to enable the Watchdog Timeout Interrupt. + * + * This function allows the user to enable watchdog timeout interrupt. + * + * @param base The ENC module base address. + * @param enable Bool parameter to enable/disable. + */ +static inline void ENC_HAL_SetWatchdogIntCmd(ENC_Type* base, bool enable) +{ + ENC_BWR_CTRL_DIE(base, (enable ? 1U : 0U)); +} + +/*! + * @brief Gets the Watchdog Timeout Interrupt configuration setting. + * + * This function allows the user to get the watchdog timeout interrupt + * configuration setting. + * + * @param base The ENC module base address. + * @return The state of wdt timeout interrupt setting. + */ +static inline bool ENC_HAL_GetWatchdogIntCmd(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL_DIE(base); +} + +/*! + * @brief Gets the Watchdog Timeout Interrupt Request configuration setting. + * + * This function returns the configuration setting of the watchdog timeout + * interrupt request. This bit is set when a watchdog timeout interrupt occurs. + * It will remain set until cleared by software. This bit is also cleared + * when watchdog is disabled. + * + * @param base The ENC module base address. + * @return Bit setting of the wdt timetout interrupt request bit. + */ +static inline bool ENC_HAL_GetWatchdogIntFlag(ENC_Type* base) +{ + return (bool)ENC_BRD_CTRL_DIRQ(base); +} + +/*! + * @brief Clears the Watchdog Timeout Interrupt Request pending. + * + * This function clears the watchdog timeout interrupt request bit. + * + * @param base The ENC module base address. + */ +static inline void ENC_HAL_ClearWatchdogIntFlag(ENC_Type* base) +{ + ENC_BWR_CTRL_DIRQ(base, 1U); +} + +/*! + * @brief Sets the type of INDEX pulse edge. + * + * This function allows the user to set the type of INDEX pulse edge used + * to initialize the position counter. + * + * @param base The ENC module base address. + * @param enable The edge type of INDEX pulse input. + */ +static inline void ENC_HAL_SetIndexPulseNegativeEdgeCmd + (ENC_Type* base, bool enable) +{ + ENC_BWR_CTRL_XNE(base, (enable ? 1U : 0U)); +} + +/*! + * @brief Gets INDEX pulse edge configuration setting. + * + * This function allows the user to get the type of INDEX pulse edge. + * + * @param base The ENC module base address. + * @return The INDEX pulse edge configuration setting + */ +static inline bool ENC_HAL_GetIndexPulseNegativeEdgeCmd(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL_XNE(base); +} + +/*! + * @brief Switches to enable the INDEX to Initialize Position Counters UPOS and LPOS. + * + * This function allows the user to enable INDEX pulse to initialize position + * counters UPOS and LPOS. + * + * @param base The ENC module base address. + * @param enable Bool parameter to enable/disable. + */ +static inline void ENC_HAL_SetIndexInitPosCmd(ENC_Type* base, bool enable) +{ + ENC_BWR_CTRL_XIP(base, (enable ? 1U : 0U)); +} + +/*! + * @brief Gets the INDEX to Initialize Position Counters configuration setting. + * + * This function allows the user to get the INDEX to initialize position + * counters configuration setting. + * + * @param base The ENC module base address. + * @return The state of INDEX init position counters. + */ +static inline bool ENC_HAL_GetIndexInitPosCmd(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL_XIP(base); +} + +/*! + * @brief Switches to enable the INDEX Pulse Interrupt. + * + * This function allows the user to enable the INDEX pulse interrupt. + * + * @param base The ENC module base address. + * @param enable Bool parameter to enable/disable. + */ +static inline void ENC_HAL_SetIndexPulseIntCmd(ENC_Type* base, bool enable) +{ + ENC_BWR_CTRL_XIE(base, (enable ? 1U : 0U)); +} + +/*! + * @brief Gets the INDEX Pulse Interrupt configuration setting. + * + * This function allows the user to get the INDEX pulse interrupt + * configuration setting. + * + * @param base The ENC module base address. + * @return The state of INDEX pulse interrupt setting. + */ +static inline bool ENC_HAL_GetIndexPulseIntCmd(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL_XIE(base); +} + +/*! + * @brief Gets the INDEX Pulse Interrupt Request configuration setting. + * + * This function returns the configuration setting of the INDEX pulse + * interrupt request. This bit is set when an INDEX interrupt occurs. It will + * remain set until cleared by software. + * + * @param base The ENC module base address. + * @return Bit setting of the INDEX pulse interrupt request bit. + */ +static inline bool ENC_HAL_GetIndexPulseIntFlag(ENC_Type* base) +{ + return (bool)ENC_BRD_CTRL_XIRQ(base); +} + +/*! + * @brief Clears the INDEX Pulse Interrupt Request pending. + * + * This function clears the INDEX pulse interrupt request bit. + * + * @param base The ENC module base address. + */ +static inline void ENC_HAL_ClearIndexPulseIntFlag(ENC_Type* base) +{ + ENC_BWR_CTRL_XIRQ(base, 1U); +} + +/*! + * @brief Enables Signal Phase Count Mode. + * + * This function allows the user to enable the signal phase count mode which + * bypasses the quadrature decoder. A positive transition of the PHASEA input + * generates a count signal. The PHASEB input and the REV (direction control bit) + * control the counter direction. + * + * @param base The ENC module base address. + * @param enable Bool parameter to enable/disable. + */ +static inline void ENC_HAL_SetSignalPhaseCountModeCmd(ENC_Type* base, bool enable) +{ + ENC_BWR_CTRL_PH1(base, (enable ? 1U : 0U)); +} + +/*! + * @brief Gets the Signal Phase Count Mode configuration setting. + * + * This function allows the user to get the signal phase counter mode + * configuration setting. + * + * @param base The ENC module base address. + * @return The state of signal phase count mode setting. + */ +static inline bool ENC_HAL_GetSignalPhaseCountModeCmd(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL_PH1(base); +} + +/*! + * @brief Switches to enable the Reverse Direction Counting. + * + * This function allows the user to enable the reverse direction counting. + * It reverses the interpretation of the quadrature signal, + * changing the direction of count. + * + * @param base The ENC module base address. + * @param enable Bool parameter to enable/disable. + */ +static inline void ENC_HAL_SetReverseCountingCmd(ENC_Type* base, bool enable) +{ + ENC_BWR_CTRL_REV(base, (enable ? 1U : 0U)); +} + +/*! + * @brief Gets Direction Counting configuration setting. + * + * This function allows the user to get the counting type + * configuration setting. + * + * @param base The ENC module base address. + * @return The count type configuration setting. + */ +static inline bool ENC_HAL_GetReverseCountingCmd(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL_REV(base); +} + +/*! + * @brief Gets the Last Count Direction Flag. + * + * This function allows the user to get the flag that indicates the direction + * of the last count. Returns true if last count was in the up direction or + * returns false if last count was in the down direction. + * + * @param base The ENC module base address. + * @return The state of count direction. + */ +static inline bool ENC_HAL_GetLastCountDirectionFlag(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL2_DIR(base); +} + +/*! + * @brief Initializes the Position Counter. + * + * This function allows the user to initialize position counters UPOS and LPOS. + * It will transfer the UINIT and LINIT contents to UPOS and LPOS. + * + * @param base The ENC module base address. + */ +static inline void ENC_HAL_InitPosCounter(ENC_Type* base) +{ + ENC_BWR_CTRL_SWIP(base, 1U); +} + +/*! + * @brief Sets the type of HOME Input Signal Edge. + * + * This function allows the user to set the type of HOME input signal edge. + * Use positive or negative going edge-to-trigger initialization of position + * counters UPOS and LPOS. + * + * @param base The ENC module base address. + * @param enable The edge type of HOME input signal. + */ +static inline void ENC_HAL_SetHomeSignalNegativeEdgeCmd + (ENC_Type* base, bool enable) +{ + ENC_BWR_CTRL_HNE(base, (enable ? 1U : 0U)); +} + +/*! + * @brief Gets HOME Input Signal Edge configuration setting. + * + * This function allows the user to get the HOME input signal edge + * configuration setting. + * + * @param base The ENC module base address. + * @return The edge type of HOME input signal. + */ +static inline bool ENC_HAL_GetHomeSignalNegativeEdgeCmd(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL_HNE(base); +} + +/*! + * @brief Switches to enable the Initialize Position Counters UPOS and LPOS. + * + * This function allows the user to enable HOME signal to initialize position + * counters UPOS and LPOS. + * + * @param base The ENC module base address. + * @param enable Bool parameter to enable/disable. + */ +static inline void ENC_HAL_SetHomeInitPosCmd(ENC_Type* base, bool enable) +{ + ENC_BWR_CTRL_HIP(base, (enable ? 1U : 0U)); +} + +/*! + * @brief Gets the HOME to Initialize Position Counters configuration setting. + * + * This function allows the user to get the HOME signal input init + * configuration setting. + * + * @param base The ENC module base address. + * @return The state of HOME signal initialization POS counters. + */ +static inline bool ENC_HAL_GetHomeInitPosCmd(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL_HIP(base); +} + +/*! + * @brief Switches to enable the HOME Signal Interrupt. + * + * This function allows the user to enable the HOME signal interrupt. + * + * @param base The ENC module base address + * @param enable Bool parameter to enable/disable. + */ +static inline void ENC_HAL_SetHomeSignalIntCmd(ENC_Type* base, bool enable) +{ + ENC_BWR_CTRL_HIE(base, (enable ? 1U : 0U)); +} + +/*! + * @brief Gets the HOME Signal Interrupt configuration setting. + * + * This function allows the user to get the HOME signal interrupt + * configuration setting. + * + * @param base The ENC module base address. + * @return The state of HOME signal interrupt setting. + */ +static inline bool ENC_HAL_GetHomeSignalIntCmd(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL_HIE(base); +} + +/*! + * @brief Gets the HOME Signal Interrupt Request configuration setting. + * + * This function returns the configuration setting of the HOME signal + * interrupt request. This bit is set when a transition on the HOME signal + * occurs. It will remain set until it is cleared by software. + * + * @param base The ENC module base address. + * @return Bit setting of the HOME signal interrupt request bit. + */ +static inline bool ENC_HAL_GetHomeSignalIntFlag(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL_HIRQ(base); +} + +/*! + * @brief Clears the HOME Signal Interrupt Request pending. + * + * This function clears the HOME signal interrupt request bit. + * + * @param base The ENC module base address. + */ +static inline void ENC_HAL_ClearHomeSignalIntFlag(ENC_Type* base) +{ + ENC_BWR_CTRL_HIRQ(base, 1U); +} + +/*! + * @brief Sets the Input Filter Sample Count. + * + * This function allows the user to set the input filter sample counts. + * The value represents the number of consecutive samples that must agree + * prior to the input filter accepting an input transition. + * A value of 0x0 represents 3 samples. A value of 0x7 represents 10 samples. + * A value of sampleCount affects the input latency. + * + * @param base The ENC module base address. + * @param sampleCount Value that represents the number of consecutive samples. + */ +static inline void ENC_HAL_SetInputFilterSampleCount + (ENC_Type* base, uint8_t sampleCount) +{ + assert(sampleCount < 0x08); + ENC_BWR_FILT_FILT_CNT(base, sampleCount); +} + +/*! + * @brief Gets the Input Filter Sample Count. + * + * This function allows the user to read the input filter sample counts. + * The value represents the number of consecutive samples that must agree + * prior to the input filter accepting an input transition. + * + * @param base The ENC module base address. + * @return Value that represents the number of consecutive samples. + */ +static inline uint8_t ENC_HAL_GetInputFilterSampleCount(ENC_Type* base) +{ + return (uint8_t)ENC_BRD_FILT_FILT_CNT(base); +} + +/*! + * @brief Sets the Input Filter Sample Period. + * + * This function allows the user to set the input filter sample period. + * This value represents the sampling period of the decoder input signals. Each + * input is sampled multiple times at the rate specified by this field. + * If samplePeriod is 0x00 (default), then the input filter is bypassed. Bypassing + * the digital filter enables the position/position difference counters to operate + * with count rates up to the IPBus frequency. The value of samplePeriod affects + * the input latency. + * + * @param base The ENC module base address. + * @param samplePeriod Value of filter sample period. + */ +void ENC_HAL_SetInputFilterSamplePeriod(ENC_Type* base, uint8_t samplePeriod); + +/*! + * @brief Gets the Input Filter Sample Period. + * + * This function allows the user to read the input filter sample period. + * This value represents the sampling period of the decoder input signals. + * + * @param base The ENC module base address. + * @return Value of filter sample period. + */ +static inline uint8_t ENC_HAL_GetInputFilterSamplePeriod(ENC_Type* base) +{ + return (uint8_t) ENC_BRD_FILT_FILT_PER(base); +} + +/*! + * @brief Sets the Watchdog timeout register. + * + * This function allows the user to set the timeout value for Watchdog timer, + * which is separated from the watchdog timer in the COP module. + * Timeout value is the number of clock cycles plus one that the watchdog timer + * counts before timing out and optionally generating an interrupt. + * + * @param base The ENC module base address. + * @param wdtTimeout Value of watchdog timeout. + */ +static inline void ENC_HAL_SetWatchdogTimeout(ENC_Type* base, uint16_t wdtTimeout) +{ + ENC_WR_WTR(base, wdtTimeout); +} + +/*! + * @brief Gets the Watchdog timeout register. + * + * This function allows the user to read the timeout value for Watchdog timer, + * which is separated from the watchdog timer in the COP module. + * Timeout value is the number of clock cycles plus one that the watchdog timer + * counts before timing out and optionally generating an interrupt. + * + * @param base The ENC module base address. + * @return Value of watchdog timeout. + */ +static inline uint16_t ENC_HAL_GetWatchdogTimeout(ENC_Type* base) +{ + return (uint16_t) ENC_RD_WTR(base); +} + +/*! + * @brief Sets the Position Difference Counter Register. + * + * This function allows the user to write the POSD register. It contains the + * position change in value occuring between each read of the position register. + * The value of the position difference counter register can be used + * to calculate velocity. + * + * @param base The ENC module base address. + * @param diffPosition Value of position difference. + */ +static inline void ENC_HAL_SetPosDiffCounterReg + (ENC_Type* base, uint16_t diffPosition) +{ + ENC_WR_POSD(base, diffPosition); +} + +/*! + * @brief Gets the Position Difference Counter Register. + * + * This function allows the user to read the POSD register. It contains the + * position change in value occurring between each read of the position register. + * The value of the position difference counter register can be used + * to calculate velocity. + * The 16-bit position difference counter computes up or down on every count pulse. + * This counter acts as a differentiator whose count value is proportional + * to the change in position since the last time the position counter was read. + * When the position register, the position difference counter, or the revolution + * counter is read, the position difference counter's contents are copied into + * the position difference hold register (POSDH) and the position difference + * counter is cleared. + * + * @param base The ENC module base address. + * @return Value of position difference hold register. + */ +static inline uint16_t ENC_HAL_GetPosDiffCounterReg + (ENC_Type* base) +{ + return (uint16_t) ENC_RD_POSD(base); +} + +/*! + * @brief Gets the Position Difference Hold Register. + * + * This function allows the user to read the POSD Hold register. Hold register + * contains a snapshot of the value of the position difference register. + * The value of the position difference hold register can be used to calculate + * velocity. + * + * @param base The ENC module base address. + * @return Value of position difference hold register. + */ +static inline uint16_t ENC_HAL_GetPosDiffHoldReg(ENC_Type* base) +{ + return (uint16_t) ENC_RD_POSDH(base); +} + +/*! + * @brief Sets the Revolution Counter Register. + * + * This function allows the user to write the Revolution counter. + * + * @param base The ENC module base address. + * @param revValue Value of revolution. + */ +static inline void ENC_HAL_SetRevolutionCounterReg + (ENC_Type* base, uint16_t revValue) +{ + ENC_WR_REV(base, revValue); +} + +/*! + * @brief Gets the Revolution Counter Register. + * + * This function allows the user to read the Revolution counter. + * + * @param base The ENC module base address. + * @return Value of revolution counter. + */ +static inline uint16_t ENC_HAL_GetRevolutionCounterReg(ENC_Type* base) +{ + return (uint16_t) ENC_RD_REV(base); +} + +/*! + * @brief Gets the Revolution Hold Register. + * + * This function allows the user to read the Revolution Hold register. Contains + * a snapshot of the value of the revolution counter register. + * + * @param base The ENC module base address. + * @return Value of revolution hold register. + */ +static inline uint16_t ENC_HAL_GetRevolutionHoldReg(ENC_Type* base) +{ + return (uint16_t) ENC_RD_REVH(base); +} + +/*! + * @brief Gets the Position Counter Register. + * + * This function allows the user to read the Position counter. + * + * @param base The ENC module base address. + * @return Value of position counter. + */ +uint32_t ENC_HAL_GetPosCounterReg(ENC_Type* base); + +/*! + * @brief Sets the Position Counter Register. + * + * This function allows the user to write the Position counter. + * + * @param base The ENC module base address. + * @param posVal Value of position counter. + */ +void ENC_HAL_SetPosCounterReg(ENC_Type* base, uint32_t posVal); + +/*! + * @brief Gets the Position Hold Register. + * + * This function allows the user to read the Position hold register. Contains + * a snapshot of the position counter register. + * + * @param base The ENC module base address. + * @return Value of position hold register. + */ +uint32_t ENC_HAL_GetPosHoldReg(ENC_Type* base); + +/*! + * @brief Sets the Initialization Register. + * + * This function allows the user to write the initialization register. + * + * @param base The ENC module base address. + * @param initValue Value of initialization register. + */ +void ENC_HAL_SetInitReg(ENC_Type* base, uint32_t initValue); + +/*! + * @brief Gets the Initialization Register. + * + * This function allows the user to read the initialization register. + * + * @param base The ENC module base address. + * @return Value of initialization register. + */ +uint32_t ENC_HAL_GetInitReg(ENC_Type* base); + +/*! + * @brief Gets the Raw HOME Input. + * + * This function allows the user to read the value of the raw HOME input. + * + * @param base The ENC module base address. + * @return Value of the raw HOME input. + */ +static inline bool ENC_HAL_GetRawHomeInput(ENC_Type* base) +{ + return (bool) ENC_BRD_IMR_HOME(base); +} + +/*! + * @brief Gets the Raw INDEX Input. + * + * This function allows the user to read the value of the raw INDEX input. + * + * @param base The ENC module base address. + * @return Value of the raw INDEX input. + */ +static inline bool ENC_HAL_GetRawIndexInput(ENC_Type* base) +{ + return (bool) ENC_BRD_IMR_INDEX(base); +} + +/*! + * @brief Gets the Raw PHASEB Input. + * + * This function allows the user to read the value of the raw PHASEB input. + * + * @param base The ENC module base address. + * @return Value of the raw PHASEB input. + */ +static inline bool ENC_HAL_GetRawPhaseBInput(ENC_Type* base) +{ + return (bool) ENC_BRD_IMR_PHB(base); +} + +/*! + * @brief Gets the Raw PHASEA Input. + * + * This function allows the user to read the value of the raw PHASEA input. + * + * @param base The ENC module base address. + * @return Value of the raw PHASEA input. + */ +static inline bool ENC_HAL_GetRawPhaseAInput(ENC_Type* base) +{ + return (bool) ENC_BRD_IMR_PHA(base); +} + +/*! + * @brief Gets the Filtered HOME Input. + * + * This function allows the user to read the value of the filtered HOME input. + * + * @param base The ENC module base address. + * @return Value of the filtered HOME input. + */ +static inline bool ENC_HAL_GetFilteredHomeInput(ENC_Type* base) +{ + return (bool) ENC_BRD_IMR_FHOM(base); +} + +/*! + * @brief Gets the Filtered INDEX Input. + * + * This function allows the user to read the value of the filtered INDEX input. + * + * @param base The ENC module base address. + * @return Value of the filtered INDEX input. + */ +static inline bool ENC_HAL_GetFilteredIndexInput(ENC_Type* base) +{ + return (bool) ENC_BRD_IMR_FIND(base); +} + +/*! + * @brief Gets the Filtered PHASEB Input. + * + * This function allows the user to read the value of the filtered PHASEB input. + * + * @param base The ENC module base address. + * @return Value of the filtered PHASEB input. + */ +static inline bool ENC_HAL_GetFilteredPhaseBInput(ENC_Type* base) +{ + return (bool) ENC_BRD_IMR_FPHB(base); +} + +/*! + * @brief Gets the Filtered PHASEA Input. + * + * This function allows the user to read the value of the filtered PHASEA input. + * + * @param base The ENC module base address. + * @return Value of the filtered PHASEA input. + */ +static inline bool ENC_HAL_GetFilteredPhaseAInput(ENC_Type* base) +{ + return (bool) ENC_BRD_IMR_FPHA(base); +} + +/*! + * @brief Gets the ENC Test Count. + * + * This function allows the user to read the test count value + * of the test register. + * This value holds the number of quadrature advances to generate. + * + * @param base The ENC module base address. + * @return Value of test count. + */ +static inline uint8_t ENC_HAL_GetTestCount(ENC_Type* base) +{ + return (uint8_t) ENC_BRD_TST_TEST_COUNT(base); +} + +/*! + * @brief Sets the ENC Test Count. + * + * This function allows the user to write the test count value + * of the test register. + * This value holds the number of quadrature advances to generate. + * + * @param base The ENC module base address. + * @param testCount Value of test count. + */ +static inline void ENC_HAL_SetTestCount(ENC_Type* base, uint8_t testCount) +{ + ENC_BWR_TST_TEST_COUNT(base, testCount); +} + +/*! + * @brief Gets the ENC Test Period. + * + * This function allows the user to read the test period value + * of the test register. + * This value holds the period of quadrature phase in IPBus clock cycles. + * + * @param base The ENC module base address. + * @return Value of test period. + */ +static inline uint8_t ENC_HAL_GetTestPeriod(ENC_Type* base) +{ + return (uint8_t) (ENC_BRD_TST_TEST_PERIOD(base) & 0x1F); +} + +/*! + * @brief Sets the ENC Test Period. + * + * This function allows the user to write the test period value + * of the test register. + * This value holds the period of quadrature phase in IPBus clock cycles. + * + * @param base The ENC module base address. + * @param testPeriod Value of test period. + */ +static inline void ENC_HAL_SetTestPeriod(ENC_Type* base, uint8_t testPeriod) +{ + assert(testPeriod < 0x20); + ENC_BWR_TST_TEST_PERIOD(base, testPeriod); +} + +/*! + * @brief Sets the Quadrature Decoder Test Signal. + * + * This function allows the user to set the quadrature decoder test signal. + * Test module can generates quadrature decoder signal in a positive + * or negative direction. + * + * @param base The ENC module base address. + * @param enable The type of test signal. + */ +static inline void ENC_HAL_SetNegativeTestSignalCmd(ENC_Type* base, bool enable) +{ + ENC_BWR_TST_QDN(base, (enable ? 1U : 0U)); +} + +/*! + * @brief Gets the Quadrature Decoder Test Signal configuration setting. + * + * This function allows the user to get the test signal configuration setting. + * + * @param base The ENC module base address. + * @return The type of test signal. + */ +static inline bool ENC_HAL_GetNegativeTestSignalCmd(ENC_Type* base) +{ + return (bool) ENC_BRD_TST_QDN(base); +} + +/*! + * @brief Switches to enable the Test Counter. + * + * This function allows the user to enable test counter. It connects the test + * counter to inputs of the quadrature decoder module. + * + * @param base The ENC module base address. + * @param enable Bool parameter to enable/disable. + */ +static inline void ENC_HAL_SetTestCounterCmd(ENC_Type* base, bool enable) +{ + ENC_BWR_TST_TCE(base, (enable ? 1U : 0U)); +} + +/*! + * @brief Tests the Test Counter Enable bit. + * + * This function returns the configuration setting of the test + * counter enable bit. + * + * @param base The ENC module base address. + * @return Bit setting of the test counter enable. + */ +static inline bool ENC_HAL_GetTestCounterCmd(ENC_Type* base) +{ + return (bool) ENC_BRD_TST_TCE(base); +} + +/*! + * @brief Switches to enable the Test Module. + * + * This function allows the user to enable test module. + * Connects the test module to inputs of the quadrature decoder module. + * + * @param base The ENC module base address. + * @param enable Bool parameter to enable/disable. + */ +static inline void ENC_HAL_SetTestModuleCmd(ENC_Type* base, bool enable) +{ + ENC_BWR_TST_TEN(base, (enable ? 1U : 0U)); +} + +/*! + * @brief Tests the Test Module Enable bit. + * + * This function returns the configuration setting of the test + * module enable bit. + * + * @param base The ENC module base address. + * @return Bit setting of the test module enable. + */ +static inline bool ENC_HAL_GetTestModuleCmd(ENC_Type* base) +{ + return (bool) ENC_BRD_TST_TEN(base); +} + +/*! + * @brief Sets the ENC Modulus Register. + * + * This function allows the user to write the ENC modulus register. Modulus + * acts as the upper bound during modulo counting and as the upper reload value + * when rolling over from the lower bound. + * + * @param base The ENC module base address. + * @param modValue Value of modulo register. + */ +void ENC_HAL_SetModulusReg(ENC_Type* base, uint32_t modValue); + +/*! + * @brief Gets the ENC Modulus Register. + * + * This function allows the user to read the ENC modulus register. Modulus + * acts as the upper bound during modulo counting and as the upper reload value + * when rolling over from the lower bound. + * + * @param base The ENC module base address. + * @return Value of modulo register. + */ +uint32_t ENC_HAL_GetModulusReg(ENC_Type* base); + +/*! + * @brief Sets the ENC Compare Register. + * + * This function allows the user to write the ENC compare register. When the + * value of Position counter matches the value of Compare register + * the CTRL[CMPIRQ] flag is set and the POSMATCH output is asserted. + * + * @param base The ENC module base address. + * @param cmpValue Value of modulo register. + */ +void ENC_HAL_SetCmpReg(ENC_Type* base, uint32_t cmpValue); + +/*! + * @brief Gets the ENC Compare Register. + * + * This function allows the user to read the ENC compare register. When the + * value of Position counter matches the value of Compare register + * the CTRL[CMPIRQ] flag is set and the POSMATCH output is asserted. + * + * @param base The ENC module base address. + * @return Value of modulo register. + */ +uint32_t ENC_HAL_GetCmpReg(ENC_Type* base); + +/*! + * @brief Switches to enable the Update Hold Registers. + * + * This function allows the user to enable the update hold registers + * on external trigger input. Updating POSDH register will also cause + * the POSD register to be cleared. + * + * @param base The ENC module base address. + * @param enable Bool parameter to enable/disable. + */ +static inline void ENC_HAL_SetTriggerUpdateHoldRegCmd(ENC_Type* base, bool enable) +{ + ENC_BWR_CTRL2_UPDHLD(base, (enable ? 1U : 0U)); +} + +/*! + * @brief Gets the Update Hold Registers configuration setting. + * + * This function allows the user to get the update hold registers + * configuration setting. + * + * @param base The ENC module base address. + * @return The state of update hold registers + */ +static inline bool ENC_HAL_GetTriggerUpdateHoldRegCmd(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL2_UPDHLD(base); +} + +/*! + * @brief Enables Update Position Registers. + * + * This function allows the user to enable the update of position registers + * on external trigger input. Allows the TRIGGER input to clear POSD, REV, + * UPOS and LPOS registers on rising edge. + * + * @param base The ENC module base address. + * @param enable Bool parameter to enable/disable. + */ +static inline void ENC_HAL_SetTriggerClearPosRegCmd(ENC_Type* base, bool enable) +{ + ENC_BWR_CTRL2_UPDPOS(base, (enable ? 1U : 0U)); +} + +/*! + * @brief Gets the Update Position Registers configuration setting. + * + * This function allows the user to get the update of position registers + * configuration setting. + * + * @param base The ENC module base address. + * @return The state of update position registers + */ +static inline bool ENC_HAL_GetTriggerClearPosRegCmd(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL2_UPDPOS(base); +} + +/*! + * @brief Switches to enable the Modulo Counting. + * + * This function allows the user to enable the modulo counting. It allows + * the position counters to count in a modulo fashion using MOD and INIT + * as the upper and lower bounds of the counting range. + * + * @param base The ENC module base address. + * @param enable Bool parameter to enable/disable. + */ +static inline void ENC_HAL_SetModuloCountingCmd(ENC_Type* base, bool enable) +{ + ENC_BWR_CTRL2_MOD(base, (enable ? 1U : 0U)); +} + +/*! + * @brief Gets the Modulo Counting configuration setting. + * + * This function allows the user to get the modulo counting + * configuration setting. + * + * @param base The ENC module base address. + * @return The state of modulo counting. + */ +static inline bool ENC_HAL_GetModuloCountingCmd(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL2_MOD(base); +} + +/*! + * @brief Switches to enable the Roll-under Interrupt. + * + * This function allows the user to enable the roll-under interrupt. + * + * @param base The ENC module base address. + * @param enable Bool parameter to enable/disable. + */ +static inline void ENC_HAL_SetRollunderIntCmd(ENC_Type* base, bool enable) +{ + ENC_BWR_CTRL2_RUIE(base, (enable ? 1U : 0U)); +} + +/*! + * @brief Gets the Roll-under Interrupt configuration setting. + * + * This function allows the user to get the roll-under interrupt + * configuration setting. + * + * @param base The ENC module base address. + * @return The state of roll-under interrupt setting. + */ +static inline bool ENC_HAL_GetRollunderIntCmd(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL2_RUIE(base); +} + +/*! + * @brief Gets the Roll-under Interrupt Request configuration setting. + * + * This function returns the configuration setting of the Roll-under + * interrupt request. It is set when the position counter rolls under from + * the INIT value to the MOD value or from 0x00000000 to 0xFFFFFFFF. It will + * remain set until cleared by software. + * + * @param base The ENC module base address. + * @return Bit setting of the interrupt request bit. + */ +static inline bool ENC_HAL_GetRollunderIntFlag(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL2_RUIRQ(base); +} + +/*! + * @brief Clears the Roll-under Interrupt Request pending. + * + * This function clears the roll-under interrupt request bit. + * + * @param base The ENC module base address. + */ +static inline void ENC_HAL_ClearRollunderIntFlag(ENC_Type* base) +{ + ENC_BWR_CTRL2_RUIRQ(base, 1U); +} + +/*! + * @brief Switches to enable the Roll-over Interrupt. + * + * This function allows the user to enable the roll-over interrupt. + * + * @param base The ENC module base address. + * @param enable Bool parameter to enable/disable. + */ +static inline void ENC_HAL_SetRolloverIntCmd(ENC_Type* base, bool enable) +{ + ENC_BWR_CTRL2_ROIE(base, (enable ? 1U : 0U)); +} + +/*! + * @brief Gets the Roll-over Interrupt configuration setting. + * + * This function allows the user to get the roll-over interrupt + * configuration setting. + * + * @param base The ENC module base address. + * @return The state of roll-over interrupt setting. + */ +static inline bool ENC_HAL_GetRolloverIntCmd(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL2_ROIE(base); +} + +/*! + * @brief Gets the Roll-over Interrupt Request configuration setting. + * + * This function returns the configuration setting of the Roll-over + * interrupt request. It is set when the position counter rolls over the MOD + * value to the INIT value or from 0xFFFFFFFF to 0x00000000. It will remain + * set until cleared by software. + * + * @param base The ENC module base address. + * @return Bit setting of the interrupt request bit. + */ +static inline bool ENC_HAL_GetRolloverIntFlag(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL2_ROIRQ(base); +} + +/*! + * @brief Clears the Roll-over Interrupt Request pending. + * + * This function clears the roll-over interrupt request bit. + * + * @param base The ENC module base address. + */ +static inline void ENC_HAL_ClearRolloverIntFlag(ENC_Type* base) +{ + ENC_BWR_CTRL2_ROIRQ(base, 1U); +} + +/*! + * @brief Switches to enable the Modulus Revolution Counter. + * + * This function allows the user to enable the modulo revolution counter. + * This is used to determine how the revolution counter (REV) is incremented + * or decremented. By default REV is controlled based on the count direction + * and the INDEX pulse. As an option, REV can be controlled using + * the roll-over/under detection during modulo counting. + * + * @param base The ENC module base address. + * @param enable Bool parameter to enable/disable. + */ +static inline void ENC_HAL_SetModulusRevCounterCmd(ENC_Type* base, bool enable) +{ + ENC_BWR_CTRL2_REVMOD(base, (enable ? 1U : 0U)); +} + +/*! + * @brief Gets the Modulus Revolution Counter configuration setting. + * + * This function allows the user to get the modulus revolution counter + * configuration setting. + * + * @param base The ENC module base address. + * @return The state of modulus revolution counter. + */ +static inline bool ENC_HAL_GetModulusRevCounterCmd(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL2_REVMOD(base); +} + +/*! + * @brief Switches to enable the POSMATCH to pulse on Counters registers reading. + * + * This function allows the user to config control of the POSMATCH output. + * POSMATCH pulses when the UPOS, LPOS, REV or POSD registers are read - when set true + * or when match occurred between position register and Compare value register (false). + * + * @param base The ENC module base address. + * @param enable Bool parameter to enable/disable. + */ +static inline void ENC_HAL_SetPosmatchOnReadingCmd(ENC_Type* base, bool enable) +{ + ENC_BWR_CTRL2_OUTCTL(base, (enable ? 1U : 0U)); +} + +/*! + * @brief Gets the POSMATCH Output configuration setting. + * + * This function allows the user to get the POSMATCH output + * configuration setting. + * + * @param base The ENC module base address. + * @return The state of POSMATCH output setting. + */ +static inline bool ENC_HAL_GetPosmatchOnReadingCmd(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL2_OUTCTL(base); +} + +/*! + * @brief Switches to enable the Simultaneous PHASEA and PHASEB Change Interrupt. + * + * This function allows the user to enable the SAB interrupt. + * + * @param base The ENC module base address. + * @param enable Bool parameter to enable/disable. + */ +static inline void ENC_HAL_SetSimultaneousIntCmd(ENC_Type* base, bool enable) +{ + ENC_BWR_CTRL2_SABIE(base, (enable ? 1U : 0U)); +} + +/*! + * @brief Gets the SAB Interrupt configuration setting. + * + * This function allows the user to get the SAB interrupt + * configuration setting. + * + * @param base The ENC module base address. + * @return The state of SAB interrupt setting. + */ +static inline bool ENC_HAL_GetSimultaneousIntCmd(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL2_SABIE(base); +} + +/*! + * @brief Gets the SAB Interrupt Request configuration setting. + * + * This function returns the configuration setting of the SAB + * interrupt request. It indicates that the PHASEA and PHASEB inputs changed + * simultaneously (within a single clock period). This event typically indicates + * an error condition because quadrature coding requires only one of these inputs + * to change at a time. The bit remains set until it is cleared by software or a reset. + * + * @param base The ENC module base address. + * @return Bit setting of the interrupt request bit. + */ +static inline bool ENC_HAL_GetSimultaneousIntFlag(ENC_Type* base) +{ + return (bool) ENC_BRD_CTRL2_SABIRQ(base); +} + +/*! + * @brief Clears the SAB Interrupt Request pending. + * + * This function clears the SAB interrupt request bit. + * + * @param base The ENC module base address. + */ +static inline void ENC_HAL_ClearSimultaneousIntFlag(ENC_Type* base) +{ + ENC_BWR_CTRL2_SABIRQ(base, 1U); +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif +#endif /* __FSL_ENC_HAL_H__*/ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_enet_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_enet_hal.h new file mode 100755 index 0000000..de2bfb7 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_enet_hal.h @@ -0,0 +1,1139 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_ENET_HAL_H__ +#define __FSL_ENET_HAL_H__ +#include <assert.h> +#include <stdint.h> +#include <stdbool.h> +#include "fsl_device_registers.h" +#include "core_cmInstr.h" +#if FSL_FEATURE_SOC_ENET_COUNT + +/*! + * @addtogroup enet_hal + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Defines the system endian type.*/ + +/*! @brief Defines the alignment operation.*/ +#define ENET_ALIGN(x,align) ((unsigned int)((x) + ((align)-1)) & (unsigned int)(~(unsigned int)((align)- 1))) +/*! @brief Defines the macro used for byte order change on Buffer descriptor*/ +#if FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY +#define BD_SHORTSWAP(n) __REV16(n) +#define BD_LONGSWAP(n) __REV(n) +#else +#define BD_SHORTSWAP(n) (n) +#define BD_LONGSWAP(n) (n) +#endif + +/*! @brief Defines the Status return codes.*/ +typedef enum _enet_status +{ + kStatus_ENET_Success = 0U, + kStatus_ENET_InvalidInput, /*!< Invalid ENET input parameter */ + kStatus_ENET_InvalidDevice, /*!< Invalid ENET device*/ + kStatus_ENET_InitTimeout, /*!< ENET initialize timeout*/ + kStatus_ENET_MemoryAllocateFail, /*!< Memory allocate failure*/ + kStatus_ENET_GetClockFreqFail, /*!< Get clock frequency failure*/ + kStatus_ENET_Initialized, /*!< ENET device already initialized*/ + kStatus_ENET_Open, /*!< Open ENET device*/ + kStatus_ENET_Close, /*!< Close ENET device*/ + kStatus_ENET_Layer2UnInitialized, /*!< Layer2 PTP buffer queue uninitialized*/ + kStatus_ENET_Layer2OverLarge, /*!< Layer2 packet length over large*/ + kStatus_ENET_Layer2BufferFull, /*!< Layer2 packet buffer full*/ + kStatus_ENET_Layer2TypeError, /*!< Layer2 packet error type*/ + kStatus_ENET_PtpringBufferFull, /*!< PTP ring buffer full*/ + kStatus_ENET_PtpringBufferEmpty, /*!< PTP ring buffer empty*/ + kStatus_ENET_SMIUninitialized, /*!< SMI uninitialized*/ + kStatus_ENET_SMIVisitTimeout, /*!< SMI visit timeout*/ + kStatus_ENET_RxbdInvalid, /*!< Receive buffer descriptor invalid*/ + kStatus_ENET_RxbdEmpty, /*!< Receive buffer descriptor empty*/ + kStatus_ENET_RxbdTrunc, /*!< Receive buffer descriptor truncate*/ + kStatus_ENET_RxbdError, /*!< Receive buffer descriptor error*/ + kStatus_ENET_RxBdFull, /*!< Receive buffer descriptor full*/ + kStatus_ENET_SmallRxBuffSize, /*!< Receive buffer size is so small*/ + kStatus_ENET_NoEnoughRxBuffers, /*!< Small receive buffer size*/ + kStatus_ENET_LargeBufferFull, /*!< Receive large buffer full*/ + kStatus_ENET_TxLarge, /*!< Transmit large packet*/ + kStatus_ENET_TxbdFull, /*!< Transmit buffer descriptor full*/ + kStatus_ENET_TxbdNull, /*!< Transmit buffer descriptor Null*/ + kStatus_ENET_TxBufferNull, /*!< Transmit data buffer Null*/ + kStatus_ENET_NoRxBufferLeft, /*!< No more receive buffer left*/ + kStatus_ENET_UnknownCommand, /*!< Invalid ENET PTP IOCTL command*/ + kStatus_ENET_TimeOut, /*!< ENET Timeout*/ + kStatus_ENET_MulticastPointerNull, /*!< Null multicast group pointer*/ + kStatus_ENET_NoMulticastAddr, /*!< No multicast group address*/ + kStatus_ENET_AlreadyAddedMulticast, /*!< Have Already added to multicast group*/ + kStatus_ENET_PHYAutoDiscoverFail /*!< Failed to automatically discover PHY*/ +} enet_status_t; + +#if FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY +/*! @brief Defines the control and status regions of the receive buffer descriptor.*/ +typedef enum _enet_rx_bd_control_status +{ + kEnetRxBdBroadCast = 0x8000U, /*!< Broadcast */ + kEnetRxBdMultiCast = 0x4000U, /*!< Multicast*/ + kEnetRxBdLengthViolation = 0x2000U, /*!< Receive length violation*/ + kEnetRxBdNoOctet = 0x1000U, /*!< Receive non-octet aligned frame*/ + kEnetRxBdCrc = 0x0400U, /*!< Receive CRC error*/ + kEnetRxBdOverRun = 0x0200U, /*!< Receive FIFO overrun*/ + kEnetRxBdTrunc = 0x0100U, /*!< Frame is truncated */ + kEnetRxBdEmpty = 0x0080U, /*!< Empty bit*/ + kEnetRxBdRxSoftOwner1 = 0x0040U, /*!< Receive software owner*/ + kEnetRxBdWrap = 0x0020U, /*!< Update buffer descriptor*/ + kEnetRxBdRxSoftOwner2 = 0x0010U, /*!< Receive software owner*/ + kEnetRxBdLast = 0x0008U, /*!< Last BD in the frame*/ + kEnetRxBdMiss = 0x0001U /*!< Receive for promiscuous mode*/ +} enet_rx_bd_control_status_t; + +/*! @brief Defines the control extended region1 of the receive buffer descriptor.*/ +typedef enum _enet_rx_bd_control_extend0 +{ + kEnetRxBdIpv4 = 0x0100U, /*!< Ipv4 frame*/ + kEnetRxBdIpv6 = 0x0200U, /*!< Ipv6 frame*/ + kEnetRxBdVlan = 0x0400U, /*!< VLAN*/ + kEnetRxBdProtocolChecksumErr = 0x1000U, /*!< Protocol checksum error*/ + kEnetRxBdIpHeaderChecksumErr = 0x2000U, /*!< IP header checksum error*/ +} enet_rx_bd_control_extend0_t; + +/*! @brief Defines the control extended region2 of the receive buffer descriptor.*/ +typedef enum _enet_rx_bd_control_extend1 +{ + kEnetRxBdUnicast = 0x0001U, /*!< Unicast frame*/ + kEnetRxBdCollision = 0x0002U, /*!< BD collision*/ + kEnetRxBdPhyErr = 0x0004U, /*!< PHY error*/ + kEnetRxBdMacErr = 0x0080U, /*!< Mac error*/ + kEnetRxBdIntrrupt = 0x8000U /*!< BD interrupt*/ +} enet_rx_bd_control_extend1_t; + +/*! @brief Defines the control status region of the transmit buffer descriptor.*/ +typedef enum _enet_tx_bd_control_status +{ + kEnetTxBdReady = 0x0080U, /*!< Ready bit*/ + kEnetTxBdTxSoftOwner1 = 0x0040U, /*!< Transmit software owner*/ + kEnetTxBdWrap = 0x0020U, /*!< Wrap buffer descriptor*/ + kEnetTxBdTxSoftOwner2 = 0x0010U, /*!< Transmit software owner*/ + kEnetTxBdLast = 0x0008U, /*!< Last BD in the frame*/ + kEnetTxBdTransmitCrc = 0x0004U /*!< Receive for transmit CRC*/ +} enet_tx_bd_control_status_t; + +/*! @brief Defines the control extended region1 of the transmit buffer descriptor.*/ +typedef enum _enet_tx_bd_control_extend0 +{ + kEnetTxBdTxErr = 0x0080U, /*!< Transmit error*/ + kEnetTxBdTxUnderFlowErr = 0x0020U, /*!< Underflow error*/ + kEnetTxBdExcessCollisionErr = 0x0010U, /*!< Excess collision error*/ + kEnetTxBdTxFrameErr = 0x0008U, /*!< Frame error*/ + kEnetTxBdLatecollisionErr = 0x0004U, /*!< Late collision error*/ + kEnetTxBdOverFlowErr = 0x0002U, /*!< Overflow error*/ + kEnetTxTimestampErr = 0x0001U /*!< Timestamp error*/ +} enet_tx_bd_control_extend0_t; + +/*! @brief Defines the control extended region2 of the transmit buffer descriptor.*/ +typedef enum _enet_tx_bd_control_extend1 +{ + kEnetTxBdTxInterrupt = 0x0040U, /*!< Transmit interrupt*/ + kEnetTxBdTimeStamp = 0x0020U /*!< Transmit timestamp flag */ +} enet_tx_bd_control_extend1_t; +#else +/*! @brief Defines the control and status region of the receive buffer descriptor.*/ +typedef enum _enet_rx_bd_control_status +{ + kEnetRxBdEmpty = 0x8000U, /*!< Empty bit*/ + kEnetRxBdRxSoftOwner1 = 0x4000U, /*!< Receive software owner*/ + kEnetRxBdWrap = 0x2000U, /*!< Update buffer descriptor*/ + kEnetRxBdRxSoftOwner2 = 0x1000U, /*!< Receive software owner*/ + kEnetRxBdLast = 0x0800U, /*!< Last BD in the frame*/ + kEnetRxBdMiss = 0x0100U, /*!< Receive for promiscuous mode*/ + kEnetRxBdBroadCast = 0x0080U, /*!< Broadcast */ + kEnetRxBdMultiCast = 0x0040U, /*!< Multicast*/ + kEnetRxBdLengthViolation = 0x0020U, /*!< Receive length violation*/ + kEnetRxBdNoOctet = 0x0010U, /*!< Receive non-octet aligned frame*/ + kEnetRxBdCrc = 0x0004U, /*!< Receive CRC error*/ + kEnetRxBdOverRun = 0x0002U, /*!< Receive FIFO overrun*/ + kEnetRxBdTrunc = 0x0001U /*!< Frame is truncated */ +} enet_rx_bd_control_status_t; + +/*! @brief Defines the control extended region1 of the receive buffer descriptor.*/ +typedef enum _enet_rx_bd_control_extend0 +{ + kEnetRxBdIpv4 = 0x0001U, /*!< Ipv4 frame*/ + kEnetRxBdIpv6 = 0x0002U, /*!< Ipv6 frame*/ + kEnetRxBdVlan = 0x0004U, /*!< VLAN*/ + kEnetRxBdProtocolChecksumErr = 0x0010U, /*!< Protocol checksum error*/ + kEnetRxBdIpHeaderChecksumErr = 0x0020U, /*!< IP header checksum error*/ +} enet_rx_bd_control_extend0_t; + +/*! @brief Defines the control extended region2 of the receive buffer descriptor.*/ +typedef enum _enet_rx_bd_control_extend1 +{ + kEnetRxBdIntrrupt = 0x0080U, /*!< BD interrupt*/ + kEnetRxBdUnicast = 0x0100U, /*!< Unicast frame*/ + kEnetRxBdCollision = 0x0200U, /*!< BD collision*/ + kEnetRxBdPhyErr = 0x0400U, /*!< PHY error*/ + kEnetRxBdMacErr = 0x8000U /*!< Mac error */ +} enet_rx_bd_control_extend1_t; + +/*! @brief Defines the control status of the transmit buffer descriptor.*/ +typedef enum _enet_tx_bd_control_status +{ + kEnetTxBdReady = 0x8000U, /*!< Ready bit*/ + kEnetTxBdTxSoftOwner1 = 0x4000U, /*!< Transmit software owner*/ + kEnetTxBdWrap = 0x2000U, /*!< Wrap buffer descriptor*/ + kEnetTxBdTxSoftOwner2 = 0x1000U, /*!< Transmit software owner*/ + kEnetTxBdLast = 0x0800U, /*!< Last BD in the frame*/ + kEnetTxBdTransmitCrc = 0x0400U /*!< Receive for transmit CRC */ +} enet_tx_bd_control_status_t; + +/*! @brief Defines the control extended region1 of the transmit buffer descriptor.*/ +typedef enum _enet_tx_bd_control_extend0 +{ + kEnetTxBdTxErr = 0x8000U, /*!< Transmit error*/ + kEnetTxBdTxUnderFlowErr = 0x2000U, /*!< Underflow error*/ + kEnetTxBdExcessCollisionErr = 0x1000U, /*!< Excess collision error*/ + kEnetTxBdTxFrameErr = 0x0800U, /*!< Frame error*/ + kEnetTxBdLatecollisionErr = 0x0400U, /*!< Late collision error*/ + kEnetTxBdOverFlowErr = 0x0200U, /*!< Overflow error*/ + kEnetTxTimestampErr = 0x0100U /*!< Timestamp error*/ +} enet_tx_bd_control_extend0_t; + +/*! @brief Defines the control extended region2 of the transmit buffer descriptor.*/ +typedef enum _enet_tx_bd_control_extend1 +{ + kEnetTxBdTxInterrupt = 0x4000U, /*!< Transmit interrupt*/ + kEnetTxBdTimeStamp = 0x2000U /*!< Transmit timestamp flag */ +} enet_tx_bd_control_extend1_t; +#endif + +/*! @brief Defines the macro to the different ENET constant value.*/ +typedef enum _enet_constant_parameter +{ + kEnetMacAddrLen = 6U, /*!< ENET mac address length*/ + kEnetHashValMask = 0x1FU, /*!< ENET hash value mask*/ + kEnetMinBuffSize = 256U, /*!< ENET minimum buffer size*/ + kEnetMaxTimeout = 0xFFFFU, /*!< ENET timeout*/ + kEnetMdcFreq = 2500000U /*!< MDC frequency*/ +} enet_constant_parameter_t; + +/*! @brief Defines the normal FIFO configuration for ENET MAC.*/ +typedef enum _enet_fifo_configure +{ + kEnetMinTxFifoAlmostFull = 6U, /*!< ENET minimum transmit FIFO almost full value*/ + kEnetMinFifoAlmostEmpty = 4U, /*!< ENET minimum FIFO almost empty value*/ + kEnetDefaultTxFifoAlmostFull = 8U /*!< ENET default transmit FIFO almost full value*/ +} enet_fifo_configure_t; + +/*! @brief Defines the normal operating mode and sleep mode for ENET MAC.*/ +typedef enum _enet_mac_operate_mode +{ + kEnetMacNormalMode = 0U, /*!< Normal operating mode for ENET MAC*/ + kEnetMacSleepMode = 1U /*!< Sleep mode for ENET MAC*/ +} enet_mac_operate_mode_t; + +/*! @brief Defines the RMII or MII mode for data interface between the MAC and the PHY.*/ +typedef enum _enet_config_rmii_mode +{ + kEnetCfgMii = 0U, /*!< MII mode for data interface*/ + kEnetCfgRmii = 1U /*!< RMII mode for data interface*/ +} enet_config_rmii_mode_t; + +/*! @brief Defines the 10 Mbps or 100 Mbps speed mode for the data transfer.*/ +typedef enum _enet_config_speed +{ + kEnetCfgSpeed100M = 0U, /*!< Speed 100 M mode*/ + kEnetCfgSpeed10M = 1U /*!< Speed 10 M mode*/ +} enet_config_speed_t; + +/*! @brief Defines the half or full duplex mode for the data transfer.*/ +typedef enum _enet_config_duplex +{ + kEnetCfgHalfDuplex = 0U, /*!< Half duplex mode*/ + kEnetCfgFullDuplex = 1U /*!< Full duplex mode*/ +} enet_config_duplex_t; + +/*! @brief Defines the write operation for the MII.*/ +typedef enum _enet_mii_write +{ + kEnetWriteNoCompliant = 0U, /*!< Write frame operation, but not MII compliant.*/ + kEnetWriteValidFrame = 1U, /*!< Write frame operation for a valid MII management frame*/ +}enet_mii_write_t; + +/*! @brief Defines the read operation for the MII.*/ +typedef enum _enet_mii_read +{ + kEnetReadValidFrame = 2U, /*!< Read frame operation for a valid MII management frame.*/ + kEnetReadNoCompliant = 3U /*!< Read frame operation, but not MII compliant*/ +}enet_mii_read_t; + +/*! @brief Defines the initialization, enables or disables the operation for a special address filter */ +typedef enum _enet_special_address_filter +{ + kEnetSpecialAddressInit = 0U, /*!< Initializes the special address filter.*/ + kEnetSpecialAddressEnable = 1U, /*!< Enables the special address filter.*/ + kEnetSpecialAddressDisable = 2U /*!< Disables the special address filter.*/ +} enet_special_address_filter_t; + +/*! @brief Defines the 1588 timer channel numbers.*/ +typedef enum _enet_timer_channel +{ + kEnetTimerChannel1 = 0U, /*!< 1588 timer Channel 1*/ + kEnetTimerChannel2 = 1U, /*!< 1588 timer Channel 2*/ + kEnetTimerChannel3 = 2U, /*!< 1588 timer Channel 3*/ + kEnetTimerChannel4 = 3U /*!< 1588 timer Channel 4*/ +} enet_timer_channel_t; + +/*! @brief Defines the capture or compare mode for 1588 timer channels.*/ +typedef enum _enet_timer_channel_mode +{ + kEnetChannelDisable = 0U, /*!< Disable timer channel*/ + kEnetChannelRisingCapture = 1U, /*!< Input capture on rising edge*/ + kEnetChannelFallingCapture = 2U, /*!< Input capture on falling edge*/ + kEnetChannelBothCapture = 3U, /*!< Input capture on both edges*/ + kEnetChannelSoftCompare = 4U, /*!< Output compare software only*/ + kEnetChannelToggleCompare = 5U, /*!< Toggle output on compare*/ + kEnetChannelClearCompare = 6U, /*!< Clear output on compare*/ + kEnetChannelSetCompare = 7U, /*!< Set output on compare*/ + kEnetChannelClearCompareSetOverflow = 10U, /*!< Clear output on compare, set output on overflow*/ + kEnetChannelSetCompareClearOverflow = 11U, /*!< Set output on compare, clear output on overflow*/ + kEnetChannelPulseLowonCompare = 14U, /*!< Pulse output low on compare for one 1588 clock cycle*/ + kEnetChannelPulseHighonCompare = 15U /*!< Pulse output high on compare for one 1588 clock cycle*/ +} enet_timer_channel_mode_t; + +/*! @brief Defines the RXFRAME/RXBYTE/TXFRAME/TXBYTE/MII/TSTIMER/TSAVAIL interrupt source for ENET.*/ +typedef enum _enet_interrupt_request +{ + kEnetBabrInterrupt = 0x40000000U, /*!< Babbling receive error interrupt source*/ + kEnetBabtInterrupt = 0x20000000U, /*!< Babbling transmit error interrupt source*/ + kEnetGraceStopInterrupt = 0x10000000U, /*!< Graceful stop complete interrupt source*/ + kEnetTxFrameInterrupt = 0x08000000U, /*!< TX FRAME interrupt source */ + kEnetTxByteInterrupt = 0x04000000U, /*!< TX BYTE interrupt source*/ + kEnetRxFrameInterrupt = 0x02000000U, /*!< RX FRAME interrupt source */ + kEnetRxByteInterrupt = 0x01000000U, /*!< RX BYTE interrupt source */ + kEnetMiiInterrupt = 0x00800000U, /*!< MII interrupt source*/ + kEnetEBusERInterrupt = 0x00400000U, /*!< Ethernet bus error interrupt source*/ + kEnetLateCollisionInterrupt = 0x00200000U, /*!< Late collision interrupt source*/ + kEnetRetryLimitInterrupt = 0x00100000U, /*!< Collision Retry Limit interrupt source*/ + kEnetUnderrunInterrupt = 0x00080000U, /*!< Transmit FIFO underrun interrupt source*/ + kEnetPayloadRxInterrupt = 0x00040000U, /*!< Payload Receive interrupt source*/ + kEnetWakeupInterrupt = 0x00020000U, /*!< WAKEUP interrupt source*/ + kEnetTsAvailInterrupt = 0x00010000U, /*!< TS AVAIL interrupt source*/ + kEnetTsTimerInterrupt = 0x00008000U, /*!< TS WRAP interrupt source*/ + kEnetAllInterrupt = 0x7FFFFFFFU /*!< All interrupt*/ +} enet_interrupt_request_t; + +/* Internal irq number*/ +typedef enum _enet_irq_number +{ + kEnetTsTimerNumber = 0, /*!< ENET ts_timer irq number*/ + kEnetReceiveNumber = 1, /*!< ENET receive irq number*/ + kEnetTransmitNumber = 2, /*!< ENET transmit irq number*/ + kEnetMiiErrorNumber = 3 /*!< ENET mii error irq number*/ +} enet_irq_number_t; + +/*! @brief Defines the ENET main constant.*/ +typedef enum _enet_frame_max +{ + kEnetNsecOneSec = 1000000000, /*!< NanoSecond in one second*/ + kEnetMaxFrameSize = 1518, /*!< Maximum frame size*/ + kEnetMaxFrameVlanSize = 1522, /*!< Maximum VLAN frame size*/ + kEnetMaxFrameDateSize = 1500, /*!< Maximum frame data size*/ + kEnetDefaultTruncLen = 2047, /*!< Default Truncate length*/ + kEnetDefaultIpg = 12, /*!< ENET default transmit inter packet gap*/ + kEnetMaxValidTxIpg = 27, /*!< Maximum valid transmit IPG*/ + kEnetMinValidTxIpg = 8, /*!< Minimum valid transmit IPG*/ + kEnetMaxMdioHoldCycle = 7, /*!< Maximum hold time clock cycle on MDIO Output*/ + kEnetMaxFrameBdNumbers = 6, /*!< Maximum buffer descriptor numbers of a frame*/ + kEnetFrameFcsLen = 4, /*!< FCS length*/ + kEnetEthernetHeadLen = 14, /*!< Ethernet Frame header length*/ + kEnetEthernetVlanHeadLen = 18 /*!< Ethernet VLAN frame header length*/ +} enet_frame_max_t; + +/*! @brief Defines the transmit accelerator configuration*/ +typedef enum _enet_txaccelerator_config +{ + kEnetTxAccelisShift16Enabled = 0x01U, /*!< Tx FIFO shift-16*/ + kEnetTxAccelIpCheckEnabled = 0x08U, /*!< Insert IP header checksum */ + kEnetTxAccelProtoCheckEnabled = 0x10U /*!< Insert protocol checksum*/ +} enet_txaccelerator_config_t; + +/*! @brief Defines the receive accelerator configuration*/ +typedef enum _enet_rxaccelerator_config +{ + kEnetRxAccelPadRemoveEnabled = 0x01U, /*!< Padding removal for short IP frames*/ + kEnetRxAccelIpCheckEnabled = 0x02U, /*!< Discard with wrong IP header checksum */ + kEnetRxAccelProtoCheckEnabled = 0x04U, /*!< Discard with wrong protocol checksum*/ + kEnetRxAccelMacCheckEnabled = 0x40U, /*!< Discard with Mac layer errors*/ + kEnetRxAccelisShift16Enabled = 0x80U /*!< Rx FIFO shift-16*/ +} enet_rxaccelerator_config_t; + + +/*! @brief Defines the ENET MAC control Configure*/ +typedef enum _enet_mac_control_flag +{ + kEnetStopModeEnable = 0x1U, /*!< ENET Stop mode enable*/ + kEnetDebugModeEnable = 0x2U, /*! Enable MAC to enter hardware freeze when enter Debug mode*/ + kEnetPayloadlenCheckEnable = 0x4U, /*!< ENET receive payload length check Enable*/ + kEnetRxFlowControlEnable = 0x8U, /*!< Enable ENET flow control*/ + kEnetRxCrcFwdEnable = 0x10U, /*!< Received frame crc is stripped from the frame*/ + kEnetRxPauseFwdEnable = 0x20U,/*!< Pause frames are forwarded to the user application*/ + kEnetRxPadRemoveEnable = 0x40U, /*!< Padding is removed from received frames*/ + kEnetRxBcRejectEnable = 0x80U, /*!< Broadcast frame reject*/ + kEnetRxPromiscuousEnable = 0x100U, /*!< Promiscuous mode enabled*/ + kEnetTxCrcFwdEnable = 0x200U, /*!< Enable transmit frame with the crc from application*/ + kEnetTxCrcBdEnable = 0x400U, /*!< When Tx CRC FWD disable, Tx buffer descriptor enable Transmit CRC*/ + kEnetMacAddrInsert = 0x800U, /*!< Enable MAC address insert*/ + kEnetTxAccelEnable = 0x1000U, /*!< Transmit accelerator enable*/ + kEnetRxAccelEnable = 0x2000U, /*!< Transmit accelerator enable*/ + kEnetStoreAndFwdEnable = 0x4000U, /*!< Switcher to enable store and forward*/ + kEnetMacMibEnable = 0x8000U, /*!< Disable MIB module*/ + kEnetSMIPreambleDisable = 0x10000U, /*!< Enable SMI preamble*/ + kEnetVlanTagEnabled = 0x20000U, /*!< Enable Vlan Tag*/ + kEnetMacEnhancedEnable = 0x40000U /*!< Enable enhanced MAC feature (1588 feature/enhanced buff descriptor)*/ +} enet_mac_control_flag_t; + +#if (!FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY) +/*! @brief Defines the buffer descriptor structure for the little-Endian system and endianness configurable IP.*/ +typedef struct ENETBdStruct +{ + uint16_t length; /*!< Buffer descriptor data length*/ + uint16_t control; /*!< Buffer descriptor control*/ + uint8_t *buffer; /*!< Data buffer pointer*/ + uint16_t controlExtend0; /*!< Extend buffer descriptor control0*/ + uint16_t controlExtend1; /*!< Extend buffer descriptor control1*/ + uint16_t payloadCheckSum; /*!< Internal payload checksum*/ + uint8_t headerLength; /*!< Header length*/ + uint8_t protocalTyte; /*!< Protocol type*/ + uint16_t reserved0; + uint16_t controlExtend2; /*!< Extend buffer descriptor control2*/ + uint32_t timestamp; /*!< Timestamp */ + uint16_t reserved1; + uint16_t reserved2; + uint16_t reserved3; + uint16_t reserved4; +} enet_bd_struct_t; + +#else +/*! @brief Defines the buffer descriptors structure for the Big-Endian system.*/ +typedef struct ENETBdStruct +{ + uint16_t control; /*!< Buffer descriptor control */ + uint16_t length; /*!< Buffer descriptor data length*/ + uint8_t *buffer; /*!< Data buffer pointer*/ + uint16_t controlExtend1; /*!< Extend buffer descriptor control1*/ + uint16_t controlExtend0; /*!< Extend buffer descriptor control0*/ + uint8_t headerLength; /*!< Header length*/ + uint8_t protocalTyte; /*!< Protocol type*/ + uint16_t payloadCheckSum; /*!< Internal payload checksum*/ + uint16_t controlExtend2; /*!< Extend buffer descriptor control2*/ + uint16_t reserved0; + uint32_t timestamp; /*!< Timestamp pointer*/ + uint16_t reserved1; + uint16_t reserved2; + uint16_t reserved3; + uint16_t reserved4; +} enet_bd_struct_t; +#endif + +/*! @brief Defines the RMII/MII configuration structure*/ +typedef struct ENETConfigRMII +{ + enet_config_rmii_mode_t mode; /*!< RMII/MII mode*/ + enet_config_speed_t speed; /*!< 100M/10M Speed*/ + enet_config_duplex_t duplex; /*!< Full/Duplex mode*/ + bool isRxOnTxDisabled; /*!< Disable rx and tx*/ + bool isLoopEnabled; /*!< MII loop mode*/ +} enet_config_rmii_t; + +/*! @brief Defines the configuration structure for the 1588 PTP timer.*/ +typedef struct ENETConfigPtpTimer +{ + bool isSlaveEnabled; /*!< Master or slave PTP timer*/ + uint32_t clockIncease; /*!< Timer increase value each clock period*/ + uint32_t period; /*!< Timer period for generate interrupt event */ +#if FSL_FEATURE_ENET_PTP_TIMER_CHANNEL_INTERRUPT_ERRATA_2579 + /*!< If support for IEEE 1588 timestamp timer overflow interrupt, \ + set the channel for overflow interrupt */ + enet_timer_channel_t channel; +#endif +} enet_config_ptp_timer_t; + +/*! @brief Defines the transmit FIFO configuration.*/ +typedef struct ENETConfigTxFifo +{ + bool isStoreForwardEnabled; /*!< Transmit FIFO store and forward */ + uint8_t txFifoWrite; /*!< Transmit FIFO write. This should be set when isStoreForwardEnabled + is false. this field indicates the number of bytes in step of 64 bytes + written to the Tx FiFO before transmission of a frame begins*/ + uint8_t txEmpty; /*!< Transmit FIFO section empty threshold, default zero*/ + uint8_t txAlmostEmpty; /*!< Transmit FIFO section almost empty threshold, The minimum value of 4 should be set*/ + uint8_t txAlmostFull; /*!< Transmit FIFO section almost full threshold, The minimum value of 6 is required + a recommended value of at least 8 should be set*/ +} enet_config_tx_fifo_t; + +/*! @brief Defines the receive FIFO configuration.*/ +typedef struct ENETConfigRxFifo +{ + uint8_t rxFull; /*!< Receive FIFO section full threshold, default zero*/ + uint8_t rxAlmostFull; /*!< Receive FIFO section almost full threshold, The minimum value of 4 should be set*/ + uint8_t rxEmpty; /*!< Receive FIFO section empty threshold, default zero*/ + uint8_t rxAlmostEmpty; /*!< Receive FIFO section almost empty threshold, The minimum value of 4 should be set*/ +} enet_config_rx_fifo_t; + +/*!@ brief Defines the receive statistics of MIB*/ +typedef struct ENETMibRxStat +{ + uint16_t rxPackets; /*!< Receive packets*/ + uint16_t rxBroadcastPackets; /*!< Receive broadcast packets*/ + uint16_t rxMulticastPackets; /*!< Receive multicast packets*/ + uint16_t rxCrcAlignErrorPackets; /*!< Receive packets with crc/align error*/ + uint16_t rxUnderSizeGoodPackets; /*!< Receive packets undersize and good crc*/ + uint16_t rxUnderSizeBadPackets; /*!< Receive packets undersize and bad crc*/ + uint16_t rxOverSizeGoodPackets; /*!< Receive packets oversize and good crc*/ + uint16_t rxOverSizeBadPackets; /*!< Receive packets oversize and bad crc*/ + uint16_t rxByte64Packets; /*!< Receive packets 64-byte*/ + uint16_t rxByte65to127Packets; /*!< Receive packets 65-byte to 127-byte*/ + uint16_t rxByte128to255Packets; /*!< Receive packets 128-byte to 255-byte*/ + uint16_t rxByte256to511Packets; /*!< Receive packets 256-byte to 511-byte */ + uint16_t rxByte512to1023Packets; /*!< Receive packets 512-byte to 1023-byte*/ + uint16_t rxByte1024to2047Packets; /*!< Receive packets 1024-byte to 2047-byte*/ + uint16_t rxByteOver2048Packets; /*!< Receive packets over 2048-byte*/ + uint32_t rxOctets; /*!< Receive octets*/ + uint32_t ieeeOctetsrxFrameOk; /*!< Receive octets of received Frames ok*/ + uint16_t ieeerxFrameDrop; /*!< Receive Frames dropped*/ + uint16_t ieeerxFrameOk; /*!< Receive Frames ok*/ + uint16_t ieeerxFrameCrcErr; /*!< Receive Frames with crc error*/ + uint16_t ieeetxFrameAlignErr; /*!< Receive Frames with align error*/ + uint16_t ieeetxFrameMacErr; /*!< Receive Frames with mac error*/ + uint16_t ieeetxFramePause; /*!< Receive flow control pause frames*/ +} enet_mib_rx_stat_t; + +/*!@ brief Defines the transmit statistics of MIB*/ +typedef struct ENETMibTxStat +{ + uint16_t txPackets; /*!< Transmit packets*/ + uint16_t txBroadcastPackets; /*!< Transmit broadcast packets*/ + uint16_t txMulticastPackets; /*!< Transmit multicast packets*/ + uint16_t txCrcAlignErrorPackets; /*!< Transmit packets with crc/align error*/ + uint16_t txUnderSizeGoodPackets; /*!< Transmit packets undersize and good crc*/ + uint16_t txUnderSizeBadPackets; /*!< Transmit packets undersize and bad crc*/ + uint16_t txOverSizeGoodPackets; /*!< Transmit packets oversize and good crc*/ + uint16_t txOverSizeBadPackets; /*!< Transmit packets oversize and bad crc*/ + uint16_t txCollision; /*!< Transmit packets with collision*/ + uint16_t txByte64Packets; /*!< Transmit packets 64-byte*/ + uint16_t txByte65to127Packets; /*!< Transmit packets 65-byte to 127-byte*/ + uint16_t txByte128to255Packets; /*!< Transmit packets 128-byte to 255-byte*/ + uint16_t txByte256to511Packets; /*!< Transmit packets 256-byte to 511-byte*/ + uint16_t txByte512to1023Packets; /*!< Transmit packets 512-byte to 1023-byte*/ + uint16_t txByte1024to2047Packets; /*!< Transmit packets 1024-byte to 2047-byte*/ + uint16_t txByteOver2048Packets; /*!< Transmit packets over 2048-byte*/ + uint32_t txOctets; /*!< Transmit octets*/ + uint32_t ieeeOctetstxFrameOk; /*!< Transmit octets of transmitted frames ok*/ + uint16_t ieeetxFrameOk; /*!< Transmit frames ok*/ + uint16_t ieeetxFrameOneCollision; /*!< Transmit frames with single collision*/ + uint16_t ieeetxFrameMultiCollison; /*!< Transmit frames with multicast collision*/ + uint16_t ieeetxFrameLateCollison; /*!< Transmit frames with late collision*/ + uint16_t ieeetxFrmaeExcCollison; /*!< Transmit frames with excessive collision*/ + uint16_t ieeetxFrameDelay; /*!< Transmit frames after deferral delay*/ + uint16_t ieeetxFrameMacErr; /*!< Transmit frames with MAC error*/ + uint16_t ieeetxFrameCarrSenseErr; /*!< Transmit frames with carrier sense error*/ + uint16_t ieeetxFramePause; /*!< Transmit flow control Pause frame*/ +} enet_mib_tx_stat_t; + +/*! @brief Define the special configure for Rx and Tx controller*/ +typedef struct ENETSpecialMacConfig +{ + uint16_t rxMaxFrameLen; /*!< Receive maximum frame length*/ + uint16_t rxTruncLen; /*!< Receive truncate length, must be greater than or equal to maximum frame length*/ + uint16_t txInterPacketGap; /*!< Transmit inter-packet-gap*/ +} enet_special_maccfg_t; + +/*! @brief Defines the basic configuration structure for the ENET device.*/ +typedef struct ENETMacConfig +{ + enet_mac_operate_mode_t macMode; /*!< Mac Normal or sleep mode*/ + uint8_t *macAddr; /*!< MAC hardware address*/ + enet_config_rmii_t *rmiiCfgPtr;/*!< RMII configure mode*/ + uint32_t macCtlConfigure;/*!< Mac control configure, it is recommended to use enet_mac_control_flag_t + it is special control set for loop mode, sleep mode, crc forward/terminate etc*/ + enet_config_rx_fifo_t *rxFifoPtr; /*!< Receive FIFO configuration, if NULL default values will be used*/ + enet_config_tx_fifo_t *txFifoPtr; /*!< Transmit FIFO configuration, if NULL default values will be used*/ + uint8_t rxAccelerCfg; /*!< Receive accelerator configure, should be set when kEnetTxAccelEnable is set*/ + uint8_t txAccelerCfg; /*!< Transmit accelerator configure, should be set when kEnetRxAccelEnable is set*/ + uint16_t pauseDuration; /*!< Pause duration, should be set when kEnetRxFlowControlEnable is set*/ + enet_special_maccfg_t *macSpecialCfg; /*!< special configure for MAC to instead of default configure*/ +#if FSL_FEATURE_ENET_SUPPORT_PTP + bool isSlaveMode; /*!< PTP 1588 timer configuration*/ +#endif +} enet_mac_config_t; + +/*! @brief The configuration structure of buffer descriptor */ +typedef struct ENETBdConfig +{ + volatile enet_bd_struct_t *txBds; /*!< The start address of ENET transmit buffer descriptors. + This address must always be evenly divisible by 16. */ + uint8_t *txBuffer;/*!< The transmit data buffer start address. This address must + always be evenly divisible by 16. */ + uint32_t txBdNumber; /*!< The transmit buffer descriptor numbers. */ + uint32_t txBuffSizeAlign; /*!< The aligned transmit buffer size. */ + volatile enet_bd_struct_t *rxBds; /*!< The start address of ENET receive buffer descriptors. + This address must always be evenly divisible by 16. */ + uint8_t *rxBuffer; /*!< The receive data buffer start address. This address must + always be evenly divisible by 16. */ + uint32_t rxBdNumber; /*!< The receive buffer descriptor numbers. */ + uint32_t rxBuffSizeAlign; /*!< The aligned receive transmit buffer size. */ +} enet_bd_config; + +/* The mask to get MIB RX static event counter */ +#define ENET_GET_MIB_RX_STATIC_MASK (1 << 0) +/* The mask to get MIB TX static event counter */ +#define ENET_GET_MIB_TX_STATIC_MASK (1 << 1) +/* The mask to get TX pause frame status */ +#define ENET_GET_TX_PAUSE_MASK (1 << 2) +/* The mask to get RX pause frame status */ +#define ENET_GET_RX_PAUSE_MASK (1 << 3) +/* The mask to get the SMI interface configuration status */ +#define ENET_GET_SMI_CONFIG_MASK (1 << 4) +/* The mask to get MIB updating status */ +#define ENET_GET_MIB_UPDATE_MASK (1 << 5) +/* The mask to get max frame length */ +#define ENET_GET_MAX_FRAME_LEN_MASK (1 << 6) + +/* The status of the transmitted flow control frames + - 1 if the MAC is transmitting a MAC control PAUSE frame. + - 0 if No PAUSE frame transmit. */ +#define ENET_TX_PUASE_FLAG (1 << 0) +/* The status of the received flow control frames + - 1 if the flow control pause frame is received and the transmitter pauses + for the duration defined in this pause frame. + - 0 if there is no flow control frame received or the pause duration is complete.*/ +#define ENET_RX_PAUSE_FLAG (1 << 1) +/* The MII configuration status. + - 1 if the MII has been configured. + - 0 if the MII has not been configured. */ +#define ENET_SMI_CONFIG_FLAG (1 << 2) +/* The MIB updating status + - 1 if MIB is idle and MIB is not updating. + - 0 if MIB is updating */ +#define ENET_MIB_UPDATE_FLAG (1 << 3) + +/*! @brief The structure to save current status */ +typedef struct ENETCurStatus +{ + enet_mib_rx_stat_t rxStatic; /*!< The Rx static event counter */ + enet_mib_tx_stat_t txStatic; /*!< The Tx static event counter */ + uint16_t maxFrameLen; /*!< The max frame length */ + uint32_t statusFlags; /*!< The status flag */ +}enet_cur_status_t; + +/* Gets the control and the status region of the receive/transmit buffer descriptors. */ +#define ENET_BD_CTL_MASK (1 << 0) +/* Gets the extended control region of the transmit buffer descriptors. */ +#define ENET_RX_BD_EXT_CTL_MASK (1 << 1) +/* Gets the extended control region one of the receive buffer descriptor. */ +#define ENET_RX_BD_EXT_CTL1_MASK (1 << 2) +/* Gets the extended control region two of the receive buffer descriptor. */ +#define ENET_RX_BD_EXT_CTL2_MASK (1 << 3) +/* Gets the data length of the buffer descriptors. */ +#define ENET_BD_LEN_MASK (1 << 5) +/* Gets the timestamp of the buffer descriptors. */ +#define ENET_BD_TIMESTAMP_MASK (1 << 6) +/* Check if input buffer descriptor is the last one in the ring buffer */ +#define ENET_RX_BD_WRAP_FLAG_MASK (1 << 7) +/* Check if buffer descriptor empty flag is set. */ +#define ENET_RX_BD_EMPTY_FLAG_MASK (1 << 8) +/* Check if buffer descriptor truncate flag is set. */ +#define ENET_RX_BD_TRUNC_FLAG_MASK (1 << 9) +/* Check if buffer descriptor last flag is set. */ +#define ENET_RX_BD_LAST_FLAG_MASK (1 << 10) +/* Check if buffer descriptor ready flag is set. */ +#define ENET_TX_BD_READY_FLAG_MASK (1 << 11) +/* Check if buffer descriptor last flag is set. */ +#define ENET_TX_BD_LAST_FLAG_MASK (1 << 12) +/* Check if buffer descriptor wrap flag is set. */ +#define ENET_TX_BD_WRAP_FLAG_MASK (1 << 13) +/* Check if buffer descriptor Receive over run flag is set. */ +#define ENET_RX_BD_OVERRUN_FLAG_MASK (1 << 14) +/* Check if buffer descriptor Receive length violation flag is set. */ +#define ENET_RX_BD_LEN_VIOLAT_FLAG_MASK (1 << 15) +/* Check if buffer descriptor Receive non-octet aligned frame flag is set. */ +#define ENET_RX_BD_NO_OCTET_FLAG_MASK (1 << 16) +/* Check if buffer descriptor Receive crc error flag is set. */ +#define ENET_RX_BD_CRC_ERR_FLAG_MASK (1 << 17) +/* Check if buffer descriptor late collision frame discard flag is set. */ +#define ENET_RX_BD_COLLISION_FLAG_MASK (1 << 18) +/* Check if buffer descriptor TxErr flag is set. */ +#define ENET_TX_BD_TX_ERR_FLAG_MASK (1 << 19) +/* Check if buffer descriptor Transmit excess collision flag is set. */ +#define ENET_TX_BD_EXC_COL_FLAG_MASK (1 << 20) +/* Check if buffer descriptor Transmit late collision flag is set. */ +#define ENET_TX_BD_LATE_COL_FLAG_MASK (1 << 21) +/* Check if buffer descriptor Transmit underflow flag is set. */ +#define ENET_TX_BD_UNDERFLOW_FLAG_MASK (1 << 22) +/* Check if buffer descriptor Transmit overflow flag is set. */ +#define ENET_TX_BD_OVERFLOW_FLAG_MASK (1 << 23) +/* Check if buffer descriptor Transmit timestamp flag is set. */ +#define ENET_TX_BD_TIMESTAMP_FLAG_MASK (1 << 24) + +/* If input buffer descriptor is the last one, equals 1 */ +#define ENET_RX_BD_WRAP_FLAG (1 << 0) +/* If buffer descriptor empty flag is set, equals 1 */ +#define ENET_RX_BD_EMPTY_FLAG (1 << 1) +/* If buffer descriptor truncate flag is set, equals 1 */ +#define ENET_RX_BD_TRUNC_FLAG (1 << 2) +/* If buffer descriptor last flag is set, equals 1 */ +#define ENET_RX_BD_LAST_FLAG (1 << 3) +/* If buffer descriptor ready flag is set, equals 1 */ +#define ENET_TX_BD_READY_FLAG (1 << 4) +/* If buffer descriptor last flag is set, equals 1 */ +#define ENET_TX_BD_LAST_FLAG (1 << 5) +/* If buffer descriptor last flag is set, equals 1 */ +#define ENET_TX_BD_WRAP_FLAG (1 << 6) +/* If buffer descriptor Receive over run flag is set, equals 1 */ +#define ENET_RX_BD_OVERRUN_FLAG (1 << 7) +/* If buffer descriptor Receive length violation flag is set, equals 1 */ +#define ENET_RX_BD_LEN_VIOLAT_FLAG (1 << 8) +/* If buffer descriptor Receive non-octet aligned frame flag is set, equals 1 */ +#define ENET_RX_BD_NO_OCTET_FLAG (1 << 9) +/* If buffer descriptor Receive crc error flag is set, equals 1 */ +#define ENET_RX_BD_CRC_ERR_FLAG (1 << 10) +/* If buffer descriptor late collision frame discard flag is set, equals 1 */ +#define ENET_RX_BD_COLLISION_FLAG (1 << 11) +/* If buffer descriptor TxRrr flag is set, equals 1 */ +#define ENET_TX_BD_TX_ERR_FLAG (1 << 12) +/* If buffer descriptor Transmit excess collision flag is set, equals 1 */ +#define ENET_TX_BD_EXC_COL_ERR_FLAG (1 << 13) +/* If buffer descriptor Transmit late collision flag is set, equals 1 */ +#define ENET_TX_BD_LATE_COL_ERR_FLAG (1 << 14) +/* If buffer descriptor Transmit underflow flag is set, equals 1 */ +#define ENET_TX_BD_UNDERFLOW_ERR_FLAG (1 << 15) +/* If buffer descriptor Transmit overflow flag is set, equals 1 */ +#define ENET_TX_BD_OVERFLOW_FLAG (1 << 16) +/* If buffer descriptor Transmit timestamp flag is set, equals 1 */ +#define ENET_TX_BD_TIMESTAMP_FLAG (1 << 17) + +/*! @brief The buffer descriptor attribute */ +typedef struct EnetBdAttr +{ + uint16_t bdCtl; /*!< Buffer descriptor control field */ + uint16_t rxBdExtCtl; /*!< Buffer descriptor extend control field */ + uint16_t rxBdExtCtl1; /*!< Buffer descriptor extend control field 1 */ + uint16_t rxBdExtCtl2; /*!< Buffer descriptor extend control field 2 */ + uint16_t bdLen; /*!< Buffer descriptor data length field */ + uint32_t bdTimestamp; /*!< Buffer descriptor time stamp field */ + uint64_t flags; /*!< The status flag in the buffer descriptor */ +}enet_bd_attr_t; + +/*! @brief The action of mac which should be enabled dynamically */ +typedef enum EnetEnableDynamicalAct +{ + kEnGraceSendStop, /*!< Enable/disable mac to stop the sending process gracefully */ + kEnSendPauseFrame, /*!< Enable/disable mac to send the pause frame after current data frame is sent */ + kEnClearMibCounter, /*!< Enable/disable mac to clear the mib counter */ +}enet_en_dynamical_act_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initializes the ENET module to reset status. + * + * @param base The ENET peripheral base address. + * @return The status of the initialize operation. + * - false initialize failure. + * - true initialize success. + */ +enet_status_t ENET_HAL_Init(ENET_Type * base); + +/*! + * @brief Configures the ENET. + * + * @param base The ENET peripheral base address. + * @param macCfgPtr MAC controller related configuration. + * @param sysClk The system clock + * @param bufDespConfig buffer descriptor related configuration + */ +void ENET_HAL_Config(ENET_Type * base, const enet_mac_config_t *macCfgPtr, \ + const uint32_t sysClk, const enet_bd_config* bdConfig); + +/*! + * @brief Gets the ENET status. + * + * @param base The ENET peripheral base address. + * @param mask The mask represent which status user want to get. + * @param curStatus The structure to save the status result + */ +void ENET_HAL_GetStatus(ENET_Type * base, const uint32_t mask, enet_cur_status_t* curStatus); + +/*! + * @brief Sets the hardware addressing filtering to a multicast group address. + * + * This interface is used to add the ENET device to a multicast group address. + * After joining the group, Mac receives all frames with the group Mac address. + * + * @param base The ENET peripheral base address. + * @param crcValue The CRC value of the multicast group address. + * @param mode The operation for initialize/enable/disable the specified hardware address. + */ +void ENET_HAL_SetMulticastAddrHash(ENET_Type * base, uint32_t crcValue, enet_special_address_filter_t mode); + +/*! + * @brief Gets the attribute field value of buffer descriptor structure and flag + * status in the control field. + * + * @param curBd The ENET buffer descriptor address. + * @param mask The attribute mask represent which field user want to get. + * @param resultAttr the attribute value which is updated according to the mask value. + */ +void ENET_HAL_GetBufDescripAttr(volatile enet_bd_struct_t *curBd, const uint64_t mask, enet_bd_attr_t* resultAttr); + + /*! + * @brief Gets the buffer address of the buffer descriptors. + * + * @param curBd The current buffer descriptor. + * @return The buffer address of the buffer descriptor. + */ +uint8_t* ENET_HAL_GetBuffDescripData(volatile enet_bd_struct_t *curBd); + +/*! + * @brief Clears the receive buffer descriptor flag after it has been received or + * encountered some error in the receiving process. + * + * This interface mainly clears the status region and update the buffer pointer of + * the rx descriptor to a null buffer to ensure that the BD is correctly available + * to receive data. + * + * @param rxBds The current receive buffer descriptor. + * @param data The data buffer address. This address must be divided by 16 + * if the isbufferUpdate is set. + * @param isbufferUpdate The data buffer update flag. When you want to update + * the data buffer of the buffer descriptor ensure that this flag + * is set. + */ +void ENET_HAL_ClrRxBdAfterHandled(volatile enet_bd_struct_t *rxBds, uint8_t *data, bool isbufferUpdate); + +/*! + * @brief Sets the transmit buffer descriptor flag before sending a frame. + * + * This interface mainly clears the status region of TX buffer descriptor to + * ensure tat the BD is correctly available to send. + * You should set the isTxtsCfged when the transmit timestamp feature is required. + * + * @param txBds The current transmit buffer descriptor. + * @param length The data length on buffer descriptor. + * @param isTxtsCfged The timestamp configure flag. The timestamp is + * added to the transmit buffer descriptor when this flag is set. + * @param isTxCrcEnable The flag to transmit CRC sequence after the data byte. + * - True the transmit controller transmits the CRC sequence after the data byte. + * if the transmit CRC forward from application is disabled this flag should be set + * to add the CRC sequence. + * - False the transmit buffer descriptor does not transmit the CRC sequence after the data byte. + * if the transmit CRC forward from application. + * @param isLastOne The last BD flag in a frame. + * - True the last BD in a frame. + * - False not the last BD in a frame. + */ +void ENET_HAL_SetTxBdBeforeSend(volatile enet_bd_struct_t *txBds, uint16_t length, \ + bool isTxtsCfged, bool isTxCrcEnable, bool isLastOne); + +/*! + * @brief Clears the context in the transmit buffer descriptors. + * + * Clears the data, length, control, and status region of the transmit buffer descriptor. + * + * @param curBd The current buffer descriptor. + */ +static inline void ENET_HAL_ClrTxBdAfterSend(volatile enet_bd_struct_t *curBd) +{ + assert(curBd); + + curBd->length = 0; /* Set data length*/ + curBd->control &= (kEnetTxBdWrap);/* Set control */ + curBd->controlExtend1 = 0; +} + +/*! + * @brief Activates the receive buffer descriptor. + * + * The buffer descriptor activation + * should be done after the ENET module is enabled. Otherwise, the activation fails. + * + * @param base The ENET peripheral base address. + */ + static inline void ENET_HAL_SetRxBdActive(ENET_Type * base) +{ + ENET_SET_RDAR(base, ENET_RDAR_RDAR_MASK); +} + +/*! + * @brief Activates the transmit buffer descriptor. + * + * The buffer descriptor activation should be done after the ENET module is + * enabled. Otherwise, the activation fails. + * + * @param base The ENET peripheral base address. + */ +static inline void ENET_HAL_SetTxBdActive(ENET_Type * base) +{ + ENET_SET_TDAR(base, ENET_TDAR_TDAR_MASK); +} + +/*! + * @brief Configures the (R)MII data interface of ENET. + * + * @param base The ENET peripheral base address. + * @param rmiiCfgPtr The RMII/MII configuration structure pointer. + */ +void ENET_HAL_SetRMIIMode(ENET_Type * base, enet_config_rmii_t *rmiiCfgPtr); + +/*! + * @brief Reads data from PHY. + * + * @param base The ENET peripheral base address. + * @return The data read from PHY + */ +static inline uint32_t ENET_HAL_GetSMIData(ENET_Type * base) +{ + return (uint32_t)ENET_BRD_MMFR_DATA(base); +} + +/*! + * @brief Sets the SMI(serial Management interface) read command. + * + * @param base The ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param operation The read operation. + */ +void ENET_HAL_SetSMIRead(ENET_Type * base, uint32_t phyAddr, uint32_t phyReg, enet_mii_read_t operation); + +/*! + * @brief Sets the SMI(serial Management interface) write command. + * + * @param base The ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param operation The write operation. + * @param data The data written to PHY. + */ +void ENET_HAL_SetSMIWrite(ENET_Type * base, uint32_t phyAddr, uint32_t phyReg, enet_mii_write_t operation, uint32_t data); + +/*! + * @brief Enables/disables the MAC dynamical action. + * + * @param base The ENET peripheral base address. + * @param action The action which will be enabled/disabled. + * @param enable The switch to enable/disable the action of the MAC. + */ +void ENET_HAL_EnDynamicalAct(ENET_Type * base, enet_en_dynamical_act_t action, bool enable); + +/*! + * @brief Enables the ENET module. + * + * @param base The ENET peripheral base address. + */ +static inline void ENET_HAL_Enable(ENET_Type * base) +{ + ENET_SET_ECR(base, ENET_ECR_ETHEREN_MASK); /* Enable Ethernet module*/ + +#if (!FSL_FEATURE_ENET_DMA_BIG_ENDIAN_ONLY) + ENET_BWR_ECR_DBSWP(base,1); /* buffer descriptor byte swapping for little-endian system and endianness configurable IP*/ +#endif +} + +/*! + * @brief Disables the ENET module. + * + * @param base The ENET peripheral base address. + */ +static inline void ENET_HAL_Disable(ENET_Type * base) +{ + ENET_CLR_ECR(base, ENET_ECR_ETHEREN_MASK); /* Disable Ethernet module*/ +} + +/*! + * @brief Enables/Disables the ENET interrupt. + * + * @param base The ENET peripheral base address. + * @param source The interrupt sources. + * @param enable The interrupt enable switch. + */ +void ENET_HAL_SetIntMode(ENET_Type * base, enet_interrupt_request_t source, bool enable); + +/*! + * @brief Clears ENET interrupt events. + * + * @param base The ENET peripheral base address. + * @param source The interrupt source to be cleared. enet_interrupt_request_t + * enum types is recommended as the interrupt source. + */ +static inline void ENET_HAL_ClearIntStatusFlag(ENET_Type * base, enet_interrupt_request_t source) +{ + ENET_WR_EIR(base,source); +} + +/*! + * @brief Gets the ENET interrupt status. + * + * @param base The ENET peripheral base address. + * @param source The interrupt sources. enet_interrupt_request_t + * enum types is recommended as the interrupt source. + * @return The event status of the interrupt source + * - true if the interrupt event happened. + * - false if the interrupt event has not happened. + */ +static inline bool ENET_HAL_GetIntStatusFlag(ENET_Type * base, enet_interrupt_request_t source) +{ + return ((ENET_RD_EIR(base) & (uint32_t)source) != 0); +} + +/*! + * @brief Configures the 1588 timer and run the 1588 timer. + * + * This interface configures the 1588 timer and starts the 1588 timer. + * After the timer starts the 1588 timer starts incrementing. + * + * @param base The ENET peripheral base address. + * @param ptpCfgPtr The 1588 timer configuration structure pointer. + */ +void ENET_HAL_Start1588Timer(ENET_Type * base, enet_config_ptp_timer_t * ptpCfgPtr); + +/*! + * @brief Stop the 1588 timer. + * + * This interface stop the 1588 timer and clear its count value. + * + * @param base The ENET peripheral base address. + */ +void ENET_HAL_Stop1588Timer(ENET_Type * base); + +/*! + * @brief Adjusts the 1588 timer. + * + * Adjust the 1588 timer according to the increase and correction period + * of the configured correction. + * + * @param base The ENET peripheral base address. + * @param increaseCorrection The increase correction for 1588 timer. + * @param periodCorrection The period correction for 1588 timer. + */ +static inline void ENET_HAL_Adjust1588Timer(ENET_Type * base, uint32_t increaseCorrection, uint32_t periodCorrection) +{ + assert(increaseCorrection <= ENET_ATINC_INC_MASK); + assert(periodCorrection <= ENET_ATCOR_COR_MASK); + /* Set correction for PTP timer increment*/ + ENET_BWR_ATINC_INC_CORR(base, increaseCorrection); + /* Set correction for PTP timer period*/ + ENET_BWR_ATCOR_COR(base, periodCorrection); +} + +/*! + * @brief Sets the 1588 timer. + * + * @param base The ENET peripheral base address. + * @param nanSecond The nanosecond set to 1588 timer. + */ +static inline void ENET_HAL_Set1588TimerNewTime(ENET_Type * base, uint32_t nanSecond) +{ + ENET_WR_ATVR(base,nanSecond); +} + +/*! + * @brief Gets the time from the 1588 timer. + * + * Sets the capture command to the 1588 timer is used before reading the current + * time register.After set timer capture, please wait for about 1us before read + * the captured timer. + * @param base The ENET peripheral base address. + * @return the current time from 1588 timer. + */ +static inline uint32_t ENET_HAL_Get1588TimerCurrentTime(ENET_Type * base) +{ + ENET_SET_ATCR(base, ENET_ATCR_CAPTURE_MASK); + /*Bug of IC need repeat*/ + ENET_SET_ATCR(base, ENET_ATCR_CAPTURE_MASK); + return ENET_RD_ATVR(base); +} + +/*! + * @brief Gets the 1588 timer channel status. + * + * @param base The ENET peripheral base address. + * @param channel The 1588 timer channel number. + * @return Compare or capture operation status + * - True if the compare or capture has occurred. + * - False if the compare or capture has not occurred. + */ +static inline bool ENET_HAL_Get1588TimerChnStatus(ENET_Type * base, enet_timer_channel_t channel) +{ + return ENET_BRD_TCSR_TF(base,channel); +} + +/*! + * @brief Resets the 1588 timer compare value and clears the 1588 timer channel interrupt flag. + * + * @param base The ENET peripheral base address. + * @param channel The 1588 timer channel number. + * @param compareValue Compare value for 1588 timer channel. + */ +static inline void ENET_HAL_Rst1588TimerCmpValAndClrFlag(ENET_Type * base, enet_timer_channel_t channel, uint32_t compareValue) +{ + ENET_WR_TCCR(base, channel, compareValue); + ENET_SET_TCSR(base, channel, ENET_TCSR_TF_MASK);/* clear interrupt flag*/ + ENET_WR_TGSR(base,(1U << channel)); /* clear channel flag*/ +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ +#endif +#endif /*!< __FSL_ENET_HAL_H__*/ + +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_ewm_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_ewm_hal.h new file mode 100755 index 0000000..e9c747f --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_ewm_hal.h @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_EWM_HAL_H__ +#define __FSL_EWM_HAL_H__ + +#include <assert.h> +#include <stdint.h> +#include <stdbool.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_EWM_COUNT + +/*! + * @addtogroup ewm_hal + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ +/*! + * @brief Data structure for EWM initialize + * + * This structure is used when initializing the EWM. + * @internal gui name="Basic configuration" id="ewmCfg" + */ +typedef struct _ewm_config +{ + bool ewmEnable; /*!< Enable EWM module @internal gui name="Enable EWM module" id="EnableModule" */ + bool ewmInEnable; /*!< Enable EWM_in input enable @internal gui name="EWM_in input" id="Input" */ + bool ewmInAssertLogic; /*!< Set EWM_in signal assertion state @internal gui name="EWM_in signal assertion" id="Assertion" */ + bool intEnable; /*!< Enable EWM interrupt enable @internal gui name="EWM interrupt" id="Interrupt" */ +#if FSL_FEATURE_EWM_HAS_PRESCALER + uint8_t ewmPrescalerValue; /*!< Set EWM prescaler value @internal gui name="Prescaler" id="Prescaler" */ +#endif + uint8_t ewmCmpLowValue; /*!< Set EWM compare low register value @internal gui name="Compare low register value" id="LowValue" */ + uint8_t ewmCmpHighValue; /*!< Set EWM compare high register value, the maximum value should be 0xfe otherwise the counter will never expire @internal gui name="Compare high register value" id="HighValue" */ +}ewm_config_t; + +/*! @brief ewm status return codes.*/ +typedef enum _ewm_status { + kStatus_EWM_Success = 0x0U, /*!< EWM operation Succeed */ + kStatus_EWM_Fail = 0x01, /*!< EWM operation Failed */ + kStatus_EWM_NotInitlialized = 0x2U, /*!< EWM is not initialized yet */ + kStatus_EWM_NullArgument = 0x3U, /*!< Argument is NULL */ +}ewm_status_t; + +/******************************************************************************* + ** Variables + *******************************************************************************/ + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Enable the EWM. + * + * This function checks whether the EWM is enabled. + * + * @param base The EWM peripheral base address + */ +static inline void EWM_HAL_Enable(EWM_Type * base) +{ + EWM_BWR_CTRL_EWMEN(base, 1U); +} + +/*! + * @brief Enable the EWM. + * + * This function checks whether the EWM is enabled. + * + * @param base The EWM peripheral base address + */ +static inline void EWM_HAL_Disable(EWM_Type * base) +{ + EWM_BWR_CTRL_EWMEN(base, 0U); +} + +/*! + * @brief Checks whether the EWM is enabled. + * + * This function checks whether the EWM is enabled. + * + * @param base The EWM peripheral base address + * @return State of the module + * @retval false means EWM is disabled + * @retval true means WODG is enabled + */ +static inline bool EWM_HAL_IsEnable(EWM_Type * base) +{ + return ((bool)EWM_BRD_CTRL_EWMEN(base)); +} + +/*! + * @brief Enable/Disable EWM interrupt. + * + * This function sets EWM enable/disable. + * + * @param base The EWM peripheral base address + * @param enable Set EWM interrupt enable/disable + */ +static inline void EWM_HAL_SetIntCmd(EWM_Type * base, bool enable) +{ + EWM_BWR_CTRL_INTEN(base, enable); +} + +/*! + * @brief Set EWM compare low register value. + * + * This function sets EWM compare low register value and defines the minimum cycles to service EWM, + * when counter value is greater than or equal to ewm compare low register value, refresh EWM can be successful, + * and this register is write once, one more write will cause bus fault. + * + * @param base The EWM peripheral base address + * @param minServiceCycles The EWM compare low register value + */ +static inline void EWM_HAL_SetCmpLowRegValue(EWM_Type * base, uint8_t minServiceCycles) +{ + EWM_WR_CMPL(base, minServiceCycles); +} + +/*! + * @brief Set EWM compare high register value. + * + * This function sets EWM compare high register value and defines the maximum cycles to service EWM, + * when counter value is less than or equal to ewm compare high register value, refresh EWM can be successful, + * the compare high register value must be greater than compare low register value, + * and this register is write once, one more write will cause bus fault. + * + * @param base The EWM peripheral base address + * @param maxServiceCycles The EWM compare low register value + */ +static inline void EWM_HAL_SetCmpHighRegValue(EWM_Type * base, uint8_t maxServiceCycles) +{ + EWM_WR_CMPH(base, maxServiceCycles); +} + +/*! + * @brief Service EWM. + * + * This function reset EWM counter to zero and + * the period of writing the frist value and the second value should be within 15 bus cycles. + * + * @param base The EWM peripheral base address +*/ +static inline void EWM_HAL_Refresh(EWM_Type * base) +{ + EWM_WR_SERV(base, (uint8_t)0xB4U); + EWM_WR_SERV(base, (uint8_t)0x2CU); +} + +/*! + * @brief Config EWM control register. + * + * This function configures EWM control register, + * EWM enable bitfeild, EWM ASSIN bitfeild and EWM INPUT enable bitfeild are WRITE ONCE, one more write will cause bus fault. + * + * @param base The EWM peripheral base address + * @param ewmConfigPtr config EWM CTRL register + */ +void EWM_HAL_SetConfig(EWM_Type * base, const ewm_config_t *ewmConfigPtr); + +/*! + * @brief Restores the EWM module to reset value. + * + * This function restores the EWM module to reset value. + * + * @param base The EWM peripheral base address + */ +void EWM_HAL_Init(EWM_Type * base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif +#endif /* __FSL_EWM_HAL_H__*/ +/******************************************************************************* + * EOF + *******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_flexbus_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_flexbus_hal.h new file mode 100755 index 0000000..69bfb90 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_flexbus_hal.h @@ -0,0 +1,659 @@ +/* + * Copyright (c) 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_FLEXBUS_HAL_H__ +#define __FSL_FLEXBUS_HAL_H__ + +#include <assert.h> +#include <stdint.h> +#include <stdbool.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_FB_COUNT + +/*! + * @addtogroup flexbus_hal + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Flexbus status return codes.*/ +typedef enum _flexbus_status +{ + kStatus_FLEXBUS_Success = 0x00U, + kStatus_FLEXBUS_OutOfRange, + kStatus_FLEXBUS_InvalidArgument, + kStatus_FLEXBUS_Failed, +} flexbus_status_t; + +/*! @brief Defines port size for Flexbus peripheral.*/ +typedef enum _flexbus_port_size +{ + kFlexbus4bytes = 0x00U, /*!< 32-bit port size */ + kFlexbus1byte = 0x01U, /*!< 8-bit port size */ + kFlexbus2bytes = 0x02U /*!< 16-bit port size */ +} flexbus_port_size_t; + +/*! @brief Defines number of cycles to hold address and attributes for Flexbus peripheral.*/ +typedef enum _flexbus_write_address_hold +{ + kFlexbusHold1cycle = 0x00U, /*!< Hold address and attributes one cycle after FB_CSn negates on writes. @internal gui name="One cycle" */ + kFlexbusHold2cycles = 0x01U, /*!< Hold address and attributes two cycle after FB_CSn negates on writes. @internal gui name="Two cycle" */ + kFlexbusHold3cycles = 0x02U, /*!< Hold address and attributes three cycle after FB_CSn negates on writes. @internal gui name="Three cycle" */ + kFlexbusHold4cycles = 0x03U /*!< Hold address and attributes four cycle after FB_CSn negates on writes. @internal gui name="Four cycle" */ +} flexbus_write_address_hold_t; + + +/*! @brief Defines number of cycles to hold address and attributes for Flexbus peripheral.*/ +typedef enum _flexbus_read_address_hold +{ + kFlexbusHold4or3cycles = 0x03U, /*!< Hold address and attributes 4 or 3 cycles on reads. @internal gui name="4 or 3 cycles" */ + kFlexbusHold3or2cycles = 0x02U, /*!< Hold address and attributes 3 or 2 cycles on reads. @internal gui name="3 or 2 cycles" */ + kFlexbusHold2or1cycle = 0x01U, /*!< Hold address and attributes 2 or 1 cycles on reads. @internal gui name="2 or 1 cycles" */ + kFlexbusHold1or0cycle = 0x00U /*!< Hold address and attributes 1 or 0 cycles on reads. @internal gui name="1 or 0 cycles" */ +} flexbus_read_address_hold_t; + + +/*! @brief Address setup for Flexbus peripheral.*/ +typedef enum _flexbus_address_setup +{ + kFlexbusFirstRisingEdge = 0x00U, /*!< Assert FB_CSn on first rising clock edge after address is asserted. @internal gui name="First rising clock edge" */ + kFlexbusSecondRisingEdge = 0x01U, /*!< Assert FB_CSn on second rising clock edge after address is asserted. @internal gui name="Second rising clock edge" */ + kFlexbusThirdRisingEdge = 0x02U, /*!< Assert FB_CSn on third rising clock edge after address is asserted. @internal gui name="Third rising clock edge" */ + kFlexbusFourthRisingEdge = 0x03U, /*!< Assert FB_CSn on fourth rising clock edge after address is asserted. @internal gui name="Fourth rising clock edge" */ +} flexbus_address_setup_t; + +/*! @brief Defines byte-lane shift for Flexbus peripheral.*/ +typedef enum _flexbus_bytelane_shift +{ + kFlexbusNotShifted = 0x00U, /*!< Not shifted. Data is left-justfied on FB_AD. @internal gui name="Not shifted" */ + kFlexbusShifted = 0x01U, /*!< Shifted. Data is right justified on FB_AD. @internal gui name="Shifted" */ +} flexbus_bytelane_shift_t; + +/*! @brief Defines multiplex group1 valid signals.*/ +typedef enum _flexbus_multiplex_group1_signal +{ + kFlexbusMultiplexGroup1_FB_ALE = 0x00U, /*!< FB_ALE */ + kFlexbusMultiplexGroup1_FB_CS1 = 0x01U, /*!< FB_CS1 */ + kFlexbusMultiplexGroup1_FB_TS = 0x02U, /*!< FB_TS */ +} flexbus_multiplex_group1_t; + +/*! @brief Defines multiplex group2 valid signals.*/ +typedef enum _flexbus_multiplex_group2_signal +{ + kFlexbusMultiplexGroup2_FB_CS4 = 0x00U, /*!< FB_CS4 */ + kFlexbusMultiplexGroup2_FB_TSIZ0 = 0x01U, /*!< FB_TSIZ0 */ + kFlexbusMultiplexGroup2_FB_BE_31_24 = 0x02U, /*!< FB_BE_31_24 */ +} flexbus_multiplex_group2_t; + +/*! @brief Defines multiplex group3 valid signals.*/ +typedef enum _flexbus_multiplex_group3_signal +{ + kFlexbusMultiplexGroup3_FB_CS5 = 0x00U, /*!< FB_CS5 */ + kFlexbusMultiplexGroup3_FB_TSIZ1 = 0x01U, /*!< FB_TSIZ1 */ + kFlexbusMultiplexGroup3_FB_BE_23_16 = 0x02U, /*!< FB_BE_23_16 */ +} flexbus_multiplex_group3_t; + +/*! @brief Defines multiplex group4 valid signals.*/ +typedef enum _flexbus_multiplex_group4_signal +{ + kFlexbusMultiplexGroup4_FB_TBST = 0x00U, /*!< FB_TBST */ + kFlexbusMultiplexGroup4_FB_CS2 = 0x01U, /*!< FB_CS2 */ + kFlexbusMultiplexGroup4_FB_BE_15_8 = 0x02U, /*!< FB_BE_15_8 */ +} flexbus_multiplex_group4_t; + +/*! @brief Defines multiplex group5 valid signals.*/ +typedef enum _flexbus_multiplex_group5_signal +{ + kFlexbusMultiplexGroup5_FB_TA = 0x00U, /*!< FB_TA */ + kFlexbusMultiplexGroup5_FB_CS3 = 0x01U, /*!< FB_CS3 */ + kFlexbusMultiplexGroup5_FB_BE_7_0 = 0x02U, /*!< FB_BE_7_0 */ +} flexbus_multiplex_group5_t; + +/*! @brief Configuration structure that the user needs to set + * @internal gui name="FlexBus configuration" id="fbCfg" + */ +typedef struct _flexbus_user_config { + uint8_t chip; /*!< Chip FlexBus for validation @internal gui name="Chip" */ + uint8_t waitStates; /*!< Value of wait states @internal gui name="WaitStates" */ + uint32_t baseAddress; /*!< Base address for using FlexBus @internal gui name="Base address" */ + uint32_t baseAddressMask; /*!< Base address mask @internal gui name="Base address mask" */ + bool writeProtect; /*!< Write protected @internal gui name="Write protect" */ + bool burstWrite; /*!< Burst-Write enable @internal gui name="Burst write" */ + bool burstRead; /*!< Burst-Read enable @internal gui name="Burst read" */ + bool byteEnableMode; /*!< Byte-enable mode support @internal gui name="Byte-enable mode" */ + bool autoAcknowledge; /*!< Auto acknowledge setting @internal gui name="Auto ACK" */ + bool extendTransferAddress; /*!< Extend transfer start/extend address latch enable @internal gui name="Address latch enable" */ + bool secondaryWaitStates; /*!< Secondary wait states number @internal gui name="Secondary wait states" */ + flexbus_port_size_t portSize; /*!< Port size of transfer @internal gui name="Port size" */ + flexbus_bytelane_shift_t byteLaneShift; /*!< Byte-lane shift enable @internal gui name="Byte-lane shift" */ + flexbus_write_address_hold_t writeAddressHold; /*!< Write address hold or deselect option @internal gui name="Write address hold" */ + flexbus_read_address_hold_t readAddressHold; /*!< Read address hold or deselect option @internal gui name="Read address hold" */ + flexbus_address_setup_t addressSetup; /*!< Address setup setting @internal gui name="Address setup" */ + flexbus_multiplex_group1_t group1MultiplexControl; /*!< FlexBus Signal Group 1 Multiplex control @internal gui name="Signal Multiplex Group 1" */ + flexbus_multiplex_group2_t group2MultiplexControl; /*!< FlexBus Signal Group 2 Multiplex control @internal gui name="Signal Multiplex Group 2"*/ + flexbus_multiplex_group3_t group3MultiplexControl; /*!< FlexBus Signal Group 3 Multiplex control @internal gui name="Signal Multiplex Group 3" */ + flexbus_multiplex_group4_t group4MultiplexControl; /*!< FlexBus Signal Group 4 Multiplex control @internal gui name="Signal Multiplex Group 4" */ + flexbus_multiplex_group5_t group5MultiplexControl; /*!< FlexBus Signal Group 5 Multiplex control @internal gui name="Signal Multiplex Group 5" */ +} flexbus_user_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Configuration + * @{ + */ + +/*! + * @brief Initialization to default values. + * + * Only chip 0 validated and set to known values. Other chips disabled. + * + * @param base Flexbus module base number. +*/ +void FLEXBUS_HAL_Init(FB_Type* base); + +/*! + * @brief Configure to a known values. + * + * @param base Flexbus module base number. + * @param userConfigPtr Flexbus input user configuration +*/ +void FLEXBUS_HAL_Configure(FB_Type* base, const flexbus_user_config_t* userConfigPtr); + +/*! + * @brief Write chip-select base address. + * + * The CSARn registers specify the chip-select base addresses. + * NOTE: Because the FlexBus module is one of the slaves connected to the crossbar switch, it is only + * accessible within a certain memory range. Refer to the device memory map for the applicable + * FlexBus "expansion" address range for which the chip-selects can be active. Set the CSARn + * registers appropriately. + * + * @param base Flexbus module base number. + * @param chip Flexbus chip for validation. + * @param addr chip-select base address. + * @param addrMask chip-select base address mask. +*/ +static inline void FLEXBUS_HAL_WriteAddr(FB_Type* base, uint8_t chip, uint16_t addr, uint16_t addrMask) +{ + assert(chip < FB_CSAR_COUNT); + FB_BWR_CSAR_BA(base, chip, addr); + FB_BWR_CSMR_BAM(base, chip, addrMask); +} + +/*! + * @brief Sets chip-selects valid bit or not. + * + * Indicates whether the corresponding CSAR, CSMR, and CSCR contents are valid. + * NOTE: At reset, no chip-select other than FB_CS0 can be used until the CSMR0[V] + * is set. Afterward, FB_CS[5:0] functions as programmed. + * + * @param base Flexbus module base number. + * @param chip Flexbus chip for validation. + * @param valid Validation for chip-selects or not. + * - true: chip-select is valid + * - false: chip-select is invalid +*/ +static inline void FLEXBUS_HAL_SetChipSelectValidCmd(FB_Type* base, uint8_t chip, bool valid) +{ + assert(chip < FB_CSMR_COUNT); + FB_BWR_CSMR_V(base, chip, valid); +} + +/*! + * @brief Enables or disables write protection function for Flexbus. + * + * Controls write accesses to the address range in the corresponding CSAR. + * 0: Read and write accesses are allowed + * 1: Only read accesses are allowed + * + * @param base Flexbus module base number. + * @param chip Flexbus chip for validation. + * @param enable Enables or disables write protection. +*/ +static inline void FLEXBUS_HAL_SetWriteProtectionCmd(FB_Type* base, uint8_t chip, bool enable) +{ + assert(chip < FB_CSMR_COUNT); + FB_BWR_CSMR_WP(base, chip, enable); +} + +/*! + * @brief Enables or disables burst-write on Flexbus. + * + * Specifies whether burst writes are used for memory associated with each FB_CSn. + * + * 0: Break data larger than the specified port size into individual, port-sized, + * non-burst writes. For example, a longword write to an 8-bit port takes four + * byte writes. + * 1: Enables burst write of data larger than the specified port size, including + * longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line + * writes to 8-, 16-, and 32-bit ports. + * + * @param base Flexbus module base number. + * @param chip Flexbus chip for validation. + * @param enable Enables or disables burst-write. +*/ +static inline void FLEXBUS_HAL_SetBurstWriteCmd(FB_Type* base, uint8_t chip, bool enable) +{ + assert(chip < FB_CSCR_COUNT); + FB_BWR_CSCR_BSTW(base, chip, enable); +} + +/*! + * @brief Enables or disables burst-read bit on Flexbus. + * + * Specifies whether burst reads are used for memory associated with each FB_CSn. + * + * 0: Data exceeding the specified port size is broken into individual, port-sized, + * non-burst reads. For example, a longword read from an 8-bit port is broken into + * four 8-bit reads. + * 1: Enables data burst reads larger than the specified port size, including longword + * reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8, + * 16-, and 32-bit ports. + * + * @param base Flexbus module base number. + * @param chip Flexbus chip for validation. + * @param enable Enables or disables burst-read. +*/ +static inline void FLEXBUS_HAL_SetBurstReadCmd(FB_Type* base, uint8_t chip, bool enable) +{ + assert(chip < FB_CSCR_COUNT); + FB_BWR_CSCR_BSTR(base, chip, enable); +} + +/*! + * @brief Enables or disables byte-enable support on Flexbus. + * + * Specifies the byte enable operation. Certain memories have byte enables that must + * be asserted during reads and writes. BEM can be set in the relevant CSCR to provide + * the appropriate mode of byte enable support for these SRAMs. + * + * The FB_BEn signals are asserted for read and write accesses. + * + * @param base Flexbus module base number. + * @param chip Flexbus chip for validation. + * @param enable Enables or disables byte-enable support +*/ +static inline void FLEXBUS_HAL_SetByteModeCmd(FB_Type* base, uint8_t chip, bool enable) +{ + assert(chip < FB_CSCR_COUNT); + FB_BWR_CSCR_BEM(base, chip, enable); +} + +/*! + * @brief Sets port size on Flexbus. + * + * Specifies the data port width associated with each chip-select. It determines where + * data is driven during write cycles and where data is sampled during read cycles. + * + * @param base Flexbus module base number. + * @param chip Flexbus chip for validation. + * @param size Size of port. +*/ +static inline void FLEXBUS_HAL_SetPortSize(FB_Type* base, uint8_t chip, flexbus_port_size_t size) +{ + assert(chip < FB_CSCR_COUNT); + FB_BWR_CSCR_PS(base, chip, size); +} + +/*! + * @brief Enables auto-acknowledge on Flexbus. + * + * Determines the assertion of the internal transfer acknowledge for accesses specified by the + * chip-select address. + * + * NOTE: If AA is set for a corresponding FB_CSn and the external system asserts an external FB_TA + * before the wait-state countdown asserts the internal FB_TA, the cycle is terminated. Burst cycles + * increment the address bus between each internal termination. + * NOTE: This bit must be set if CSPMCR disables FB_TA. + * + * enable value: + * 0: No internal FB_TA is asserted. Cycle is terminated externally + * 1: Internal transfer acknowledge is asserted as specified by WS + * + * @param base Flexbus module base number. + * @param chip Flexbus chip for validation. + * @param enable Enables or disables Auto-acknowledge. +*/ +static inline void FLEXBUS_HAL_SetAutoAcknowledgeCmd(FB_Type* base, uint8_t chip, bool enable) +{ + assert(chip < FB_CSCR_COUNT); + FB_BWR_CSCR_AA(base, chip, enable); +} + +/*! + * @brief Enables byte-lane shift on Flexbus. + * + * Determines if data on FB_AD appears left-justified or right-justified during the data phase + * of a FlexBus access. + * + * 0: Not shifted. Data is left-justfied on FB_AD. + * 1: Shifted. Data is right justified on FB_AD. + * + * @param base Flexbus module base number. + * @param chip Flexbus chip for validation. + * @param shift Selects left-justified or right-justified data +*/ +static inline void FLEXBUS_HAL_SetByteLaneShift(FB_Type* base, uint8_t chip, flexbus_bytelane_shift_t shift) +{ + assert(chip < FB_CSCR_COUNT); + FB_BWR_CSCR_BLS(base, chip, shift); +} + +/*! + * @brief Sets number of wait states on Flexbus. + * + * The number of wait states inserted after FB_CSn asserts and before an internal transfer + * acknowledge is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63 wait states). + * + * @param base Flexbus module base number. + * @param chip Flexbus chip for validation. + * @param waitStates Defines value of wait states +*/ +static inline void FLEXBUS_HAL_SetWaitStates(FB_Type* base, uint8_t chip, uint8_t waitStates) +{ + assert(chip < FB_CSCR_COUNT); + assert(waitStates <= 0x3F); + FB_BWR_CSCR_WS(base, chip, waitStates); +} + +/*! + * @brief Sets write address hold or deselect. + * + * Write address hold or deselect. This field controls the address, data, and attribute hold time + * after the termination of a write cycle that hits in the chip-select address space. + * NOTE: The hold time applies only at the end of a transfer. Therefore, during a burst transfer + * or a transfer to a port size smaller than the transfer size, the hold time is only added after + * the last bus cycle. + * + * @param base Flexbus module base number. + * @param chip Flexbus chip for validation. + * @param addrHold Value of cycles to hold write address. +*/ +static inline void FLEXBUS_HAL_SetWriteAddrHoldOrDeselect(FB_Type* base, uint8_t chip, flexbus_write_address_hold_t addrHold) +{ + assert(chip < FB_CSCR_COUNT); + FB_BWR_CSCR_WRAH(base, chip, addrHold); +} + +/*! + * @brief Sets read address hold or deselect. + * + * This field controls the address and attribute hold time after the termination during a read cycle + * that hits in the chip-select address space. + * NOTE: The hold time applies only at the end of a transfer. Therefore, during a burst transfer + * or a transfer to a port size smaller than the transfer size, the hold time is only added after + * the last bus cycle. + * + * @param base Flexbus module base number. + * @param chip Flexbus chip for validation. + * @param addrHold Value of cycles to hold read address. +*/ +static inline void FLEXBUS_HAL_SetReadAddrHoldOrDeselect(FB_Type* base, uint8_t chip, flexbus_read_address_hold_t addrHold) +{ + assert(chip < FB_CSCR_COUNT); + FB_BWR_CSCR_RDAH(base, chip, addrHold); +} + +/*! + * @brief Set address setup + * + * Controls the assertion of the chip-select with respect to assertion of a valid address and + * attributes. The address and attributes are considered valid at the same time FB_TS/FB_ALE asserts. + * + * @param base Flexbus module base number. + * @param chip Flexbus chip for validation. + * @param delay Value of delay. +*/ +static inline void FLEXBUS_HAL_SetAddrSetup(FB_Type* base, uint8_t chip, flexbus_address_setup_t delay) +{ + assert(chip < FB_CSCR_COUNT); + FB_BWR_CSCR_ASET(base, chip, delay); +} + +/*! + * @brief Enables extended address latch. + * + * Extended address latch enable + * + * 0: FB_TS/FB_ALE asserts for one bus clock cycle. + * 1: FB_TS/FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts. + * + * @param base Flexbus module base number. + * @param chip Flexbus chip for validation. + * @param enable Enables or disables extended address latch. +*/ +static inline void FLEXBUS_HAL_SetExtendedAddrLatchCmd(FB_Type* base, uint8_t chip, bool enable) +{ + assert(chip < FB_CSCR_COUNT); + FB_BWR_CSCR_EXTS(base, chip, enable); +} + +/*! + * @brief Enables secondary wait state. + * + * Secondary wait state enable. + * + * 0: The WS value inserts wait states before an internal transfer acknowledge is generated + * for all transfers. + * 1: The SWS value inserts wait states before an internal transfer acknowledge is generated + * for burst transfer secondary terminations. + * + * @param base Flexbus module base number. + * @param chip Flexbus chip for validation. + * @param enable Enables or disables wait state +*/ +static inline void FLEXBUS_HAL_SetSecondaryWaitStateCmd(FB_Type* base, uint8_t chip, bool enable) +{ + assert(chip < FB_CSCR_COUNT); + FB_BWR_CSCR_SWSEN(base, chip, enable); +} + +/*! + * @brief Multiplex group1 set + * + * GROUP1 Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals. + * + * @param base Flexbus module base number. + * @param controls Flexbus multiplex settings for Group1. + * + * @return Flexbus status. +*/ +static inline void FLEXBUS_HAL_SetMultiplexControlGroup1(FB_Type* base, flexbus_multiplex_group1_t controls) +{ + FB_BWR_CSPMCR_GROUP1(base, controls); +} + +/*! + * @brief Multiplex group1 get + * + * GROUP1 Controls the multiplexing of the FB_ALE, FB_CS1 , and FB_TS signals. + * + * @param base Flexbus module base number. + * + * @return Flexbus multiplex settings for Group1. +*/ +static inline flexbus_multiplex_group1_t FLEXBUS_HAL_GetMultiplexControlGroup1(FB_Type* base) +{ + return (flexbus_multiplex_group1_t)FB_BRD_CSPMCR_GROUP1(base); +} + +/*! + * @brief Multiplex group2 set + * + * GROUP2 Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When + * GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the + * bus hangs during a transfer. + * + * @param base Flexbus module base number. + * @param controls Flexbus multiplex settings for Group2. + * + * @return Flexbus status. + * +*/ +static inline void FLEXBUS_HAL_SetMultiplexControlGroup2(FB_Type* base, flexbus_multiplex_group2_t controls) +{ + FB_BWR_CSPMCR_GROUP2(base, controls); +} + +/*! + * @brief Multiplex group2 get + * + * GROUP2 Controls the multiplexing of the FB_TA , FB_CS3 , and FB_BE_7_0 signals. When + * GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the + * bus hangs during a transfer. + * + * @param base Flexbus module base number. + * + * @return Flexbus multiplex settings for Group2. +*/ +static inline flexbus_multiplex_group2_t FLEXBUS_HAL_GetMultiplexControlGroup2(FB_Type* base) +{ + return (flexbus_multiplex_group2_t)FB_BRD_CSPMCR_GROUP2(base); +} + +/*! + * @brief Multiplex group3 set + * + * GROUP3 Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals. + * + * @param base Flexbus module base number. + * @param controls Flexbus multiplex settings for Group3. + * + * @return Flexbus status. + * +*/ +static inline void FLEXBUS_HAL_SetMultiplexControlGroup3(FB_Type* base, flexbus_multiplex_group3_t controls) +{ + FB_BWR_CSPMCR_GROUP3(base, controls); +} + +/*! + * @brief Multiplex group3 get + * + * GROUP3 Controls the multiplexing of the FB_CS4 , FB_TSIZ0, and FB_BE_31_24 signals. + * + * @param base Flexbus module base number. + * + * @return Flexbus multiplex settings for Group3. + * +*/ +static inline flexbus_multiplex_group3_t FLEXBUS_HAL_GetMultiplexControlGroup3(FB_Type* base) +{ + return (flexbus_multiplex_group3_t)FB_BRD_CSPMCR_GROUP3(base); +} + +/*! + * @brief Multiplex group4 set + * + * GROUP4 Controls the multiplexing of the FB_TBST, FB_CS2, and FB_BE_15_8 signals. + * + * @param base Flexbus module base number. + * @param controls Flexbus multiplex settings for Group4. + * + * @return Flexbus status. + * +*/ +static inline void FLEXBUS_HAL_SetMultiplexControlGroup4(FB_Type* base, flexbus_multiplex_group4_t controls) +{ + FB_BWR_CSPMCR_GROUP4(base, controls); +} + +/*! + * @brief Multiplex group4 get + * + * GROUP4 Controls the multiplexing of the FB_TBST, FB_CS2, and FB_BE_15_8 signals. + * + * @param base Flexbus module base number. + * + * @return Flexbus multiplex settings for Group4. + * +*/ +static inline flexbus_multiplex_group4_t FLEXBUS_HAL_GetMultiplexControlGroup4(FB_Type* base) +{ + return (flexbus_multiplex_group4_t)FB_BRD_CSPMCR_GROUP4(base); +} + +/*! + * @brief Multiplex group5 set + * + * GROUP5 Controls the multiplexing of the FB_TA, FB_CS3, and FB_BE_7_0 signals. + * + * @param base Flexbus module base number. + * @param controls Flexbus multiplex settings for Group5. + * + * @return Flexbus status. + * +*/ +static inline void FLEXBUS_HAL_SetMultiplexControlGroup5(FB_Type* base, flexbus_multiplex_group5_t controls) +{ + FB_BWR_CSPMCR_GROUP5(base, controls); +} + +/*! + * @brief Multiplex group5 get + * + * GROUP5 Controls the multiplexing of the FB_TA, FB_CS3, and FB_BE_7_0 signals. + * + * @param base Flexbus module base number. + * + * @return Flexbus multiplex settings for Group5. + * +*/ +static inline flexbus_multiplex_group5_t FLEXBUS_HAL_GetMultiplexControlGroup5(FB_Type* base) +{ + return (flexbus_multiplex_group5_t)FB_BRD_CSPMCR_GROUP5(base); +} + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif +#endif /* __FSL_FLEXCAN_HAL_H__*/ + +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_flexcan_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_flexcan_hal.h new file mode 100755 index 0000000..2710024 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_flexcan_hal.h @@ -0,0 +1,727 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_FLEXCAN_HAL_H__ +#define __FSL_FLEXCAN_HAL_H__ + +#include <assert.h> +#include <stdint.h> +#include <stdbool.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_FLEXCAN_COUNT + +/*! + * @addtogroup flexcan_hal + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief FlexCAN constants*/ +enum _flexcan_constants +{ + kFlexCanMessageSize = 8, /*!< FlexCAN message buffer data size in bytes*/ +}; + +/*! @brief The Status enum is used to report current status of the FlexCAN interface.*/ +enum _flexcan_err_status +{ + kFlexCanRxWrn = 0x0080U, /*!< Reached warning level for RX errors*/ + kFlexCanTxWrn = 0x0100U, /*!< Reached warning level for TX errors*/ + kFlexCanStfErr = 0x0200U, /*!< Stuffing Error*/ + kFlexCanFrmErr = 0x0400U, /*!< Form Error*/ + kFlexCanCrcErr = 0x0800U, /*!< Cyclic Redundancy Check Error*/ + kFlexCanAckErr = 0x1000U, /*!< Received no ACK on transmission*/ + kFlexCanBit0Err = 0x2000U, /*!< Unable to send dominant bit*/ + kFlexCanBit1Err = 0x4000U /*!< Unable to send recessive bit*/ +}; + +/*! @brief FlexCAN status return codes*/ +typedef enum _flexcan_status +{ + kStatus_FLEXCAN_Success = 0, + kStatus_FLEXCAN_OutOfRange, + kStatus_FLEXCAN_UnknownProperty, + kStatus_FLEXCAN_InvalidArgument, + kStatus_FLEXCAN_Fail, + kStatus_FLEXCAN_TimeOut, + kStatus_FLEXCAN_TxBusy, + kStatus_FLEXCAN_RxBusy, + kStatus_FLEXCAN_NoTransmitInProgress, + kStatus_FLEXCAN_NoReceiveInProgress +} flexcan_status_t; + + +/*! @brief FlexCAN operation modes*/ +typedef enum _flexcan_operation_modes { + kFlexCanNormalMode, /*!< Normal mode or user mode @internal gui name="Normal" */ + kFlexCanListenOnlyMode, /*!< Listen-only mode @internal gui name="Listen-only" */ + kFlexCanLoopBackMode, /*!< Loop-back mode @internal gui name="Loop back" */ + kFlexCanFreezeMode, /*!< Freeze mode @internal gui name="Freeze" */ + kFlexCanDisableMode /*!< Module disable mode @internal gui name="Disabled" */ +} flexcan_operation_modes_t; + +/*! @brief FlexCAN message buffer CODE for Rx buffers*/ +typedef enum _flexcan_msgbuff_code_rx { + kFlexCanRXInactive = 0x0, /*!< MB is not active.*/ + kFlexCanRXFull = 0x2, /*!< MB is full.*/ + kFlexCanRXEmpty = 0x4, /*!< MB is active and empty.*/ + kFlexCanRXOverrun = 0x6, /*!< MB is overwritten into a full buffer.*/ + kFlexCanRXBusy = 0x8, /*!< FlexCAN is updating the contents of the MB.*/ + /*! The CPU must not access the MB.*/ + kFlexCanRXRanswer = 0xA, /*!< A frame was configured to recognize a Remote Request Frame*/ + /*! and transmit a Response Frame in return.*/ + kFlexCanRXNotUsed = 0xF /*!< Not used*/ +} flexcan_msgbuff_code_rx_t; + +/*! @brief FlexCAN message buffer CODE FOR Tx buffers*/ +typedef enum _flexcan_msgbuff_code_tx { + kFlexCanTXInactive = 0x08, /*!< MB is not active.*/ + kFlexCanTXAbort = 0x09, /*!< MB is aborted.*/ + kFlexCanTXData = 0x0C, /*!< MB is a TX Data Frame(MB RTR must be 0).*/ + kFlexCanTXRemote = 0x1C, /*!< MB is a TX Remote Request Frame (MB RTR must be 1).*/ + kFlexCanTXTanswer = 0x0E, /*!< MB is a TX Response Request Frame from.*/ + /*! an incoming Remote Request Frame.*/ + kFlexCanTXNotUsed = 0xF /*!< Not used*/ +} flexcan_msgbuff_code_tx_t; + +/*! @brief FlexCAN message buffer transmission types*/ +typedef enum _flexcan_msgbuff_transmission_type { + kFlexCanMBStatusTypeTX, /*!< Transmit MB*/ + kFlexCanMBStatusTypeTXRemote, /*!< Transmit remote request MB*/ + kFlexCanMBStatusTypeRX, /*!< Receive MB*/ + kFlexCanMBStatusTypeRXRemote, /*!< Receive remote request MB*/ + kFlexCanMBStatusTypeRXTXRemote /*!< FlexCAN remote frame receives remote request and*/ + /*! transmits MB.*/ +} flexcan_msgbuff_transmission_type_t; + +typedef enum _flexcan_rx_fifo_id_element_format { + kFlexCanRxFifoIdElementFormatA, /*!< One full ID (standard and extended) per ID Filter Table*/ + /*! element.*/ + kFlexCanRxFifoIdElementFormatB, /*!< Two full standard IDs or two partial 14-bit (standard and*/ + /*! extended) IDs per ID Filter Table element.*/ + kFlexCanRxFifoIdElementFormatC, /*!< Four partial 8-bit Standard IDs per ID Filter Table*/ + /*! element.*/ + kFlexCanRxFifoIdElementFormatD /*!< All frames rejected.*/ +} flexcan_rx_fifo_id_element_format_t; +/*! @brief FlexCAN Rx FIFO filters number*/ +typedef enum _flexcan_rx_fifo_id_filter_number { + kFlexCanRxFifoIDFilters_8 = 0x0, /*!< 8 Rx FIFO Filters. @internal gui name="8 Rx FIFO Filters" */ + kFlexCanRxFifoIDFilters_16 = 0x1, /*!< 16 Rx FIFO Filters. @internal gui name="16 Rx FIFO Filters" */ + kFlexCanRxFifoIDFilters_24 = 0x2, /*!< 24 Rx FIFO Filters. @internal gui name="24 Rx FIFO Filters" */ + kFlexCanRxFifoIDFilters_32 = 0x3, /*!< 32 Rx FIFO Filters. @internal gui name="32 Rx FIFO Filters" */ + kFlexCanRxFifoIDFilters_40 = 0x4, /*!< 40 Rx FIFO Filters. @internal gui name="40 Rx FIFO Filters" */ + kFlexCanRxFifoIDFilters_48 = 0x5, /*!< 48 Rx FIFO Filters. @internal gui name="48 Rx FIFO Filters" */ + kFlexCanRxFifoIDFilters_56 = 0x6, /*!< 56 Rx FIFO Filters. @internal gui name="56 Rx FIFO Filters" */ + kFlexCanRxFifoIDFilters_64 = 0x7, /*!< 64 Rx FIFO Filters. @internal gui name="64 Rx FIFO Filters" */ + kFlexCanRxFifoIDFilters_72 = 0x8, /*!< 72 Rx FIFO Filters. @internal gui name="72 Rx FIFO Filters" */ + kFlexCanRxFifoIDFilters_80 = 0x9, /*!< 80 Rx FIFO Filters. @internal gui name="80 Rx FIFO Filters" */ + kFlexCanRxFifoIDFilters_88 = 0xA, /*!< 88 Rx FIFO Filters. @internal gui name="88 Rx FIFO Filters" */ + kFlexCanRxFifoIDFilters_96 = 0xB, /*!< 96 Rx FIFO Filters. @internal gui name="96 Rx FIFO Filters" */ + kFlexCanRxFifoIDFilters_104 = 0xC, /*!< 104 Rx FIFO Filters. @internal gui name="104 Rx FIFO Filters" */ + kFlexCanRxFifoIDFilters_112 = 0xD, /*!< 112 Rx FIFO Filters. @internal gui name="112 Rx FIFO Filters" */ + kFlexCanRxFifoIDFilters_120 = 0xE, /*!< 120 Rx FIFO Filters. @internal gui name="120 Rx FIFO Filters" */ + kFlexCanRxFifoIDFilters_128 = 0xF /*!< 128 Rx FIFO Filters. @internal gui name="128 Rx FIFO Filters" */ +} flexcan_rx_fifo_id_filter_num_t; + +/*! @brief FlexCAN RX FIFO ID filter table structure*/ +typedef struct FLEXCANIdTable { + bool isRemoteFrame; /*!< Remote frame*/ + bool isExtendedFrame; /*!< Extended frame*/ + uint32_t *idFilter; /*!< Rx FIFO ID filter elements*/ +} flexcan_id_table_t; + +/*! @brief FlexCAN RX mask type.*/ +typedef enum _flexcan_rx_mask_type { + kFlexCanRxMaskGlobal, /*!< Rx global mask*/ + kFlexCanRxMaskIndividual /*!< Rx individual mask*/ +} flexcan_rx_mask_type_t; + +/*! @brief FlexCAN Message Buffer ID type*/ +typedef enum _flexcan_msgbuff_id_type { + kFlexCanMsgIdStd, /*!< Standard ID*/ + kFlexCanMsgIdExt /*!< Extended ID*/ +} flexcan_msgbuff_id_type_t; + +/*! @brief FlexCAN clock source*/ +typedef enum _flexcan_clk_source { + kFlexCanClkSourceOsc, /*!< Oscillator clock*/ + kFlexCanClkSourceIpbus /*!< Peripheral clock*/ +} flexcan_clk_source_t; + +/*! @brief FlexCAN error interrupt types*/ +typedef enum _flexcan_int_type { + kFlexCanIntRxwarning = CAN_CTRL1_RWRNMSK_MASK, /*!< RX warning interrupt*/ + kFlexCanIntTxwarning = CAN_CTRL1_TWRNMSK_MASK, /*!< TX warning interrupt*/ + kFlexCanIntErr = CAN_CTRL1_ERRMSK_MASK, /*!< Error interrupt*/ + kFlexCanIntBusoff = CAN_CTRL1_BOFFMSK_MASK, /*!< Bus off interrupt*/ + kFlexCanIntWakeup = CAN_MCR_WAKMSK_MASK /*!< Wake up interrupt*/ +} flexcan_int_type_t; + +/*! @brief FlexCAN bus error counters*/ +typedef struct FLEXCANBuserrCounter { + uint16_t txerr; /*!< Transmit error counter*/ + uint16_t rxerr; /*!< Receive error counter*/ +} flexcan_buserr_counter_t; + +/*! @brief FlexCAN Message Buffer code and status for transmit and receive */ +typedef struct FLEXCANMsgBuffCodeStatus { + uint32_t code; /*!< MB code for TX or RX buffers. + Defined by flexcan_mb_code_rx_t and flexcan_mb_code_tx_t */ + flexcan_msgbuff_id_type_t msgIdType; /*!< Type of message ID (standard or extended)*/ + uint32_t dataLen; /*!< Length of Data in Bytes*/ +} flexcan_msgbuff_code_status_t; + +/*! @brief FlexCAN message buffer structure*/ +typedef struct FLEXCANMsgBuff { + uint32_t cs; /*!< Code and Status*/ + uint32_t msgId; /*!< Message Buffer ID*/ + uint8_t data[kFlexCanMessageSize]; /*!< Bytes of the FlexCAN message*/ +} flexcan_msgbuff_t; + +/*! @brief FlexCAN timing related structures*/ +typedef struct FLEXCANTimeSegment { + uint32_t propSeg; /*!< Propagation segment*/ + uint32_t phaseSeg1; /*!< Phase segment 1*/ + uint32_t phaseSeg2; /*!< Phase segment 2*/ + uint32_t preDivider; /*!< Clock pre divider*/ + uint32_t rJumpwidth; /*!< Resync jump width*/ +} flexcan_time_segment_t; +#define RxFifoOcuppiedFirstMsgBuff 6U +#define RxFifoOcuppiedLastMsgBuff(x) (5 + (x + 1) * 8 / 4) +#define RxFifoFilterElementNum(x) ((x + 1) * 8) +#define FlexCanRxFifoAcceptRemoteFrame 1U +#define FlexCanRxFifoAcceptExtFrame 1U +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Configuration + * @{ + */ + +/*! + * @brief Enables FlexCAN controller. + * + * @param base The FlexCAN base address + * @return 0 if successful; non-zero failed + */ +flexcan_status_t FLEXCAN_HAL_Enable(CAN_Type * base); + +/*! + * @brief Disables FlexCAN controller. + * + * @param base The FlexCAN base address + * @return 0 if successful; non-zero failed + */ +flexcan_status_t FLEXCAN_HAL_Disable(CAN_Type * base); + +/*! + * @brief Selects the clock source for FlexCAN. + * + * @param base The FlexCAN base address + * @param clk The FlexCAN clock source + * @return 0 if successful; non-zero failed + */ +flexcan_status_t FLEXCAN_HAL_SelectClock(CAN_Type * base, flexcan_clk_source_t clk); + +/*! + * @brief Reads the clock source for FlexCAN Protocol Engine (PE). + * + * @param base The FlexCAN base address + * @return 0: if clock source is oscillator clock, 1: if clock source is peripheral clock + */ +static inline bool FLEXCAN_HAL_GetClock(CAN_Type * base) +{ + return CAN_BRD_CTRL1_CLKSRC(base); +} + +/*! + * @brief Initializes the FlexCAN controller. + * + * @param base The FlexCAN base address + * @return 0 if successful; non-zero failed + */ +flexcan_status_t FLEXCAN_HAL_Init(CAN_Type * base); + +/*! + * @brief Sets the FlexCAN time segments for setting up bit rate. + * + * @param base The FlexCAN base address + * @param timeSeg FlexCAN time segments, which need to be set for the bit rate. + * @return 0 if successful; non-zero failed + */ +void FLEXCAN_HAL_SetTimeSegments(CAN_Type * base, flexcan_time_segment_t *timeSeg); + +/*! + * @brief Gets the FlexCAN time segments to calculate the bit rate. + * + * @param base The FlexCAN base address + * @param timeSeg FlexCAN time segments read for bit rate + * @return 0 if successful; non-zero failed + */ +void FLEXCAN_HAL_GetTimeSegments(CAN_Type * base, flexcan_time_segment_t *timeSeg); + +/*! + * @brief Un freezes the FlexCAN module. + * + * @param base The FlexCAN base address + * @return 0 if successful; non-zero failed. + */ +void FLEXCAN_HAL_ExitFreezeMode(CAN_Type * base); + +/*! + * @brief Freezes the FlexCAN module. + * + * @param base The FlexCAN base address + */ +void FLEXCAN_HAL_EnterFreezeMode(CAN_Type * base); + +/*! + * @brief Set operation mode. + * + * @param base The FlexCAN base address + * @param mode Set an operation mode + * @return 0 if successful; non-zero failed. + */ +flexcan_status_t FLEXCAN_HAL_SetOperationMode( + CAN_Type * base, + flexcan_operation_modes_t mode); + +/*! + * @brief Exit operation mode. + * + * @param base The FlexCAN base address + * @param mode Exit An operation mode + * @return 0 if successful; non-zero failed. + */ +flexcan_status_t FLEXCAN_HAL_ExitOperationMode( + CAN_Type * base, + flexcan_operation_modes_t mode); + +/*@}*/ + +/*! + * @name Data transfer + * @{ + */ + +/*! + * @brief Sets the FlexCAN message buffer fields for transmitting. + * + * @param base The FlexCAN base address + * @param msgBuffIdx Index of the message buffer + * @param cs CODE/status values (TX) + * @param msgId ID of the message to transmit + * @param msgData Bytes of the FlexCAN message + * @return 0 if successful; non-zero failed + */ +flexcan_status_t FLEXCAN_HAL_SetTxMsgBuff( + CAN_Type * base, + uint32_t msgBuffIdx, + flexcan_msgbuff_code_status_t *cs, + uint32_t msgId, + uint8_t *msgData); + +/*! + * @brief Sets the FlexCAN message buffer fields for receiving. + * + * @param base The FlexCAN base address + * @param msgBuffIdx Index of the message buffer + * @param cs CODE/status values (RX) + * @param msgId ID of the message to receive + * @return 0 if successful; non-zero failed + */ +flexcan_status_t FLEXCAN_HAL_SetRxMsgBuff( + CAN_Type * base, + uint32_t msgBuffIdx, + flexcan_msgbuff_code_status_t *cs, + uint32_t msgId); + +/*! + * @brief Gets the FlexCAN message buffer fields. + * + * @param base The FlexCAN base address + * @param msgBuffIdx Index of the message buffer + * @param msgBuff The fields of the message buffer + * @return 0 if successful; non-zero failed + */ +flexcan_status_t FLEXCAN_HAL_GetMsgBuff( + CAN_Type * base, + uint32_t msgBuffIdx, + flexcan_msgbuff_t *msgBuff); + +/*! + * @brief Locks the FlexCAN Rx message buffer. + * + * @param base The FlexCAN base address + * @param msgBuffIdx Index of the message buffer + * @return 0 if successful; non-zero failed + */ +flexcan_status_t FLEXCAN_HAL_LockRxMsgBuff( + CAN_Type * base, + uint32_t msgBuffIdx); + +/*! + * @brief Unlocks the FlexCAN Rx message buffer. + * + * @param base The FlexCAN base address + * @return 0 if successful; non-zero failed + */ +static inline uint32_t FLEXCAN_HAL_UnlockRxMsgBuff(CAN_Type * base) +{ + uint32_t tmp; + /* Unlock the mailbox */ + tmp = CAN_RD_TIMER(base); + return tmp; +} + +/*! + * @brief Enables the Rx FIFO. + * + * @param base The FlexCAN base address + * @param numOfFilters The number of Rx FIFO filters + */ +void FLEXCAN_HAL_EnableRxFifo(CAN_Type * base, uint32_t numOfFilters); + +/*! + * @brief Disables the Rx FIFO. + * + * @param base The FlexCAN base address + */ +void FLEXCAN_HAL_DisableRxFifo(CAN_Type * base); + +/*! + * @brief Sets the number of the Rx FIFO filters. + * + * @param base The FlexCAN base address + * @param number The number of Rx FIFO filters + */ +void FLEXCAN_HAL_SetRxFifoFilterNum(CAN_Type * base, uint32_t number); + +/*! + * @brief Sets the maximum number of Message Buffers. + * + * @param base The FlexCAN base address + * @param maxMsgBuffNum Maximum number of message buffers + */ +void FLEXCAN_HAL_SetMaxMsgBuffNum( + CAN_Type * base, + uint32_t maxMsgBuffNum); + +/*! + * @brief Sets the FlexCAN Rx FIFO fields. + * + * @param base The FlexCAN base address + * @param idFormat The format of the Rx FIFO ID Filter Table Elements + * @param idFilterTable The ID filter table elements which contain RTR bit, IDE bit, + * and RX message ID. + * @return 0 if successful; non-zero failed. + */ +flexcan_status_t FLEXCAN_HAL_SetRxFifoFilter( + CAN_Type * base, + flexcan_rx_fifo_id_element_format_t idFormat, + flexcan_id_table_t *idFilterTable); + +/*! + * @brief Gets the FlexCAN Rx FIFO data. + * + * @param base The FlexCAN base address + * @param rxFifo The FlexCAN receive FIFO data + * @return 0 if successful; non-zero failed. + */ +flexcan_status_t FLEXCAN_HAL_ReadRxFifo( + CAN_Type * base, + flexcan_msgbuff_t *rxFifo); + +/*@}*/ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables/Disables the FlexCAN Message Buffer interrupt. + * + * @param base The FlexCAN base address + * @param msgBuffIdx Index of the message buffer + * @param enable choose enable or disable + * @return 0 if successful; non-zero failed + */ +flexcan_status_t FLEXCAN_HAL_SetMsgBuffIntCmd( + CAN_Type * base, + uint32_t msgBuffIdx, bool enable); + +/*! + * @brief Enables error interrupt of the FlexCAN module. + * @param base The FlexCAN base address + * @param errType The interrupt type + * @param enable choose enable or disable + */ +void FLEXCAN_HAL_SetErrIntCmd(CAN_Type * base, flexcan_int_type_t errType, bool enable); + +/*@}*/ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the value of FlexCAN freeze ACK. + * + * @param base The FlexCAN base address + * @return freeze ACK state (1-freeze mode, 0-not in freeze mode). + */ +static inline uint32_t FLEXCAN_HAL_GetFreezeAck(CAN_Type * base) +{ + return CAN_BRD_MCR_FRZACK(base); +} + +/*! + * @brief Gets the individual FlexCAN MB interrupt flag. + * + * @param base The FlexCAN base address + * @param msgBuffIdx Index of the message buffer + * @return the individual Message Buffer interrupt flag (0 and 1 are the flag value) + */ +uint8_t FLEXCAN_HAL_GetMsgBuffIntStatusFlag( + CAN_Type * base, + uint32_t msgBuffIdx); + +/*! + * @brief Gets all FlexCAN Message Buffer interrupt flags. + * + * @param base The FlexCAN base address + * @return all MB interrupt flags + */ +static inline uint32_t FLEXCAN_HAL_GetAllMsgBuffIntStatusFlag(CAN_Type * base) +{ + return CAN_RD_IFLAG1(base); +} + +/*! + * @brief Clears the interrupt flag of the message buffers. + * + * @param base The FlexCAN base address + * @param flag The value to be written to the interrupt flag1 register. + */ +/* See fsl_flexcan_hal.h for documentation of this function.*/ +static inline void FLEXCAN_HAL_ClearMsgBuffIntStatusFlag( + CAN_Type * base, + uint32_t flag) +{ + /* Clear the corresponding message buffer interrupt flag*/ + CAN_WR_IFLAG1(base, flag); +} + +/*! + * @brief Gets the transmit error counter and receives the error counter. + * + * @param base The FlexCAN base address + * @param errCount Transmit error counter and receive error counter + */ +void FLEXCAN_HAL_GetErrCounter( + CAN_Type * base, + flexcan_buserr_counter_t *errCount); + +/*! + * @brief Gets error and status. + * + * @param base The FlexCAN base address + * @return The current error and status + */ +static inline uint32_t FLEXCAN_HAL_GetErrStatus(CAN_Type * base) +{ + return CAN_RD_ESR1(base); +} + +/*! + * @brief Clears all other interrupts in ERRSTAT register (Error, Busoff, Wakeup). + * + * @param base The FlexCAN base address + */ +void FLEXCAN_HAL_ClearErrIntStatusFlag(CAN_Type * base); + +/*@}*/ + +/*! + * @name Mask + * @{ + */ + +/*! + * @brief Sets the Rx masking type. + * + * @param base The FlexCAN base address + * @param type The FlexCAN Rx mask type + */ +void FLEXCAN_HAL_SetRxMaskType(CAN_Type * base, flexcan_rx_mask_type_t type); + +/*! + * @brief Sets the FlexCAN RX FIFO global standard mask. + * + * @param base The FlexCAN base address + * @param stdMask Standard mask + */ +void FLEXCAN_HAL_SetRxFifoGlobalStdMask( + CAN_Type * base, + uint32_t stdMask); + +/*! + * @brief Sets the FlexCAN Rx FIFO global extended mask. + * + * @param base The FlexCAN base address + * @param extMask Extended mask + */ +void FLEXCAN_HAL_SetRxFifoGlobalExtMask( + CAN_Type * base, + uint32_t extMask); + +/*! + * @brief Sets the FlexCAN Rx individual standard mask for ID filtering in the Rx MBs and the Rx FIFO. + * + * @param base The FlexCAN base address + * @param msgBuffIdx Index of the message buffer + * @param stdMask Individual standard mask + * @return 0 if successful; non-zero failed + */ +flexcan_status_t FLEXCAN_HAL_SetRxIndividualStdMask( + CAN_Type * base, + uint32_t msgBuffIdx, + uint32_t stdMask); + +/*! + * @brief Sets the FlexCAN Rx individual extended mask for ID filtering in the Rx Message Buffers and the Rx FIFO. + * + * @param base The FlexCAN base address + * @param msgBuffIdx Index of the message buffer + * @param extMask Individual extended mask + * @return 0 if successful; non-zero failed + */ +flexcan_status_t FLEXCAN_HAL_SetRxIndividualExtMask( + CAN_Type * base, + uint32_t msgBuffIdx, + uint32_t extMask); + +/*! + * @brief Sets the FlexCAN Rx Message Buffer global standard mask. + * + * @param base The FlexCAN base address + * @param stdMask Standard mask + */ +void FLEXCAN_HAL_SetRxMsgBuffGlobalStdMask( + CAN_Type * base, + uint32_t stdMask); + +/*! + * @brief Sets the FlexCAN RX Message Buffer BUF14 standard mask. + * + * @param base The FlexCAN base address + * @param stdMask Standard mask + */ +void FLEXCAN_HAL_SetRxMsgBuff14StdMask( + CAN_Type * base, + uint32_t stdMask); + +/*! + * @brief Sets the FlexCAN Rx Message Buffer BUF15 standard mask. + * + * @param base The FlexCAN base address + * @param stdMask Standard mask + * @return 0 if successful; non-zero failed + */ +void FLEXCAN_HAL_SetRxMsgBuff15StdMask( + CAN_Type * base, + uint32_t stdMask); + +/*! + * @brief Sets the FlexCAN RX Message Buffer global extended mask. + * + * @param base The FlexCAN base address + * @param extMask Extended mask + */ +void FLEXCAN_HAL_SetRxMsgBuffGlobalExtMask( + CAN_Type * base, + uint32_t extMask); + +/*! + * @brief Sets the FlexCAN RX Message Buffer BUF14 extended mask. + * + * @param base The FlexCAN base address + * @param extMask Extended mask + */ +void FLEXCAN_HAL_SetRxMsgBuff14ExtMask( + CAN_Type * base, + uint32_t extMask); + +/*! + * @brief Sets the FlexCAN RX MB BUF15 extended mask. + * + * @param base The FlexCAN base address + * @param extMask Extended mask + */ +void FLEXCAN_HAL_SetRxMsgBuff15ExtMask( + CAN_Type * base, + uint32_t extMask); + +/*! + * @brief Gets the FlexCAN ID acceptance filter hit indicator on Rx FIFO. + * + * @param base The FlexCAN base address + * @return RX FIFO information + */ +static inline uint32_t FLEXCAN_HAL_GetRxFifoHitIdAcceptanceFilter(CAN_Type * base) +{ + return CAN_BRD_RXFIR_IDHIT(base); +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif +#endif /* __FSL_FLEXCAN_HAL_H__*/ + +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_flexio_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_flexio_hal.h new file mode 100755 index 0000000..d15a6a3 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_flexio_hal.h @@ -0,0 +1,788 @@ +/* + * Copyright (c) 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_FLEXIO_HAL_H__ +#define __FSL_FLEXIO_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> + +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_FLEXIO_COUNT + +/*! + * @addtogroup flexio_hal + * @{ + */ + +/******************************************************************************* + * Enumeration. + ******************************************************************************/ +/*! + * @brief FlexIO status return code. + */ +typedef enum +{ + kStatus_FLEXIO_Success = 0U, /*!< Success. */ + kStatus_FLEXIO_InvalidArgument = 1U, /*!< Invalid argument existed. */ + kStatus_FLEXIO_Failed = 2U /*!< Execution failed. */ +} flexio_status_t; + +/*! + * @brief Define time of timer trigger polarity. + */ +typedef enum _flexio_timer_trigger_polarity +{ + kFlexioTimerTriggerPolarityActiveHigh = 0U, /*!< Active high. */ + kFlexioTimerTriggerPolarityActiveLow = 1U /*!< Active low. */ +} flexio_timer_trigger_polarity_t; + +/*! + * @brief Define type of timer trigger source. + */ +typedef enum _flexio_timer_trigger_source +{ + kFlexioTimerTriggerSourceExternal = 0U, /*!< External trigger selected. */ + kFlexioTimerTriggerSourceInternal = 1U /*!< Internal trigger selected. */ +} flexio_timer_trigger_source_t; + +/*! + * @brief Define type of timer/shifter pin configuration. + */ +typedef enum _flexio_pin_config +{ + kFlexioPinConfigOutputDisabled = 0U, /*!< Pin output disabled. */ + kFlexioPinConfigOpenDrainOrBidirection = 1U, /*!< Pin open drain or bidirectional output enable. */ + kFlexioPinConfigBidirectionOutputData = 2U, /*!< Pin bidirectional output data. */ + kFlexioPinConfigOutput = 3U /*!< Pin output. */ +} flexio_pin_config_t; + +/*! + * @brief Definition of pin polarity. + */ +typedef enum _flexio_pin_polarity +{ + kFlexioPinActiveHigh = 0U, /*!< Active high. */ + kFlexioPinActiveLow = 1U /*!< Active low. */ +} flexio_pin_polarity_t; + +/*! + * @brief Define type of timer work mode. + */ +typedef enum _flexio_timer_mode +{ + kFlexioTimerModeDisabled = 0U, /*!< Timer Disabled. */ + kFlexioTimerModeDual8BitBaudBit = 1U, /*!< Dual 8-bit counters baud/bit mode. */ + kFlexioTimerModeDual8BitPWM = 2U, /*!< Dual 8-bit counters PWM mode. */ + kFlexioTimerModeSingle16Bit = 3U /*!< Single 16-bit counter mode. */ +} flexio_timer_mode_t; + +/*! + * @brief Define type of timer initial output or timer reset affaction. + */ +typedef enum _flexio_timer_output +{ + kFlexioTimerOutputOneNotAffectedByReset = 0U, /*!< Logic one when enabled and is not affected by timer reset. */ + kFlexioTimerOutputZeroNotAffectedByReset = 1U, /*!< Logic zero when enabled and is not affected by timer reset. */ + kFlexioTimerOutputOneAffectedByReset = 2U, /*!< Logic one when enabled and on timer reset. */ + kFlexioTimerOutputZeroAffectedByReset = 3U /*!< Logic zero when enabled and on timer reset. */ +} flexio_timer_output_t; + +/*! + * @brief Define type of timer decerement. + */ +typedef enum _flexio_timer_decrement_source +{ + kFlexioTimerDecSrcOnFlexIOClockShiftTimerOutput = 0U, /*!< Decrement counter on FlexIO clock, Shift clock equals Timer output. */ + kFlexioTimerDecSrcOnTriggerInputShiftTimerOutput = 1U, /*!< Decrement counter on Trigger input (both edges), Shift clock equals Timer output. */ + kFlexioTimerDecSrcOnPinInputShiftPinInput = 2U, /*!< Decrement counter on Pin input (both edges), Shift clock equals Pin input. */ + kFlexioTimerDecSrcOnTriggerInputShiftTriggerInput = 3U /*!< Decrement counter on Trigger input (both edges), Shift clock equals Trigger input. */ +} flexio_timer_decrement_source_t; + +/*! + * @brief Define type of timer reset condition. + */ +typedef enum _flexio_timer_reset_condition +{ + kFlexioTimerResetNever = 0U, /*!< Timer never reset. */ + kFlexioTimerResetOnTimerPinEqualToTimerOutput = 2U, /*!< Timer reset on Timer Pin equal to Timer Output. */ + kFlexioTimerResetOnTimerTriggerEqualToTimerOutput = 3U, /*!< Timer reset on Timer Trigger equal to Timer Output. */ + kFlexioTimerResetOnTimerPinRisingEdge = 4U, /*!< Timer reset on Timer Pin rising edge. */ + kFlexioTimerResetOnTimerTriggerRisingEdge = 6U, /*!< Timer reset on Trigger rising edge. */ + kFlexioTimerResetOnTimerTriggerBothEdge = 7U /*!< Timer reset on Trigger rising or falling edge. */ +} flexio_timer_reset_condition_t; + +/*! + * @brief Define type of timer disable condition. + */ +typedef enum _flexio_timer_disable_condition +{ + kFlexioTimerDisableNever = 0U, /*!< Timer never disabled. */ + kFlexioTimerDisableOnPreTimerDisable = 1U, /*!< Timer disabled on Timer N-1 disable. */ + kFlexioTimerDisableOnTimerCompare = 2U, /*!< Timer disabled on Timer compare. */ + kFlexioTimerDisableOnTimerCompareTriggerLow = 3U, /*!< Timer disabled on Timer compare and Trigger Low. */ + kFlexioTimerDisableOnPinBothEdge = 4U, /*!< Timer disabled on Pin rising or falling edge. */ + kFlexioTimerDisableOnPinBothEdgeTriggerHigh = 5U, /*!< Timer disabled on Pin rising or falling edge provided Trigger is high. */ + kFlexioTimerDisableOnTriggerFallingEdge = 6U /*!< Timer disabled on Trigger falling edge. */ +} flexio_timer_disable_condition_t; + +/*! + * @brief Define type of timer enable condition. + */ +typedef enum _flexio_timer_enable_condition +{ + kFlexioTimerEnabledAlways = 0U, /*!< Timer always enabled. */ + kFlexioTimerEnableOnPrevTimerEnable = 1U, /*!< Timer enabled on Timer N-1 enable. */ + kFlexioTimerEnableOnTriggerHigh = 2U, /*!< Timer enabled on Trigger high. */ + kFlexioTimerEnableOnTriggerHighPinHigh = 3U, /*!< Timer enabled on Trigger high and Pin high. */ + kFlexioTimerEnableOnPinRisingEdge = 4U, /*!< Timer enabled on Pin rising edge. */ + kFlexioTimerEnableOnPinRisingEdgeTriggerHigh = 5U, /*!< Timer enabled on Pin rising edge and Trigger high. */ + kFlexioTimerEnableOnTriggerRisingEdge = 6U, /*!< Timer enabled on Trigger rising edge. */ + kFlexioTimerEnableOnTriggerBothEdge = 7U /*!< Timer enabled on Trigger rising or falling edge. */ +} flexio_timer_enable_condition_t; + +/*! + * @brief Define type of timer stop bit generate condition. + */ +typedef enum _flexio_timer_stop_bit_condition +{ + kFlexioTimerStopBitDisabled = 0U, /*!< Stop bit disabled. */ + kFlexioTimerStopBitEnableOnTimerCompare = 1U, /*!< Stop bit is enabled on timer compare. */ + kFlexioTimerStopBitEnableOnTimerDisable = 2U, /*!< Stop bit is enabled on timer disable. */ + kFlexioTimerStopBitEnableOnTimerCompareDisable = 3U /*!< Stop bit is enabled on timer compare and timer disable. */ +} flexio_timer_stop_bit_condition_t; + +/*! + * @brief Define type of timer start bit generate condition. + */ +typedef enum _flexio_timer_start_bit_condition +{ + kFlexioTimerStartBitDisabled = 0U, /*!< Start bit disabled. */ + kFlexioTimerStartBitEnabled = 1U /*!< Start bit enabled. */ +} flexio_timer_start_bit_condition_t; + +/*! @briedf Define type of timer polarity for shifter control. */ +typedef enum _flexio_shifter_timer_polarity +{ + kFlexioShifterTimerPolarityOnPositive = 0U, /* Shift on positive edge of shift clock */ + kFlexioShifterTimerPolarityOnNegitive = 1U /* Shift on negative edge of shift clock */ +} flexio_shifter_timer_polarity_t; + +/*! + * @brief Define type of shifter working mode. + */ +typedef enum _flexio_shifter_mode +{ + kFlexioShifterDisabled = 0U, /*!< Shifter is disabled. */ + kFlexioShifterModeReceive = 1U, /*!< Receive mode. */ + kFlexioShifterModeTransmit = 2U, /*!< Transmit mode. */ + kFlexioShifterModeMatchStore = 4U, /*!< Match store mode. */ + kFlexioShifterModeMatchContinuous = 5U /*!< Match continuous mode. */ +} flexio_shifter_mode_t; + +/*! + * @brief Define type of shifter input source. + */ +typedef enum _flexio_shifter_input_source +{ + kFlexioShifterInputFromPin = 0U, /*!< Shifter input from pin. */ + kFlexioShifterInputFromNextShifterOutput = 1U /*!< Shifter input from Shifter N+1. */ +} flexio_shifter_input_source_t; + +/*! + * @brief Define of STOP bit configuration. + */ +typedef enum _flexio_shifter_stop_bit +{ + kFlexioShifterStopBitDisable = 0U, /*!< Disable shifter stop bit. */ + kFlexioShifterStopBitLow = 2U, /*!< Set shifter stop bit to logic low level. */ + kFlexioShifterStopBitHigh = 3U /*!< Set shifter stop bit to logic high level. */ +} flexio_shifter_stop_bit_t; + +/*! + * @brief Define type of START bit configuration. + */ +typedef enum _flexio_shifter_start_bit +{ + kFlexioShifterStartBitDisabledLoadDataOnEnable = 0U, /*!< Disable shifter start bit, transmitter loads data on enable. */ + kFlexioShifterStartBitDisabledLoadDataOnShift = 1U, /*!< Disable shifter start bit, transmitter loads data on first shift. */ + kFlexioShifterStartBitLow = 2U, /*!< Set shifter start bit to logic low level. */ + kFlexioShifterStartBitHigh = 3U /*!< Set shifter start bit to logic high lecel. */ +} flexio_shifter_start_bit_t; + +/******************************************************************************* + * Definitions. + ******************************************************************************/ + +/*! + * @brief Define structure of configuring the FlexIO timer. + */ +typedef struct _flexio_timer_config_t +{ + /* Trigger. */ + uint32_t trgsel; /*!< The internal trigger selection number using MACROs. */ + flexio_timer_trigger_polarity_t trgpol; /*!< Trigger Polarity. */ + flexio_timer_trigger_source_t trgsrc; /*!< Trigger Source, internal(see to 'trgsel') or external. */ + /* Pin. */ + flexio_pin_config_t pincfg; /*!< Timer Pin Configuration. */ + uint32_t pinsel; /*!< Timer Pin number Select. */ + flexio_pin_polarity_t pinpol; /*!< Timer Pin Polarity. */ + /* Timer. */ + flexio_timer_mode_t timod; /*!< Timer work Mode. */ + flexio_timer_output_t timout; /*!< Configures the initial state of the Timer Output and whether it is affected by the Timer reset. */ + flexio_timer_decrement_source_t timdec; /*!< Configures the source of the Timer decrement and the source of the Shift clock. */ + flexio_timer_reset_condition_t timrst; /*!< Configures the condition that causes the timer counter (and optionally the timer output) to be reset. */ + flexio_timer_disable_condition_t timdis; /*!< Configures the condition that causes the Timer to be disabled and stop decrementing. */ + flexio_timer_enable_condition_t timena; /*!< Configures the condition that causes the Timer to be enabled and start decrementing. */ + flexio_timer_stop_bit_condition_t tstop; /*!< Timer STOP Bit generation. */ + flexio_timer_start_bit_condition_t tstart; /*!< Timer STRAT Bit generation. */ + uint32_t timcmp; /*!< Value for Timer Compare N Register. */ +} flexio_timer_config_t; + +#define FLEXIO_HAL_TIMER_TRIGGER_SEL_PININPUT(x) ((x) << 1) +#define FLEXIO_HAL_TIMER_TRIGGER_SEL_SHIFTnSTAT(x) (((x) << 2) | 0x1) +#define FLEXIO_HAL_TIMER_TRIGGER_SEL_TIMn(x) (((x) << 2) | 0x3) + +/*! + * @brief Define structure of configure the Flexio shifter. + */ +typedef struct _flexio_shifter_config_t +{ + /* Timer. */ + uint32_t timsel; /*!< Selects which Timer is used for controlling the logic/shift register and generating the Shift clock. */ + flexio_shifter_timer_polarity_t timpol; /*!< Timer Polarity. */ + /* Pin. */ + flexio_pin_config_t pincfg; /*!< Shifter Pin Configuration. */ + uint32_t pinsel; /*!< Shifter Pin number Select. */ + flexio_pin_polarity_t pinpol; /*!< Shifter Pin Polarity. */ + /* Shifter. */ + flexio_shifter_mode_t smode; /*!< Configures the mode of the Shifter. */ + flexio_shifter_input_source_t insrc; /*!< Selects the input source for the shifter. */ + flexio_shifter_stop_bit_t sstop; /*!< Shifter STOP bit. */ + flexio_shifter_start_bit_t sstart; /*!< Shifter START bit. */ +} flexio_shifter_config_t; + +/******************************************************************************* + * APIs. + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*------------------------------------------------------------------------------ + * FLEXIO_VERID + *----------------------------------------------------------------------------*/ +/*! + * @brief Get the FlexIO major version number. + * + * @param base base address + * @return major version + */ +static inline uint32_t FLEXIO_HAL_GetMajorVersionNumber(FLEXIO_Type * base) +{ + return FLEXIO_BRD_VERID_MAJOR(base); +} + +/*! + * @brief Get the FlexIO minor version number. + * + * @param base base address + * @return minor version + */ +static inline uint32_t FLEXIO_HAL_GetMinorVersionNumber(FLEXIO_Type * base) +{ + return FLEXIO_BRD_VERID_MINOR(base); +} + +/*! + * @brief Get the FlexIO feature specification number. + * + * @param base base address + * @return feature number + */ +static inline uint32_t FLEXIO_HAL_GetFeatureNumber(FLEXIO_Type * base) +{ + return FLEXIO_BRD_VERID_FEATURE(base); +} + +/*------------------------------------------------------------------------------ + * FLEXIO_PARAM + *----------------------------------------------------------------------------*/ +/*! + * @brief Get the number of external triggers implemented. + * + * @param base base address + * @return number of external triggers + */ +static inline uint32_t FLEXIO_HAL_GetTriggerNumber(FLEXIO_Type * base) +{ + return FLEXIO_BRD_PARAM_TRIGGER(base); +} + +/*! + * @brief Get the number of pins implemented. + * + * @param base base address + * @return number of pins + */ +static inline uint32_t FLEXIO_HAL_GetPinNumber(FLEXIO_Type * base) +{ + return FLEXIO_BRD_PARAM_PIN(base); +} + +/*! + * @brief Get the number of timers implemented. + * + * @param base base address + * @return number of timers + */ +static inline uint32_t FLEXIO_HAL_GetTimerNumber(FLEXIO_Type * base) +{ + return FLEXIO_BRD_PARAM_TIMER(base); +} + +/*! + * @brief Get the number of shifters implemented. + * + * @param base base address + * @return number of shifters + */ +static inline uint32_t FLEXIO_HAL_GetShifterNumber(FLEXIO_Type * base) +{ + return FLEXIO_BRD_PARAM_SHIFTER(base); +} + +/*------------------------------------------------------------------------------ + * FLEXIO_CTRL + *----------------------------------------------------------------------------*/ +/*! + * @brief Control the FlexIO operation in Doze modes. + * + * @param base base address + * @param enable Pass true to enable FlexIO in Doze modes. + */ +static inline void FLEXIO_HAL_SetDozeModeCmd(FLEXIO_Type * base, bool enable) +{ + FLEXIO_BWR_CTRL_DOZEN(base, enable ? 1U : 0U); +} + +/*! + * @brief Control the FlexIO operation in Debug mode. + * + * @param base base address + * @param enable Pass true to enable FlexIO in Debug mode. + */ +static inline void FLEXIO_HAL_SetDebugModeCmd(FLEXIO_Type * base, bool enable) +{ + FLEXIO_BWR_CTRL_DBGE(base, enable ? 1U : 0U); +} + +/*! + * @brief Control the FlexIO register accesses speed. + * + * @param base base address + * @param enable true if fast register access is enabled, FlexIO clock to be set + * at least twice the frequency of the bus clock. Or false if normal register + * accesses is selected. + */ +static inline void FLEXIO_HAL_SetFastAccessCmd(FLEXIO_Type * base, bool enable) +{ + FLEXIO_BWR_CTRL_FASTACC(base, enable ? 1U : 0U); +} + +/*! + * @brief Software reset of the module + * + * @param base base address + * @param enable true - Enable software reset + * false - Clear software reset + */ +static inline void FLEXIO_HAL_SetSoftwareResetCmd(FLEXIO_Type * base, bool enable) +{ + FLEXIO_BWR_CTRL_SWRST(base, enable ? 1U : 0U); +} + +/*! + * @brief Enable the FlexIO module operation. + * + * @param base base address + * @param enable Pass true to enable FlexIO + */ +static inline void FLEXIO_HAL_SetFlexioEnableCmd(FLEXIO_Type * base, bool enable) +{ + /*FLEXIO_BWR_CTRL_FLEXEN(base, enable ? 1U : 0U);*/ + uint32_t tmp32 = FLEXIO_RD_CTRL(base); + tmp32 &= ~FLEXIO_CTRL_FLEXEN_MASK; + if (enable) + { + tmp32 |= FLEXIO_CTRL_FLEXEN_MASK; + } + FLEXIO_WR_CTRL(base, tmp32); +} + +/*------------------------------------------------------------------------------ + * Timer + *----------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------------ + * FLEXIO_TIMIEN - Timer Interrupt Enable Register + *----------------------------------------------------------------------------*/ +/*! + * @brief Enable or disable timer status interrupt requests. + * + * @param base base address + * @param mask Mask of timers to be enabled/disabled interrupt status + * @param enable Pass true to enable interrupt, false to disable + */ +void FLEXIO_HAL_SetTimerStatusIntCmd(FLEXIO_Type * base, uint32_t mask, bool enable); + +/*------------------------------------------------------------------------------ + * FLEXIO_TIMSTAT - Timer Status Register + *----------------------------------------------------------------------------*/ +/*! + * @brief Get timer status flags. + * + * @param base base address + * + * @return timer status flags + */ +static inline uint32_t FLEXIO_HAL_GetTimerStatusFlags(FLEXIO_Type * base) +{ + return FLEXIO_BRD_TIMSTAT_TSF(base); +} + +/*! + * @brief Clear timer status flags. + * + * @param base base address + * @param mask timer mask + * + * @return timer status flags + */ +static inline void FLEXIO_HAL_ClearTimerStatusFlags(FLEXIO_Type * base, uint32_t mask) +{ + FLEXIO_BWR_TIMSTAT_TSF(base, mask); +} + +/*------------------------------------------------------------------------------ + * FLEXIO_TIMCTLn - Timer Control N Register + * FLEXIO_TIMCFGn - Timer Configuration N Register + * FLEXIO_TIMCMPn - Timer Compare N Register + *----------------------------------------------------------------------------*/ +/*! + * @brief Configure a timer in FlexIO. + * + * @param base base address + * @param timerIdx timer id number + * @param timerConfigPtr pointer to FlexIO's timer configuration data + */ +void FLEXIO_HAL_ConfigureTimer(FLEXIO_Type * base, uint32_t timerIdx, + const flexio_timer_config_t *timerConfigPtr); + +/*------------------------------------------------------------------------------ + * Shfiter + *----------------------------------------------------------------------------*/ +/*------------------------------------------------------------------------------ + * FLEXIO_SHIFTSTAT - Shifter Status Register + *----------------------------------------------------------------------------*/ +/*! + * @brief Get shifter status flags. + * + * @param base base address + * + * @return shifter status flags + */ +static inline uint32_t FLEXIO_HAL_GetShifterStatusFlags(FLEXIO_Type * base) +{ + return FLEXIO_BRD_SHIFTSTAT_SSF(base); +} + +/*! + * @brief Clear shifter status flags. + * + * @param base base address + * @param mask shifter mask + * + * @return shifter status flags + */ +static inline void FLEXIO_HAL_ClearShifterStatusFlags(FLEXIO_Type * base, uint32_t mask) +{ + FLEXIO_BWR_SHIFTSTAT_SSF(base, mask); +} + +/*------------------------------------------------------------------------------ + * FLEXIO_SHIFTSIEN - Shifter Status Interrupt Enable + *----------------------------------------------------------------------------*/ +/*! + * @brief Enable or disable shifter status interrupt requests. + * + * @param base base address + * @param mask Mask of shifters to be enabled/disabled status interrupt status + * @param enable Pass true to enable interrupt, false to disable + */ +void FLEXIO_HAL_SetShifterStatusIntCmd(FLEXIO_Type * base, uint32_t mask, bool enable); + +/*! + * @brief Return enabled shifter status interrupt + * + * @param base base address + * + * @return mask - Mask of enabled shifter status interrupt + */ +static inline uint32_t FLEXIO_HAL_GetShifterStatusIntCmd(FLEXIO_Type * base) +{ + return FLEXIO_BRD_SHIFTSIEN_SSIE(base); +} + +/*------------------------------------------------------------------------------ + * FLEXIO_SHIFTERR - Shifter Error Register + *----------------------------------------------------------------------------*/ +/*! + * @brief Get shifter error flags. + * + * @param base base address + * + * @return shifter error flags + */ +static inline uint32_t FLEXIO_HAL_GetShifterErrorFlags(FLEXIO_Type * base) +{ + return FLEXIO_BRD_SHIFTERR_SEF(base); +} + +/*! + * @brief Clear shifter error flags. + * + * @param base base address + * @param mask shifter mask + * + * @return shifter error flags + */ +static inline void FLEXIO_HAL_ClearShifterErrorFlags(FLEXIO_Type * base, uint32_t mask) +{ + FLEXIO_BWR_SHIFTERR_SEF(base, mask); +} + +/*------------------------------------------------------------------------------ + * FLEXIO_SHIFTEIEN - Shifter Error Interrupt Enable + *----------------------------------------------------------------------------*/ +/*! + * @brief Return shifter enabled error interrupts + * + * @param base base address + * + * @return mask - Mask of enabled shifter error interrupt + */ +static inline uint32_t FLEXIO_HAL_GetShifterErrorInt(FLEXIO_Type * base) +{ + return FLEXIO_BRD_SHIFTEIEN_SEIE(base); +} + +/*! + * @brief Enable or disable shifter error interrupt requests. + * + * @param base base address + * @param mask Mask of shifters to be enabled/disabled error interrupt status + * @param enable Pass true to enable interrupt, false to disable + */ +void FLEXIO_HAL_SetShifterErrorIntCmd(FLEXIO_Type * base, uint32_t mask, bool enable); + +/*------------------------------------------------------------------------------ + * FLEXIO_SHIFTCTLn - Shifter Control N Register + * FLEXIO_SHIFTCFGn - Shifter Configuration N Register + *----------------------------------------------------------------------------*/ +/*! + * @brief Configure a shifter including ctl, cfg + * + * @param base base address + * @param shifterIdx shifter index + * @param shifterConfigPtr pointer to shifter configuration structure + */ +void FLEXIO_HAL_ConfigureShifter(FLEXIO_Type * base, uint32_t shifterIdx, + const flexio_shifter_config_t *shifterConfigPtr); + +/*------------------------------------------------------------------------------ + * FLEXIO_SHIFTSDEN - Shifter Status DMA Enable + *----------------------------------------------------------------------------*/ +/*! + * @brief Return shifter enabled status DMA support. + * + * @param base base address + * + * @return mask Mask of shifters' DMA status + */ +static inline uint32_t FLEXIO_HAL_GetShiftStatusDma(FLEXIO_Type * base) +{ + return FLEXIO_BRD_SHIFTSDEN_SSDE(base); +} + +/*! + * @brief Enable or disable shifter status DMA support. + * + * @param base base address + * @param mask Mask of shifters to be enabled/disabled DMA status + * @param enable Pass true to enable DMA transfer signalling + */ +void FLEXIO_HAL_SetShifterStatusDmaCmd(FLEXIO_Type * base, uint32_t mask, bool enable); + +/*------------------------------------------------------------------------------ + * FLEXIO_SHIFTBUFn - Shifter Buffer N Register + *----------------------------------------------------------------------------*/ +/*! + * @brief Store data from shifter buffer. + * + * @param base base address + * @param shifterIdx shifter index + * + * @return shifter buffer content + */ +static inline uint32_t FLEXIO_HAL_GetShifterBuffer(FLEXIO_Type * base, uint32_t shifterIdx) +{ + return FLEXIO_RD_SHIFTBUF(base, shifterIdx); +} + +/*! + * @brief Load data to shifter buffer. + * + * @param base base address + * @param shifterIdx shifter index + * @param value Value to be load to shifter buffer + */ +static inline void FLEXIO_HAL_SetShifterBuffer(FLEXIO_Type * base, uint32_t shifterIdx, uint32_t value) +{ + FLEXIO_WR_SHIFTBUF(base, shifterIdx, value); +} + +/*------------------------------------------------------------------------------ + * FLEXIO_SHIFTBUFBBSn - Shifter Buffer N Bit Byte Swapped Register + *----------------------------------------------------------------------------*/ +/*! + * @brief Store data from bit byte swapped shifter buffer. + * + * @param base base address + * @param shifterIdx shifter index + * + * @return bit byte swapped shifter buffer content + * SHIFTBUF[24:31], SHIFTBUF[16:23], SHIFTBUF[8:15], SHIFTBUF[0:7] + */ +static inline uint32_t FLEXIO_HAL_GetShifterBufferBitByteSwapped(FLEXIO_Type * base, uint32_t shifterIdx) +{ + return FLEXIO_RD_SHIFTBUFBBS(base, shifterIdx); +} + +/*! + * @brief Load data to bit byte swapped shifter buffer. + * + * @param base base address + * @param shifterIdx shifter index + * @param value Value to be load to bit byte swapped shifter buffer + */ +static inline void FLEXIO_HAL_SetShifterBufferBitByteSwapped(FLEXIO_Type * base, uint32_t shifterIdx, uint32_t value) +{ + FLEXIO_WR_SHIFTBUFBBS(base, shifterIdx, value); +} + +/*------------------------------------------------------------------------------ + * FLEXIO_SHIFTBUFBYSn - Shifter Buffer N Byte Swapped Register + *----------------------------------------------------------------------------*/ +/*! + * @brief Store data from byte swapped shifter buffer. + * + * @param base base address + * @param shifterIdx shifter index + * + * @return bit byte swapped shifter buffer content + * SHIFTBUF[7:0], SHIFTBUF[15:8], SHIFTBUF[23:16], SHIFTBUF[31:24] + */ +static inline uint32_t FLEXIO_HAL_GetShifterBufferByteSwapped(FLEXIO_Type * base, uint32_t shifterIdx) +{ + return FLEXIO_RD_SHIFTBUFBYS(base, shifterIdx); +} + +/*! + * @brief Load data to byte swapped shifter buffer. + * + * @param base base address + * @param shifterIdx shifter index + * @param value Value to be load to byte swapped shifter buffer + */ +static inline void FLEXIO_HAL_SetShifterBufferByteSwapped(FLEXIO_Type * base, uint32_t shifterIdx, uint32_t value) +{ + FLEXIO_WR_SHIFTBUFBYS(base, shifterIdx, value); +} + +/*------------------------------------------------------------------------------ + * FLEXIO_SHIFTBUFBISn - Shifter Buffer N Bit Swapped Register + *----------------------------------------------------------------------------*/ +/*! + * @brief Store data from bit swapped shifter buffer. + * + * @param base base address + * @param shifterIdx shifter index + * + * @return bit swapped shifter buffer content + * SHIFTBUF[0:31] + */ +static inline uint32_t FLEXIO_HAL_GetShifterBufferBitSwapped(FLEXIO_Type * base, uint32_t shifterIdx) +{ + return FLEXIO_RD_SHIFTBUFBIS(base, shifterIdx); +} + +/*! + * @brief Load data to Bit swapped shifter buffer. + * + * @param base base address + * @param shifterIdx shifter index + * @param value Value to be load to Bit swapped shifter buffer + */ +static inline void FLEXIO_HAL_SetShifterBufferBitSwapped(FLEXIO_Type * base, uint32_t shifterIdx, uint32_t value) +{ + FLEXIO_WR_SHIFTBUFBIS(base, shifterIdx, value); +} + +/*! + * @brief Restore the FlexIO peripheral to reset state. + * + * @param base base address + */ +void FLEXIO_HAL_Init(FLEXIO_Type * base); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif +#endif /* __FSL_FLEXIO_HAL_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_flexio_i2c_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_flexio_i2c_hal.h new file mode 100755 index 0000000..d0c2949 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_flexio_i2c_hal.h @@ -0,0 +1,286 @@ +/* + * Copyright (c) 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_FLEXIO_I2C_HAL_H__ +#define __FSL_FLEXIO_I2C_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> + +#include "fsl_flexio_hal.h" +#if FSL_FEATURE_SOC_FLEXIO_COUNT + +/*! + * @addtogroup flexio_i2c_hal + * @{ + */ + +/*! + * @brief Define structure of configuring the flexio i2c device. + */ +typedef struct FlexioI2cDev +{ + FLEXIO_Type * flexioBase; /*!< FlexIO module base pointer. */ + + uint32_t sdaPinIdx; /*!< Pin index for I2C SDA in FlexIO. */ + uint32_t sckPinIdx; /*!< Pin index for I2C SCK in FlexIO. */ + + uint32_t shifterIdx[2]; /*!< Shifter index used for I2C in FlexIO. */ + uint32_t timerIdx[2]; /*!< Timer index used for I2C in FlexIO. */ +} flexio_i2c_dev_t; + +/*! + * @brief Define structure of configuring the flexio i2c bus for master. + */ +typedef struct FlexioI2cMasterConfig +{ + uint32_t flexioBusClk; /*!< FlexIO bus clock frequency in Hz. */ + uint32_t baudrate; /*!< I2C xfer bandrate in bps. */ + uint32_t xferWordCount; /*!< Word count for one transfer frame. */ +} flexio_i2c_master_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/*--------------------------------------------------------------------------- + * Configure. + *-------------------------------------------------------------------------*/ +/*! + * @brief Configure the flexio working as i2c master device. + * + * @param devPtr Pointer to the device. + * @param configPtr Pointer to configuration structure. + * @return Execution status. + */ +flexio_status_t FLEXIO_I2C_HAL_ConfigMaster(flexio_i2c_dev_t *devPtr, const flexio_i2c_master_config_t *configPtr); + +/*! + * @brief Configure the count of words for each frame. + * + * When using flexio_i2c_master, each frame's length should be configured + * before sending any word. Of course, when calling the FLEXIO_I2C_HAL_ConfigMaster(), + * user can set the "configPtr->xferWrodCount" to set word count. However, this + * API could provide the light-weight setting without changing any other settings. + * + * @param devPtr Pointer to the device. + * @param count Word count for each frame. + * @return Execution status. + */ +flexio_status_t FLEXIO_I2C_HAL_ConfigXferWordCountOnce(flexio_i2c_dev_t *devPtr, uint32_t count); + +/*--------------------------------------------------------------------------- + * Tx. + *-------------------------------------------------------------------------*/ +/*! + * @brief Get the flag if the rx buffer is empty. + * + * @param devPtr Pointer to the device. + * @return Assertion of the event. + */ +bool FLEXIO_I2C_HAL_GetTxBufferEmptyFlag(flexio_i2c_dev_t *devPtr); + +/*! + * @brief Clear the flag of tx buffer empty manually. + * + * @param devPtr Pointer to the device. + */ +void FLEXIO_I2C_HAL_ClearTxBufferEmptyFlag(flexio_i2c_dev_t *devPtr); + +/*! + * @brief Switch on/off the interrupt for tx buffer is empty. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_I2C_HAL_SetTxBufferEmptyIntCmd(flexio_i2c_dev_t *devPtr, bool enable); + +/*! + * @brief Get the tx error flag. + * + * @param devPtr Pointer to the device. + * @return Assertion of the event. + */ +bool FLEXIO_I2C_HAL_GetTxErrFlag(flexio_i2c_dev_t *devPtr); + +/*! + * @brief Clear the tx error flag manually. + * + * @param devPtr Pointer to the device. + */ +void FLEXIO_I2C_HAL_ClearTxErrFlag(flexio_i2c_dev_t *devPtr); + +/*! + * @brief Switch on/off the interrupt for tx error. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_I2C_HAL_SetTxErrIntCmd(flexio_i2c_dev_t *devPtr, bool enable); + +/*! + * @brief Put data into tx buffer. + * + * @param devPtr Pointer to the device. + * @param dat Sending data. + */ +void FLEXIO_I2C_HAL_PutData(flexio_i2c_dev_t *devPtr, uint32_t dat); + +/*! + * @brief Put data into tx buffer when empty. + * + * @param devPtr Pointer to the device. + * @param dat Sending data. + */ +void FLEXIO_I2C_HAL_PutDataPolling(flexio_i2c_dev_t *devPtr, uint32_t dat); + +/*! + * @brief Switch on/off the tx DMA support. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_I2C_HAL_SetTxDmaCmd(flexio_i2c_dev_t *devPtr, bool enable); + +/*! + * @brief Get address of tx buffer when using DMA. + * + * @param devPtr Pointer to the device. + * @return Address of tx buffer. + */ +uint32_t FLEXIO_I2C_HAL_GetTxBufferAddr(flexio_i2c_dev_t *devPtr); + +/*--------------------------------------------------------------------------- + * Rx. + *-------------------------------------------------------------------------*/ +/*! + * @brief Get the flag that rx buffer is full. + * + * @param devPtr Pointer to the device. + * @return Assertion of the event. + */ +bool FLEXIO_I2C_HAL_GetRxBufferFullFlag(flexio_i2c_dev_t *devPtr); + +/*! + * @brief Clear the rx buffer empty flag manually. + * + * @param devPtr Pointer to the device. + */ +void FLEXIO_I2C_HAL_ClearRxBufferFullFlag(flexio_i2c_dev_t *devPtr); + +/*! + * @brief Switch on/off the interrupt for rx buffer is full. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_I2C_HAL_SetRxBufferFullIntCmd(flexio_i2c_dev_t *devPtr, bool enable); + +/*! + * @brief Get the rx error flag. + * + * @param devPtr Pointer to the device. + * @return Assertion of the event. + */ +bool FLEXIO_I2C_HAL_GetRxErrFlag(flexio_i2c_dev_t *devPtr); + +/*! + * @brief Clear the rx error flag manually. + * + * @param devPtr Pointer to the device. + */ +void FLEXIO_I2C_HAL_ClearRxErrFlag(flexio_i2c_dev_t *devPtr); + +/*! + * @brief Switch on/off the interrupt for rx error. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_I2C_HAL_SetRxErrIntCmd(flexio_i2c_dev_t *devPtr, bool enable); + +/*! + * @brief Get the data from tx buffer. + * + * @param devPtr Pointer to the device. + * @return Data from rx buffer. + */ +uint32_t FLEXIO_I2C_HAL_GetData(flexio_i2c_dev_t *devPtr); + +/*! + * @brief Get the data from tx buffer when full. + * + * @param devPtr Pointer to the device. + * @return Data from rx buffer. + */ +uint32_t FLEXIO_I2C_HAL_GetDataPolling(flexio_i2c_dev_t *devPtr); + +/*! + * @brief Switch on/off the rx DMA support. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_I2C_HAL_SetRxDmaCmd(flexio_i2c_dev_t *devPtr, bool enable); + +/*! + * @brief Get the address the of rx buffer. + * + * @param devPtr Pointer to the device. + * @return Address of rx buffer. + */ +uint32_t FLEXIO_I2C_HAL_GetRxBufferAddr(flexio_i2c_dev_t *devPtr); + +/*! + * @brief Configure the next sending would generate NACK condition. + * + * @param devPtr Pointer to the device. + */ +void FLEXIO_I2C_HAL_ConfigSendNAck(flexio_i2c_dev_t *devPtr); + +/*! + * @brief Configure the next sending would generate ACK condition. + * + * @param devPtr Pointer to the device. + */ +void FLEXIO_I2C_HAL_ConfigSendAck(flexio_i2c_dev_t *devPtr); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif +#endif /* __FSL_FLEXIO_I2C_HAL_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_flexio_i2s_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_flexio_i2s_hal.h new file mode 100755 index 0000000..c23b262 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_flexio_i2s_hal.h @@ -0,0 +1,300 @@ +/* + * Copyright (c) 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_FLEXIO_I2S_HAL_H__ +#define __FSL_FLEXIO_I2S_HAL_H__ + +#include "fsl_flexio_hal.h" +#if FSL_FEATURE_SOC_FLEXIO_COUNT + +/*! + * @addtogroup flexio_i2s_hal + * @{ + */ + +/*! + * @brief Define type of FlexIO I2S device. + */ +typedef struct FlexioI2sDev +{ + FLEXIO_Type * flexioBase; /*!< FlexIO module base address. */ + /* User-defined pin for I2S. */ + uint32_t txPinIdx; /*!< output for cases of both master and slave. */ + uint32_t rxPinIdx; /*!< input for cases of both master and slave. */ + uint32_t sckPinIdx; /*!< output for master, input for slave. */ + uint32_t wsPinIdx; /*!< output for master, input for slave. */ + /* Internal hardware resource. */ + uint32_t shifterIdx[2]; /*!< Shifter index used for I2S in FlexIO. */ + uint32_t timerIdx[2]; /*!< Timer index used for I2S in FlexIO. */ +} flexio_i2s_dev_t; + +/*! + * @brief Define type of I2S master device configuration structure. + */ +typedef struct FlexioI2sMasterConfig +{ + uint32_t flexioBusClk; /*!< Flexio bus clock in Hz. */ + uint32_t bitClk; /*!< Bit clock in Hz. */ + uint32_t bitCount; /*!< Bit count for each work. */ +} flexio_i2s_master_config_t; + +/*! + * @brief Define type of I2S slave device configuration structure. + */ +typedef struct FlexioI2sSlaveConfig +{ + uint32_t bitCount; /*!< Bit count for each work. */ +} flexio_i2s_slave_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/*--------------------------------------------------------------------------- + * Configure. + *-------------------------------------------------------------------------*/ +/*! + * @brief Configure the flexio working as i2s master device. + * + * @param devPtr Pointer to the device. + * @param configPtr Pointer to configuration structure. + * @return Execution status. + */ +flexio_status_t FLEXIO_I2S_HAL_Configure_Master( + flexio_i2s_dev_t *devPtr, const flexio_i2s_master_config_t *configPtr); + +/*! + * @brief Configure the flexio working as i2s slave device. + * + * @param devPtr Pointer to the device. + * @param configPtr Pointer to configuration structure. + * @return Execution status. + */ +flexio_status_t FLEXIO_I2S_HAL_Configure_Slave( + flexio_i2s_dev_t *devPtr, const flexio_i2s_slave_config_t *configPtr); + +/*--------------------------------------------------------------------------- + * Tx. + *-------------------------------------------------------------------------*/ +/* Status flag and interrupt. */ +/*! + * @brief Get the flag that tx buffer is empty. + * + * @param devPtr Pointer to the device. + * @return Assertion of the event. + */ +bool FLEXIO_I2S_HAL_GetTxBufferEmptyFlag(flexio_i2s_dev_t *devPtr); + +/*! + * @brief Clear the tx buffer empty flag manually. + * + * @param devPtr Pointer to the device. + */ +void FLEXIO_I2S_HAL_ClearTxBufferEmptyFlag(flexio_i2s_dev_t *devPtr); + +/*! + * @brief Switch on/off the interrupt for tx buffer empty. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_I2S_HAL_SetTxBufferEmptyIntCmd(flexio_i2s_dev_t *devPtr, bool enable); + +/*! + * @brief Get the current setting of interrupt switcher. + * + * @param devPtr Pointer to the device. + * @return The setting of event. + */ +bool FLEXIO_I2S_HAL_GetTxBufferEmptyIntCmd(flexio_i2s_dev_t *devPtr); + +/* Error flag and interrupt. */ +/*! + * @brief Get the rx error flag. + * + * @param devPtr Pointer to the device. + * @return Assertion of the event. + */ +bool FLEXIO_I2S_HAL_GetTxErrFlag(flexio_i2s_dev_t *devPtr); + +/*! + * @brief Clear the tx error flag manually. + * + * @param devPtr Pointer to the device. + */ +void FLEXIO_I2S_HAL_ClearTxErrFlag(flexio_i2s_dev_t *devPtr); + +/*! + * @brief Switch on/off the interrupt for tx error. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_I2S_HAL_SetTxErrIntCmd(flexio_i2s_dev_t *devPtr, bool enable); + +/* Data buffer. */ +/*! + * @brief Put the data into tx buffer. + * + * @param devPtr Pointer to the device. + * @param dat Sending data. + */ +void FLEXIO_I2S_HAL_PutData(flexio_i2s_dev_t *devPtr, uint32_t dat); + +/*! + * @brief Put the data into tx buffer when empty. + * + * @param devPtr Pointer to the device. + * @param dat Sending data. + */ +void FLEXIO_I2S_HAL_PutDataPolling(flexio_i2s_dev_t *devPtr, uint32_t dat); + +/* DMA. */ +/*! + * @brief Switch on/off the tx DMA support. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_I2S_HAL_SetTxDmaCmd(flexio_i2s_dev_t *devPtr, bool enable); + +/*! + * @brief Get the address of tx buffer when using DMA. + * + * @param devPtr Pointer to the device. + * @return Address of tx buffer. + */ +uint32_t FLEXIO_I2S_HAL_GetTxBufferAddr(flexio_i2s_dev_t *devPtr); + +/*--------------------------------------------------------------------------- + * Rx. + *-------------------------------------------------------------------------*/ +/* Status flag and interrupt. */ +/*! + * @brief Get the flag if the rx buffer is full. + * + * @param devPtr Pointer to the device. + * @return Assertion of the event. + */ +bool FLEXIO_I2S_HAL_GetRxBufferFullFlag(flexio_i2s_dev_t *devPtr); + +/*! + * @brief Clear the rx buffer full flag. + * + * @param devPtr Pointer to the device. + */ +void FLEXIO_I2S_HAL_ClearRxBufferFullFlag(flexio_i2s_dev_t *devPtr); + +/*! + * @brief Switch on/off the interrupt for rx buffer full. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_I2S_HAL_SetRxBufferFullIntCmd(flexio_i2s_dev_t *devPtr, bool enable); + +/*! + * @brief Get the current setting of tx buffer full interrupt. + * + * @param devPtr Pointer to the device. + * @return Assertion of event. + */ +bool FLEXIO_I2S_HAL_GetRxBufferFullIntCmd(flexio_i2s_dev_t *devPtr); + +/* Error flag and interrupt. */ +/*! + * @brief Get the flag if rx error. + * + * @param devPtr Pointer to the device. + * @return Assertion of the event. + */ +bool FLEXIO_I2S_HAL_GetRxErrFlag(flexio_i2s_dev_t *devPtr); + +/*! + * @brief Clear the rx error flag manually. + * + * @param devPtr Pointer to the device. + */ +void FLEXIO_I2S_HAL_ClearRxErrFlag(flexio_i2s_dev_t *devPtr); + +/*! + * @brief Switch on/off the interrupt for rx error event. + * + * @param devPtr Pointer to the device. + * @param enable Swichter to the event. + */ +void FLEXIO_I2S_HAL_SetRxErrIntCmd(flexio_i2s_dev_t *devPtr, bool enable); + +/* Data buffer. */ +/*! + * @brief Get the data from rx buffer. + * + * @param devPtr Pointer to the device. + * @return Reading data. + */ +uint32_t FLEXIO_I2S_HAL_GetData(flexio_i2s_dev_t *devPtr); + +/*! + * @brief Get the data from rx buffer when full. + * + * @param devPtr Pointer to the device. + * @return Reading data. + */ +uint32_t FLEXIO_I2S_HAL_GetDataPolling(flexio_i2s_dev_t *devPtr); + +/* DMA. */ +/*! + * @brief Switch on/off the rx DMA support. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_I2S_HAL_SetRxDmaCmd(flexio_i2s_dev_t *devPtr, bool enable); + +/*! + * @brief Get the address of rx buffer when using DMA. + * + * @param devPtr Pointer to the device. + * @return Address of rx buffer. + */ +uint32_t FLEXIO_I2S_HAL_GetRxBufferAddr(flexio_i2s_dev_t *devPtr); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif +#endif /* __FSL_FLEXIO_I2S_HAL_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_flexio_spi_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_flexio_spi_hal.h new file mode 100755 index 0000000..81e5bab --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_flexio_spi_hal.h @@ -0,0 +1,326 @@ +/* + * Copyright (c) 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_FLEXIO_SPI_HAL_H__ +#define __FSL_FLEXIO_SPI_HAL_H__ + +#include "fsl_flexio_hal.h" + +/*! + * @addtogroup flexio_spi_hal + * @{ + */ + +/*! + * @brief Define structure of configuring the flexio spi device. + */ +typedef struct +{ + FLEXIO_Type * flexioBase; /*!< FlexIO module base address. */ + /* User-defined pin for SPI master. */ + uint32_t txPinIdx; /*!< Output pin index. */ + uint32_t rxPinIdx; /*!< Input pin index. */ + uint32_t sclkPinIdx; /*!< Clock line, output for master, input for slave. */ + uint32_t csnPinIdx; /*!< Chip select line, output for master, input for slave. */ + /* Internal hardware resource. */ + uint32_t shifterIdx[2]; /*!< Shifter index. */ + uint32_t timerIdx[2]; /*!< Timer index. + * timer 0 is available for both master and slave. + * timer 1 would be only available for master + * and not used in slave mode. */ +} flexio_spi_dev_t; + +/*! + * @brief Define structure of configuring the flexio spi bus when master. + */ +typedef struct +{ + uint32_t flexioBusClk; /*!< Clock frequency of flexio bus. */ + uint32_t baudrate; /*!< Baudrate for spi bus. */ + uint32_t bitCount; /*!< Bit count for each word. */ + bool cphaOneEnable; /*!< The phase of spi. */ +} flexio_spi_master_config_t; + +/*! + * @brief Define structure of configuring the flexio spi bus when slave. + */ +typedef struct +{ + uint32_t bitCount; /*!< Bit count for each word. */ + bool cphaOneEnable; /*!< The phase of spi. */ +} flexio_spi_slave_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/*--------------------------------------------------------------------------- + * Configure. + *-------------------------------------------------------------------------*/ +/*! + * @brief Configure the flexio working as spi master. + * + * @param devPtr Pointer to the device. + * @param configPtr Pointer to the configuration structure. + * @return Execution status. + */ +flexio_status_t FLEXIO_SPI_HAL_ConfigMaster(flexio_spi_dev_t *devPtr, const flexio_spi_master_config_t *configPtr); + +/*! + * @brief Configure the flexio working as spi slave. + * + * @param devPtr Pointer to the device. + * @param configPtr Pointer to the configuration structure. + * @return Execution status. + */ +flexio_status_t FLEXIO_SPI_HAL_ConfigSlave(flexio_spi_dev_t *devPtr, const flexio_spi_slave_config_t *configPtr); + +/*--------------------------------------------------------------------------- + * Tx. + *-------------------------------------------------------------------------*/ +/*! + * @brief Get the flag if the tx buffer is empty. + * + * @param devPtr Pointer to the device. + * @return Assertion of the event. + */ +bool FLEXIO_SPI_HAL_GetTxBufferEmptyFlag(flexio_spi_dev_t *devPtr); + +/*! + * @brief Clear the flag that tx buffer is empty. + * + * @param devPtr Pointer to the device. + */ +void FLEXIO_SPI_HAL_ClearTxBufferEmptyFlag(flexio_spi_dev_t *devPtr); + +/*! + * @brief Switch on/off the interrupt for event of tx buffer empty. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_SPI_HAL_SetTxBufferEmptyIntCmd(flexio_spi_dev_t *devPtr, bool enable); + +/*! + * @brief Get the flag of tx error. + * + * @param devPtr Pointer to the device. + * @return Assertion of the event. + */ +bool FLEXIO_SPI_HAL_GetTxErrFlag(flexio_spi_dev_t *devPtr); + +/*! + * @brief Clear the flag of tx error manually. + * + * @param devPtr Pointer to the device. + */ +void FLEXIO_SPI_HAL_ClearTxErrFlag(flexio_spi_dev_t *devPtr); + +/*! + * @brief Switch on/off the interrupt for tx error event. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_SPI_HAL_SetTxErrIntCmd(flexio_spi_dev_t *devPtr, bool enable); + +/*! + * @brief Put the data to tx buffer as MSB transfer. + * + * @param devPtr Pointer to the device. + * @param dat Sending data. + */ +void FLEXIO_SPI_HAL_PutDataMSB(flexio_spi_dev_t *devPtr, uint32_t dat); + +/*! + * @brief Put the data to tx buffer as MSB transfer when empty. + * + * @param devPtr Pointer to the device. + * @param dat Sending data. + */ +void FLEXIO_SPI_HAL_PutDataMSBPolling(flexio_spi_dev_t *devPtr, uint32_t dat); + +/*! + * @brief Put the data to tx buffer as LSB transfer. + * + * @param devPtr Pointer to the device. + * @param dat Sending data. + */ +void FLEXIO_SPI_HAL_PutDataLSB(flexio_spi_dev_t *devPtr, uint32_t dat); + +/*! + * @brief Put the data to tx buffer as LSB transfer when empty. + * + * @param devPtr Pointer to the device. + * @param dat Sending data. + */ +void FLEXIO_SPI_HAL_PutDataLSBPolling(flexio_spi_dev_t *devPtr, uint32_t dat); + +/*! + * @brief Switch on/off the DMA support for tx event. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_SPI_HAL_SetTxDmaCmd(flexio_spi_dev_t *devPtr, bool enable); + +/*! + * @brief Get the tx MSB buffer's register for DMA use. + * + * @param devPtr Pointer to the device. + * @return Address of tx MSB buffer. + */ +uint32_t FLEXIO_SPI_HAL_GetTxBufferMSBAddr(flexio_spi_dev_t *devPtr); + +/*! + * @brief Get the tx LSB buffer's register for DMA use. + * + * @param devPtr Pointer to the device. + * @return Address of tx LSB buffer. + */ +uint32_t FLEXIO_SPI_HAL_GetTxBufferLSBAddr(flexio_spi_dev_t *devPtr); + +/*--------------------------------------------------------------------------- + * Rx. + *-------------------------------------------------------------------------*/ + +/*! + * @brief Get the flag if the rx buffer is full. + * + * @param devPtr Pointer to the device. + * @return Assertion of event. + */ +bool FLEXIO_SPI_HAL_GetRxBufferFullFlag(flexio_spi_dev_t *devPtr); + +/*! + * @brief Clear the flag of rx buffer full manually. + * + * @param devPtr Pointer to the device. + */ +void FLEXIO_SPI_HAL_ClearRxBufferFullFlag(flexio_spi_dev_t *devPtr); + +/*! + * @brief Switch on/off the interrupt of rx buffer full event. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_SPI_HAL_SetRxBufferFullIntCmd(flexio_spi_dev_t *devPtr, bool enable); + +/*! + * @brief Get the flag of rx error. + * + * @param devPtr Pointer to the device. + * @return Assertion of event. + */ +bool FLEXIO_SPI_HAL_GetRxErrFlag(flexio_spi_dev_t *devPtr); + +/*! + * @brief Clear the flag of rx error manually. + * + * @param devPtr Pointer to the device. + */ +void FLEXIO_SPI_HAL_ClearRxErrFlag(flexio_spi_dev_t *devPtr); + +/*! + * @brief Switch on/off the interrupt of the rx error event. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_SPI_HAL_SetRxErrIntCmd(flexio_spi_dev_t *devPtr, bool enable); + +/*! + * @brief Get the data from rx MSB buffer. + * + * @param devPtr Pointer to the device. + * @return Data from rx MSB buffer. + */ +uint32_t FLEXIO_SPI_HAL_GetDataMSB(flexio_spi_dev_t *devPtr); + +/*! + * @brief Get the data from rx MSB buffer when full. + * + * @param devPtr Pointer to the device. + * @return Data from rx MSB buffer. + */ +uint32_t FLEXIO_SPI_HAL_GetDataMSBPolling(flexio_spi_dev_t *devPtr); + +/*! + * @brief Get the data from rx LSB buffer. + * + * @param devPtr Pointer to the device. + * @return Data from rx LSB buffer. + */ +uint32_t FLEXIO_SPI_HAL_GetDataLSB(flexio_spi_dev_t *devPtr); + +/*! + * @brief Get the data from rx LSB buffer when full. + * + * @param devPtr Pointer to the device. + * @return Data from rx LSB buffer. + */ +uint32_t FLEXIO_SPI_HAL_GetDataLSBPolling(flexio_spi_dev_t *devPtr); + +/*! + * @brief Swtich on/off the DMA for rx event. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_SPI_HAL_SetRxDmaCmd(flexio_spi_dev_t *devPtr, bool enable); + +/*! + * @brief Get the address of rx MSB buffer. + * + * @param devPtr Pointer to the device. + * @return Address of rx MSB buffer. + */ +uint32_t FLEXIO_SPI_HAL_GetRxBufferMSBAddr(flexio_spi_dev_t *devPtr); + +/*! + * @brief Get the address of rx LSB buffer. + * + * @param devPtr Pointer to the device. + * @return Address of rx MSB buffer. + */ +uint32_t FLEXIO_SPI_HAL_GetRxBufferLSBAddr(flexio_spi_dev_t *devPtr); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* __FSL_FLEXIO_SPI_HAL_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_flexio_uart_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_flexio_uart_hal.h new file mode 100755 index 0000000..e7d86a3 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_flexio_uart_hal.h @@ -0,0 +1,306 @@ +/* + * Copyright (c) 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_FLEXIO_UART_HAL_H__ +#define __FSL_FLEXIO_UART_HAL_H__ + +#include "fsl_flexio_hal.h" +#if FSL_FEATURE_SOC_FLEXIO_COUNT + +/*! + * @addtogroup flexio_uart_hal + * @{ + */ + +/*! + * @brief Define structure of configuring the flexio uart tx device. + */ +typedef struct +{ + FLEXIO_Type * flexioBase; /*!< FlexIO module base address. */ + uint32_t txPinIdx; /*!< Pin index for UART Tx in FlexIO. */ + + uint32_t shifterIdx; /*!< Shifter index used for UART Tx in FlexIO. */ + uint32_t timerIdx; /*!< Timer index used for UART Tx in FlexIO. */ +} flexio_uart_tx_dev_t; + + /*! + * @brief Define structure of configuring the flexio uart rx device. + */ +typedef struct +{ + FLEXIO_Type * flexioBase; /*!< FlexIO module base address. */ + uint32_t rxPinIdx; /*!< Pin index for UART Rx in FlexIO. */ + + uint32_t shifterIdx; /*!< Shifter index used for UART Rx in FlexIO. */ + uint32_t timerIdx; /*!< Timer index used for UART Rx in FlexIO. */ +} flexio_uart_rx_dev_t; + +/*! + * @brief Define structure of configuring the flexio uart bus. + */ +typedef struct +{ + uint32_t flexioBusClk; /*!< FlexIO bus clock frequency in Hz. */ + uint32_t baudrate; /*!< UART xfer bandrate in bps. */ + uint32_t bitCount; /*!< UART xfer data length in bit. */ +} flexio_uart_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/****************************************************************************** + * UART Tx. + ******************************************************************************/ +/*! + * @brief Configure the flexio working as uart tx device. + * + * @param devPtr Pointer to the device. + * @param configPtr Pointer to configuration structure. + * @return Execution status. + */ +flexio_status_t FLEXIO_UART_Tx_HAL_Configure( + flexio_uart_tx_dev_t *devPtr, const flexio_uart_config_t *configPtr); + +/*! + * @brief Get the flag if the tx buffer is empty. + * + * @param devPtr Pointer to the device. + * @return The assertion of the event. + */ +bool FLEXIO_UART_Tx_HAL_GetTxBufferEmptyFlag(flexio_uart_tx_dev_t *devPtr); + +/*! + * @brief Clear the tx buffer empty flag manually. + * + * @param devPtr Pointer to the device. + */ +void FLEXIO_UART_Tx_HAL_ClearTxBufferEmptyFlag(flexio_uart_tx_dev_t *devPtr); + +/*! + * @brief Switch on/off the interrupt for buffer empty event. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_UART_Tx_HAL_SetTxBufferEmptyIntCmd(flexio_uart_tx_dev_t *devPtr, bool enable); + +/*! + * @brief Get the current setting for tx buffer empty event. + * + * @param devPtr Pointer to the device. + * @return Setting for the interrupt event. + */ +bool FLEXIO_UART_Tx_HAL_GetTxBufferEmptyIntCmd(flexio_uart_tx_dev_t *devPtr); + +/*! + * @brief Get the tx error flag. + * + * @param devPtr Pointer to the device. + * @return Assertion of the event. + */ +bool FLEXIO_UART_Tx_HAL_GetTxErrFlag(flexio_uart_tx_dev_t *devPtr); + +/*! + * @brief Clear the tx error flag manually. + * + * @param devPtr Pointer to the device. + */ +void FLEXIO_UART_Tx_HAL_ClearTxErrFlag(flexio_uart_tx_dev_t *devPtr); + +/*! + * @brief Switch on/off the interrupt for tx error event. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_UART_Tx_HAL_SetTxErrIntCmd(flexio_uart_tx_dev_t *devPtr, bool enable); + +/*! + * @brief Put the data into the tx buffer. + * + * @param devPtr Pointer to the device. + * @param dat Sending data. + */ +void FLEXIO_UART_Tx_HAL_PutData(flexio_uart_tx_dev_t *devPtr, uint32_t dat); + +/*! + * @brief Put the data into the tx buffer when empty. + * + * @param devPtr Pointer to the device. + * @param dat Sending data. + */ +void FLEXIO_UART_Tx_HAL_PutDataPolling(flexio_uart_tx_dev_t *devPtr, uint32_t dat); + +/*! + * @brief Send an array of data by flexio uart tx device. + * + * @param devPtr Pointer to the device. + * @param txBufPtr Pointer to the sending buffer. + * @param txLen Length of sending buffer. + */ +void FLEXIO_UART_Tx_HAL_SendDataPolling(flexio_uart_tx_dev_t *devPtr, uint32_t *txBufPtr, uint32_t txLen); + +/*! + * @brief Switch on/off the DMA on flexio uart tx device. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_UART_Tx_HAL_SetTxDmaCmd(flexio_uart_tx_dev_t *devPtr, bool enable); + +/*! + * @brief Get the tx buffer's address for DMA use. + * + * @param devPtr Pointer to the device. + * @return tx buffer's address. + */ +uint32_t FLEXIO_UART_Tx_HAL_GetTxBufferAddr(flexio_uart_tx_dev_t *devPtr); + +/****************************************************************************** + * UART Rx. +******************************************************************************/ +/*! + * @brief Configure the flexio working as uart rx device. + * + * @param devPtr Pointer to the device. + * @param configPtr Pointer to configuration structure. + */ +flexio_status_t FLEXIO_UART_Rx_HAL_Configure( + flexio_uart_rx_dev_t *devPtr, const flexio_uart_config_t *configPtr); + +/*! + * @brief Get the flag if the rx buffer is full. + * + * @param devPtr Pointer to the device. + * @return The assertion of the event. + */ +bool FLEXIO_UART_Rx_HAL_GetRxBufferFullFlag(flexio_uart_rx_dev_t *devPtr); + +/*! + * @brief Clear the flag that rx buffer is full manually. + * + * @param devPtr Pointer to the device. + */ +void FLEXIO_UART_Rx_HAL_ClearRxBufferFullFlag(flexio_uart_rx_dev_t *devPtr); + +/*! + * @brief Switcher on/off the interrupt for rx buffer full event. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_UART_Rx_HAL_SetRxBufferFullIntCmd(flexio_uart_rx_dev_t *devPtr, bool enable); + +/*! + * @brief Get the current setting if interrupt is enabled. + * + * @param devPtr Pointer to the device. + * @return Assertion of the event. + */ +bool FLEXIO_UART_Rx_HAL_GetRxBufferFullIntCmd(flexio_uart_rx_dev_t *devPtr); + +/*! + * @brief Get the flag of rx error event. + * + * @param devPtr Pointer to the device. + * @return Assertion of the event. + */ +bool FLEXIO_UART_Rx_HAL_GetRxErrFlag(flexio_uart_rx_dev_t *devPtr); + +/*! + * @brief Clear the flag of rx error event manually. + * + * @param devPtr Pointer to the device. + */ +void FLEXIO_UART_Rx_HAL_ClearRxErrFlag(flexio_uart_rx_dev_t *devPtr); + +/*! + * @brief Switch on/off the interrupt for rx error event. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_UART_Rx_HAL_SetRxErrIntCmd(flexio_uart_rx_dev_t *devPtr, bool enable); + +/*! + * @brief Get the data from rx buffer. + * + * @param devPtr Pointer to the device. + * @return Data from the rx buffer. + */ +uint32_t FLEXIO_UART_Rx_HAL_GetData(flexio_uart_rx_dev_t *devPtr); + +/*! + * @brief Get the data from rx buffer when full. + * + * @param devPtr Pointer to the device. + * @return Data from the rx buffer. + */ +uint32_t FLEXIO_UART_Rx_HAL_GetDataPolling(flexio_uart_rx_dev_t *devPtr); + +/*! + * @brief Receive an array of data through the rx buffer. + * + * @param devPtr Pointer to the device. + * @param rxBufPtr Pointer to the rx buffer. + * @param rxLen Length of the rx buffer. + */ +void FLEXIO_UART_Rx_HAL_ReceiveDataPolling(flexio_uart_rx_dev_t *devPtr, uint32_t *rxBufPtr, uint32_t rxLen); + +/*! + * @brief Switch on/off the rx DMA support. + * + * @param devPtr Pointer to the device. + * @param enable Switcher to the event. + */ +void FLEXIO_UART_Rx_HAL_SetRxDmaCmd(flexio_uart_rx_dev_t *devPtr, bool enable); + +/*! + * @brief Get the rx buffer's address for DMA use. + * + * @param devPtr Pointer to the device. + * @return rx buffer's address. + */ +uint32_t FLEXIO_UART_Rx_HAL_GetRxBufferAddr(flexio_uart_rx_dev_t *devPtr); + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif +#endif /* __FSL_FLEXIO_UART_HAL_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_ftm_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_ftm_hal.h new file mode 100755 index 0000000..ef88faf --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_ftm_hal.h @@ -0,0 +1,1532 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#if !defined(__FSL_FTM_HAL_H__) +#define __FSL_FTM_HAL_H__ + +#include "fsl_device_registers.h" +#include <stdbool.h> +#include <assert.h> + +#if FSL_FEATURE_SOC_FTM_COUNT + +/*! + * @addtogroup ftm_hal + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define CHAN0_IDX (0U) /*!< Channel number for CHAN0.*/ +#define CHAN1_IDX (1U) /*!< Channel number for CHAN1.*/ +#define CHAN2_IDX (2U) /*!< Channel number for CHAN2.*/ +#define CHAN3_IDX (3U) /*!< Channel number for CHAN3.*/ +#define CHAN4_IDX (4U) /*!< Channel number for CHAN4.*/ +#define CHAN5_IDX (5U) /*!< Channel number for CHAN5.*/ +#define CHAN6_IDX (6U) /*!< Channel number for CHAN6.*/ +#define CHAN7_IDX (7U) /*!< Channel number for CHAN7.*/ + +#define FTM_COMBINE_CHAN_CTRL_WIDTH (8U) + +/*! @brief FlexTimer clock source selection*/ +typedef enum _ftm_clock_source +{ + kClock_source_FTM_None = 0, /*!< @internal gui name="None" */ + kClock_source_FTM_SystemClk, /*!< @internal gui name="System clock" */ + kClock_source_FTM_FixedClk, /*!< @internal gui name="Fixed clock" */ + kClock_source_FTM_ExternalClk /*!< @internal gui name="External clock" */ +}ftm_clock_source_t; + +/*! @brief FlexTimer counting mode selection */ +typedef enum _ftm_counting_mode +{ + kCounting_FTM_UP = 0, + kCounting_FTM_UpDown +}ftm_counting_mode_t; + +/*! @brief FlexTimer pre-scaler factor selection for the clock source*/ +typedef enum _ftm_clock_ps +{ + kFtmDividedBy1 = 0, /*!< @internal gui name="Divide by 1" */ + kFtmDividedBy2 , /*!< @internal gui name="Divide by 2" */ + kFtmDividedBy4 , /*!< @internal gui name="Divide by 4" */ + kFtmDividedBy8, /*!< @internal gui name="Divide by 8" */ + kFtmDividedBy16, /*!< @internal gui name="Divide by 16" */ + kFtmDividedBy32, /*!< @internal gui name="Divide by 32" */ + kFtmDividedBy64, /*!< @internal gui name="Divide by 64" */ + kFtmDividedBy128 /*!< @internal gui name="Divide by 128" */ +}ftm_clock_ps_t; + +/*! @brief FlexTimer pre-scaler factor for the deadtime insertion*/ +typedef enum _ftm_deadtime_ps +{ + kFtmDivided1 = 1, /*!< @internal gui name="Divide by 1" */ + kFtmDivided4, /*!< @internal gui name="Divide by 4" */ + kFtmDivided16, /*!< @internal gui name="Divide by 16" */ +}ftm_deadtime_ps_t; + +/*! @brief FlexTimer operation mode, capture, output, dual */ +typedef enum _ftm_config_mode_t +{ + kFtmInputCapture, /*!< @internal gui name="Input capture" */ + kFtmOutputCompare, /*!< @internal gui name="Output compare" */ + kFtmEdgeAlignedPWM, /*!< @internal gui name="Edge aligned PWM" */ + kFtmCenterAlignedPWM, /*!< @internal gui name="Center aligned PWM" */ + kFtmCombinedPWM, /*!< @internal gui name="Combined PWM" */ + kFtmDualEdgeCapture /*!< @internal gui name="Dual edge capture" */ +}ftm_config_mode_t; + +/*! @brief FlexTimer input capture edge mode, rising edge, or falling edge */ +typedef enum _ftm_input_capture_edge_mode_t +{ + kFtmRisingEdge = 1, + kFtmFallingEdge, + kFtmRisingAndFalling +}ftm_input_capture_edge_mode_t; + +/*! @brief FlexTimer output compare edge mode. Toggle, clear or set.*/ +typedef enum _ftm_output_compare_edge_mode_t +{ + kFtmToggleOnMatch = 1, + kFtmClearOnMatch, + kFtmSetOnMatch +}ftm_output_compare_edge_mode_t; + +/*! @brief FlexTimer PWM output pulse mode, high-true or low-true on match up */ +typedef enum _ftm_pwm_edge_mode_t +{ + kFtmHighTrue = 0, /*!< @internal gui name="High true" */ + kFtmLowTrue /*!< @internal gui name="Low true" */ +}ftm_pwm_edge_mode_t; + +/*! @brief FlexTimer dual capture edge mode, one shot or continuous */ +typedef enum _ftm_dual_capture_edge_mode_t +{ + kFtmOneShot = 0, + kFtmContinuous +}ftm_dual_capture_edge_mode_t; + +/*! @brief FlexTimer quadrature decode modes, phase encode or count and direction mode */ +typedef enum _ftm_quad_decode_mode_t +{ + kFtmQuadPhaseEncode = 0, + kFtmQuadCountAndDir +}ftm_quad_decode_mode_t; + +/*! @brief FlexTimer quadrature phase polarities, normal or inverted polarity */ +typedef enum _ftm_quad_phase_polarity_t +{ + kFtmQuadPhaseNormal = 0, /*!< Phase A input signal is not inverted before identifying the rising and falling edges of this signal. @internal gui name="Normal polarity" */ + kFtmQuadPhaseInvert /*!< Phase A input signal is inverted before identifying the rising and falling edges of this signal. @internal gui name="Inverted polarity" */ +}ftm_quad_phase_polarity_t; + +/*! @brief FlexTimer sync options to update registers with buffer */ +typedef enum _ftm_sync_method_t +{ + kFtmUseSoftwareTrig = (1U << FTM_SYNC_SWSYNC_SHIFT), + kFtmUseHardwareTrig0 = (1U << FTM_SYNC_TRIG0_SHIFT), + kFtmUseHardwareTrig1 = (1U << FTM_SYNC_TRIG1_SHIFT), + kFtmUseHardwareTrig2 = (1U << FTM_SYNC_TRIG2_SHIFT) +}ftm_sync_method_t; + +/*! @brief Options for the FlexTimer behaviour in BDM Mode */ +typedef enum _ftm_bdm_mode_t +{ + kFtmBdmMode_00 = 0, + /*!< FTM counter stopped, CH(n)F bit can be set, FTM channels in functional mode, writes to MOD,CNTIN and C(n)V registers bypass the register buffers. @internal gui name="Mode 0" */ + kFtmBdmMode_01, + /*!< FTM counter stopped, CH(n)F bit is not set, FTM channels outputs are forced to their safe value , writes to MOD,CNTIN and C(n)V registers bypass the register buffers. @internal gui name="Mode 1" */ + kFtmBdmMode_10, + /*!< FTM counter stopped, CH(n)F bit is not set, FTM channels outputs are frozen when chip enters in BDM mode, writes to MOD,CNTIN and C(n)V registers bypass the register buffers. @internal gui name="Mode 2" */ + kFtmBdmMode_11 + /*!< FTM counter in functional mode, CH(n)F bit can be set, FTM channels in functional mode, writes to MOD,CNTIN and C(n)V registers is in fully functional mode. @internal gui name="Mode 3" */ +}ftm_bdm_mode_t; + +/*! @brief FTM status */ +typedef enum _ftm_status { + kStatusFtmSuccess = 0U, /*!< FTM success status.*/ + kStatusFtmError = 1U, /*!< FTM error status.*/ +} ftm_status_t; + +/*! @brief FlexTimer edge mode*/ +typedef union _ftm_edge_mode_t +{ + ftm_input_capture_edge_mode_t input_capture_edge_mode; + ftm_output_compare_edge_mode_t output_compare_edge_mode; + ftm_pwm_edge_mode_t ftm_pwm_edge_mode; + ftm_dual_capture_edge_mode_t ftm_dual_capture_edge_mode; +}ftm_edge_mode_t; + +/*! + * @brief FlexTimer driver PWM parameter + * @internal gui name="PWM configuration" id="ftmPwmCfg" + */ +typedef struct FtmPwmParam +{ + ftm_config_mode_t mode; /*!< FlexTimer PWM operation mode @internal gui name="Mode" id="ChannelMode" */ + ftm_pwm_edge_mode_t edgeMode; /*!< PWM output mode @internal gui name="Edge mode" id="ChannelEdgeMode" */ + uint32_t uFrequencyHZ; /*!< PWM period in Hz @internal gui name="Frequency" id="Frequency" */ + uint32_t uDutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 + 0=inactive signal(0% duty cycle)... + 100=active signal (100% duty cycle). @internal gui name="Duty cycle" id="ChannelDuty" */ + uint16_t uFirstEdgeDelayPercent; /*!< Used only in combined PWM mode to generate asymmetrical PWM. + Specifies the delay to the first edge in a PWM period. + If unsure please leave as 0, should be specified as + percentage of the PWM period @internal gui name="First edge delay" id="ChannelFirstEdge" */ +}ftm_pwm_param_t; + +/*! @brief FlexTimer Dual Edge Capture parameters */ +typedef struct FtmDualEdgeCaptureParam +{ + ftm_dual_capture_edge_mode_t mode; /*!< Dual Edge Capture mode: one-shot or continuous */ + ftm_input_capture_edge_mode_t currChanEdgeMode; /*!< Input Edge select for Channel n */ + ftm_input_capture_edge_mode_t nextChanEdgeMode; /*!< Input Edge select for Channel n + 1 */ +}ftm_dual_edge_capture_param_t; + +/*! @brief FlexTimer quadrature decode phase parameters + * @internal gui name="Quadrature decode configuration" id="ftmQuadCfg" + */ +typedef struct FtmPhaseParam +{ + bool kFtmPhaseInputFilter; /*!< false: disable phase filter, true: enable phase filter @internal gui name="Phase input filter" id="QuadPhaseFilter" */ + uint32_t kFtmPhaseFilterVal; /*!< Filter value, used only if phase input filter is enabled @internal gui name="Phase filter value" id="QuadPhaseValue" */ + ftm_quad_phase_polarity_t kFtmPhasePolarity; /*!< kFtmQuadPhaseNormal or kFtmQuadPhaseInvert @internal gui name="Phase polarity" id="QuadPhasePol" */ +}ftm_phase_params_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*FTM timer control*/ +/*! + * @brief Sets the FTM clock source. + * + * @param ftmBase The FTM base address pointer + * @param clock The FTM peripheral clock selection\n + * bits - 00: No clock 01: system clock 10: fixed clock 11: External clock + */ +static inline void FTM_HAL_SetClockSource(FTM_Type *ftmBase, ftm_clock_source_t clock) +{ + FTM_BWR_SC_CLKS(ftmBase, clock); +} + +/*! + * @brief Reads the FTM clock source. + * + * @param ftmBase The FTM base address pointer + * + * @return The FTM clock source selection\n + * bits - 00: No clock 01: system clock 10: fixed clock 11:External clock + */ +static inline uint8_t FTM_HAL_GetClockSource(FTM_Type *ftmBase) +{ + return FTM_BRD_SC_CLKS(ftmBase); +} + +/*! + * @brief Sets the FTM clock divider. + * + * @param ftmBase The FTM base address pointer + * @param ps The FTM peripheral clock pre-scale divider + */ +static inline void FTM_HAL_SetClockPs(FTM_Type *ftmBase, ftm_clock_ps_t ps) +{ + FTM_BWR_SC_PS(ftmBase, ps); +} + +/*! + * @brief Reads the FTM clock divider. + * + * @param ftmBase The FTM base address pointer + * + * @return The FTM clock pre-scale divider + */ +static inline uint8_t FTM_HAL_GetClockPs(FTM_Type *ftmBase) +{ + return FTM_BRD_SC_PS(ftmBase); +} + +/*! + * @brief Enables the FTM peripheral timer overflow interrupt. + * + * @param ftmBase The FTM base address pointer + */ +static inline void FTM_HAL_EnableTimerOverflowInt(FTM_Type *ftmBase) +{ + FTM_BWR_SC_TOIE(ftmBase, 1); +} + +/*! + * @brief Disables the FTM peripheral timer overflow interrupt. + * + * @param ftmBase The FTM base address pointer + */ +static inline void FTM_HAL_DisableTimerOverflowInt(FTM_Type *ftmBase) +{ + FTM_BWR_SC_TOIE(ftmBase, 0); +} + +/*! + * @brief Reads the bit that controls enabling the FTM timer overflow interrupt. + * + * @param ftmBase The FTM base address pointer + * @return true if overflow interrupt is enabled, false if not + */ +static inline bool FTM_HAL_IsOverflowIntEnabled(FTM_Type *ftmBase) +{ + return (bool)(FTM_BRD_SC_TOIE(ftmBase)); +} + +/*! + * @brief Clears the timer overflow interrupt flag. + * + * @param ftmBase The FTM base address pointer + */ +static inline void FTM_HAL_ClearTimerOverflow(FTM_Type *ftmBase) +{ + FTM_BWR_SC_TOF(ftmBase, 0); +} + +/*! + * @brief Returns the FTM peripheral timer overflow interrupt flag. + * + * @param ftmBase The FTM base address pointer + * @return true if overflow, false if not + */ +static inline bool FTM_HAL_HasTimerOverflowed(FTM_Type *ftmBase) +{ + return FTM_BRD_SC_TOF(ftmBase); +} + +/*! + * @brief Sets the FTM center-aligned PWM select. + * + * @param ftmBase The FTM base address pointer + * @param mode 1:upcounting mode 0:up_down counting mode + */ +static inline void FTM_HAL_SetCpwms(FTM_Type *ftmBase, uint8_t mode) +{ + assert(mode < 2); + FTM_BWR_SC_CPWMS(ftmBase, mode); +} + +/*! + * @brief Sets the FTM peripheral current counter value. + * + * @param ftmBase The FTM base address pointer + * @param val FTM timer counter value to be set + */ +static inline void FTM_HAL_SetCounter(FTM_Type *ftmBase, uint16_t val) +{ + FTM_WR_CNT_COUNT(ftmBase, val); +} + +/*! + * @brief Returns the FTM peripheral current counter value. + * + * @param ftmBase The FTM base address pointer + * @return current FTM timer counter value + */ +static inline uint16_t FTM_HAL_GetCounter(FTM_Type *ftmBase) +{ + return FTM_RD_CNT_COUNT(ftmBase); +} + +/*! + * @brief Sets the FTM peripheral timer modulo value. + * + * @param ftmBase The FTM base address pointer + * @param val The value to be set to the timer modulo + */ +static inline void FTM_HAL_SetMod(FTM_Type *ftmBase, uint16_t val) +{ + FTM_WR_MOD_MOD(ftmBase, val); +} + +/*! + * @brief Returns the FTM peripheral counter modulo value. + * + * @param ftmBase The FTM base address pointer + * @return FTM timer modulo value + */ +static inline uint16_t FTM_HAL_GetMod(FTM_Type *ftmBase) +{ + return FTM_RD_MOD_MOD(ftmBase); +} + +/*! + * @brief Sets the FTM peripheral timer counter initial value. + * + * @param ftmBase The FTM base address pointer + * @param val initial value to be set + */ +static inline void FTM_HAL_SetCounterInitVal(FTM_Type *ftmBase, uint16_t val) +{ + FTM_WR_CNTIN_INIT(ftmBase, val & FTM_CNTIN_INIT_MASK); +} + +/*! + * @brief Returns the FTM peripheral counter initial value. + * + * @param ftmBase The FTM base address pointer + * @return FTM timer counter initial value + */ +static inline uint16_t FTM_HAL_GetCounterInitVal(FTM_Type *ftmBase) +{ + return FTM_RD_CNTIN_INIT(ftmBase); +} + +/*FTM channel operating mode (Mode, edge and level selection) for capture, output, PWM, combine, dual */ +/*! + * @brief Sets the FTM peripheral timer channel mode. + * + * @param ftmBase The FTM base address pointer + * @param channel The FTM peripheral channel number + * @param selection The mode to be set valid value MSnB:MSnA :00,01, 10, 11 + */ +static inline void FTM_HAL_SetChnMSnBAMode(FTM_Type *ftmBase, uint8_t channel, uint8_t selection) +{ + assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); + FTM_BWR_CnSC_MSA(ftmBase, channel, selection & 1); + FTM_BWR_CnSC_MSB(ftmBase, channel, selection & 2 ? 1 : 0); +} + +/*! + * @brief Sets the FTM peripheral timer channel edge level. + * + * @param ftmBase The FTM base address pointer + * @param channel The FTM peripheral channel number + * @param level The rising or falling edge to be set, valid value ELSnB:ELSnA :00,01, 10, 11 + */ +static inline void FTM_HAL_SetChnEdgeLevel(FTM_Type *ftmBase, uint8_t channel, uint8_t level) +{ + assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); + FTM_BWR_CnSC_ELSA(ftmBase, channel, level & 1 ? 1 : 0); + FTM_BWR_CnSC_ELSB(ftmBase, channel, level & 2 ? 1 : 0); +} + +/*! + * @brief Gets the FTM peripheral timer channel mode. + * + * @param ftmBase The FTM base address pointer + * @param channel The FTM peripheral channel number + * @return The MSnB:MSnA mode value, will be 00,01, 10, 11 + */ +static inline uint8_t FTM_HAL_GetChnMode(FTM_Type *ftmBase, uint8_t channel) +{ + assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); + return (FTM_BRD_CnSC_MSA(ftmBase, channel)|| (FTM_BRD_CnSC_MSB(ftmBase, channel) << 1)); +} + +/*! + * @brief Gets the FTM peripheral timer channel edge level. + * + * @param ftmBase The FTM base address pointer + * @param channel The FTM peripheral channel number + * @return The ELSnB:ELSnA mode value, will be 00,01, 10, 11 + */ +static inline uint8_t FTM_HAL_GetChnEdgeLevel(FTM_Type *ftmBase, uint8_t channel) +{ + assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); + return (FTM_BRD_CnSC_ELSA(ftmBase, channel)|| (FTM_BRD_CnSC_ELSB(ftmBase, channel) << 1)); +} + +/*! + * @brief Enables or disables the FTM peripheral timer channel DMA. + * + * @param ftmBase The FTM base address pointer + * @param channel The FTM peripheral channel number + * @param val enable or disable + */ +static inline void FTM_HAL_SetChnDmaCmd(FTM_Type *ftmBase, uint8_t channel, bool val) +{ + assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); + FTM_BWR_CnSC_DMA(ftmBase, channel,(val? 1 : 0)); +} + +/*! + * @brief Returns whether the FTM peripheral timer channel DMA is enabled. + * + * @param ftmBase The FTM base address pointer + * @param channel The FTM peripheral channel number + * @return true if enabled, false if disabled + */ +static inline bool FTM_HAL_IsChnDma(FTM_Type *ftmBase, uint8_t channel) +{ + assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); + return (FTM_BRD_CnSC_DMA(ftmBase, channel) ? true : false); +} + +/*! + * @brief Get FTM channel(n) interrupt enabled or not. + * @param ftmBase FTM module base address. + * @param channel The FTM peripheral channel number + */ +static inline bool FTM_HAL_IsChnIntEnabled(FTM_Type *ftmBase, uint8_t channel) +{ + assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); + return (bool)(FTM_BRD_CnSC_CHIE(ftmBase, channel)); +} + +/*! + * @brief Enables the FTM peripheral timer channel(n) interrupt. + * + * @param ftmBase The FTM base address pointer + * @param channel The FTM peripheral channel number + */ +static inline void FTM_HAL_EnableChnInt(FTM_Type *ftmBase, uint8_t channel) +{ + assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); + FTM_BWR_CnSC_CHIE(ftmBase, channel, 1); +} +/*! + * @brief Disables the FTM peripheral timer channel(n) interrupt. + * + * @param ftmBase The FTM base address pointer + * @param channel The FTM peripheral channel number + */ +static inline void FTM_HAL_DisableChnInt(FTM_Type *ftmBase, uint8_t channel) +{ + assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); + FTM_BWR_CnSC_CHIE(ftmBase, channel, 0); +} + +/*! + * @brief Returns whether any event for the FTM peripheral timer channel has occurred. + * + * @param ftmBase The FTM base address pointer + * @param channel The FTM peripheral channel number + * @return true if event occurred, false otherwise. + */ +static inline bool FTM_HAL_HasChnEventOccurred(FTM_Type *ftmBase, uint8_t channel) +{ + assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); + return (FTM_BRD_CnSC_CHF(ftmBase, channel)) ? true : false; +} + +/*! + * @brief Clear the channel flag by writing a 0 to the CHF bit. + * + * @param ftmBase The FTM base address pointer + * @param channel The FTM peripheral channel number + */ +static inline void FTM_HAL_ClearChnEventFlag(FTM_Type *ftmBase, uint8_t channel) +{ + assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); + FTM_BWR_CnSC_CHF(ftmBase, channel, 0); +} + +/*FTM channel control*/ +/*! + * @brief Sets the FTM peripheral timer channel counter value. + * + * @param ftmBase The FTM base address pointer + * @param channel The FTM peripheral channel number + * @param val counter value to be set + */ +static inline void FTM_HAL_SetChnCountVal(FTM_Type *ftmBase, uint8_t channel, uint16_t val) +{ + assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); + FTM_WR_CnV_VAL(ftmBase, channel, val); +} + +/*! + * @brief Gets the FTM peripheral timer channel counter value. + * + * @param ftmBase The FTM base address pointer + * @param channel The FTM peripheral channel number + * @return return channel counter value + */ +static inline uint16_t FTM_HAL_GetChnCountVal(FTM_Type *ftmBase, uint8_t channel) +{ + assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); + return FTM_RD_CnV_VAL(ftmBase, channel); +} + +/*! + * @brief Gets the FTM peripheral timer channel event status. + * + * @param ftmBase The FTM base address pointer + * @param channel The FTM peripheral channel number + * @return return channel event status value + */ +static inline uint32_t FTM_HAL_GetChnEventStatus(FTM_Type *ftmBase, uint8_t channel) +{ + assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); + return (FTM_RD_STATUS(ftmBase) & (1U << channel)) ? true : false; + /*return BR_FTM_STATUS(ftmBase, channel);*/ +} + +/*! + * @brief Clears the FTM peripheral timer all channel event status. + * + * @param ftmBase The FTM base address pointer + * @param channel The FTM peripheral channel number + */ +static inline void FTM_HAL_ClearChnEventStatus(FTM_Type *ftmBase, uint8_t channel) +{ + assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); + FTM_CLR_STATUS(ftmBase, 1U << channel); +} + +/*! + * @brief Writes the provided value to the OUTMASK register. + * + * This function will mask/uumask multiple channels. + * + * @param ftmBase The FTM base address pointer + * @param regVal value to be written to the register + */ +static inline void FTM_HAL_SetOutmaskReg(FTM_Type *ftmBase, uint32_t regVal) +{ + FTM_WR_OUTMASK(ftmBase, regVal); +} + +/*! + * @brief Sets the FTM peripheral timer channel output mask. + * + * @param ftmBase The FTM base address pointer + * @param channel The FTM peripheral channel number + * @param mask mask to be set 0 or 1, unmasked or masked + */ +static inline void FTM_HAL_SetChnOutputMask(FTM_Type *ftmBase, uint8_t channel, bool mask) +{ + assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); + mask ? FTM_SET_OUTMASK(ftmBase, 1U << channel) : FTM_CLR_OUTMASK(ftmBase, 1U << channel); + /* BW_FTM_OUTMASK_CHnOM(ftmBase, channel,mask); */ +} + +/*! + * @brief Sets the FTM peripheral timer channel output initial state 0 or 1. + * + * @param ftmBase The FTM base address pointer + * @param channel The FTM peripheral channel number + * @param state counter value to be set 0 or 1 + */ +static inline void FTM_HAL_SetChnOutputInitStateCmd(FTM_Type *ftmBase, uint8_t channel, uint8_t state) +{ + assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); + FTM_CLR_OUTINIT(ftmBase, 1U << channel); + FTM_SET_OUTINIT(ftmBase, (uint8_t)(state << channel)); +} + +/*! + * @brief Sets the FTM peripheral timer channel output polarity. + * + * @param ftmBase The FTM base address pointer + * @param channel The FTM peripheral channel number + * @param pol polarity to be set 0 or 1 + */ +static inline void FTM_HAL_SetChnOutputPolarityCmd(FTM_Type *ftmBase, uint8_t channel, uint8_t pol) +{ + assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); + FTM_CLR_POL(ftmBase, 1U << channel); + FTM_SET_POL(ftmBase, (uint8_t)(pol << channel)); +} +/*! + * @brief Sets the FTM peripheral timer channel input polarity. + * + * @param ftmBase The FTM base address pointer + * @param channel The FTM peripheral channel number + * @param pol polarity to be set, 0: active high, 1:active low + */ +static inline void FTM_HAL_SetChnFaultInputPolarityCmd(FTM_Type *ftmBase, uint8_t channel, uint8_t pol) +{ + assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); + FTM_CLR_FLTPOL(ftmBase, 1U << channel); + FTM_SET_FLTPOL(ftmBase, (uint8_t)(pol << channel)); +} + + +/*Feature mode selection HAL*/ + /*FTM fault control*/ +/*! + * @brief Enables the FTM peripheral timer fault interrupt. + * + * @param ftmBase The FTM base address pointer + */ +static inline void FTM_HAL_EnableFaultInt(FTM_Type *ftmBase) +{ + FTM_BWR_MODE_FAULTIE(ftmBase, 1); +} + +/*! + * @brief Disables the FTM peripheral timer fault interrupt. + * + * @param ftmBase The FTM base address pointer + */ +static inline void FTM_HAL_DisableFaultInt(FTM_Type *ftmBase) +{ + FTM_BWR_MODE_FAULTIE(ftmBase, 0); +} + +/*! + * @brief Defines the FTM fault control mode. + * + * @param ftmBase The FTM base address pointer + * @param mode, valid options are 1, 2, 3, 4 + */ +static inline void FTM_HAL_SetFaultControlMode(FTM_Type *ftmBase, uint8_t mode) +{ + FTM_BWR_MODE_FAULTM(ftmBase, mode); +} + +/*! + * @brief Enables or disables the FTM peripheral timer capture test mode. + * + * @param ftmBase The FTM base address pointer + * @param enable true to enable capture test mode, false to disable + */ +static inline void FTM_HAL_SetCaptureTestCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_MODE_CAPTEST(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Enables or disables the FTM write protection. + * + * @param ftmBase The FTM base address pointer + * @param enable true: Write-protection is enabled, false: Write-protection is disabled + */ +static inline void FTM_HAL_SetWriteProtectionCmd(FTM_Type *ftmBase, bool enable) +{ + enable ? FTM_BWR_FMS_WPEN(ftmBase, 1) : FTM_BWR_MODE_WPDIS(ftmBase, 1); +} + +/*! + * @brief Enables the FTM peripheral timer group. + * + * @param ftmBase The FTM base address pointer + * @param enable true: all registers including FTM-specific registers are available + * false: only the TPM-compatible registers are available + */ +static inline void FTM_HAL_Enable(FTM_Type *ftmBase, bool enable) +{ + assert(FTM_BRD_MODE_WPDIS(ftmBase)); + FTM_BWR_MODE_FTMEN(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Initializes the channels output. + * + * @param ftmBase The FTM base address pointer + * @param enable true: the channels output is initialized according to the state of OUTINIT reg + * false: has no effect + */ +static inline void FTM_HAL_SetInitChnOutputCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_MODE_INIT(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Sets the FTM peripheral timer sync mode. + * + * @param ftmBase The FTM base address pointer + * @param enable true: no restriction both software and hardware triggers can be used\n + * false: software trigger can only be used for MOD and CnV synch, hardware trigger + * only for OUTMASK and FTM counter synch. + */ +static inline void FTM_HAL_SetPwmSyncMode(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_MODE_PWMSYNC(ftmBase, enable ? 1 : 0); +} + +/*FTM synchronization control*/ +/*! + * @brief Enables or disables the FTM peripheral timer software trigger. + * + * @param ftmBase The FTM base address pointer. + * @param enable true: software trigger is selected, false: software trigger is not selected + */ +static inline void FTM_HAL_SetSoftwareTriggerCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_SYNC_SWSYNC(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Sets the FTM peripheral timer hardware trigger. + * + * @param ftmBase The FTM base address pointer + * @param trigger_num 0, 1, 2 for trigger0, trigger1 and trigger3 + * @param enable true: enable hardware trigger from field trigger_num for PWM synch + * false: disable hardware trigger from field trigger_num for PWM synch + */ +void FTM_HAL_SetHardwareSyncTriggerSrc(FTM_Type *ftmBase, uint32_t trigger_num, bool enable); + +/*! + * @brief Determines when the OUTMASK register is updated with the value of its buffer. + * + * @param ftmBase The FTM base address pointer + * @param enable true if OUTMASK register is updated only by PWM sync\n + * false if OUTMASK register is updated in all rising edges of the system clock + */ +static inline void FTM_HAL_SetOutmaskPwmSyncModeCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_SYNC_SYNCHOM(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Determines if the FTM counter is re-initialized when the selected trigger for + * synchronization is detected. + * + * @param ftmBase The FTM base address pointer + * @param enable True to update FTM counter when triggered , false to count normally + */ +static inline void FTM_HAL_SetCountReinitSyncCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_SYNC_REINIT(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Enables or disables the FTM peripheral timer maximum loading points. + * + * @param ftmBase The FTM base address pointer + * @param enable True to enable maximum loading point, false to disable + */ +static inline void FTM_HAL_SetMaxLoadingCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_SYNC_CNTMAX(ftmBase, enable ? 1 : 0); +} +/*! + * @brief Enables or disables the FTM peripheral timer minimum loading points. + * + * @param ftmBase The FTM base address pointer + * @param enable True to enable minimum loading point, false to disable + */ +static inline void FTM_HAL_SetMinLoadingCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_SYNC_CNTMIN(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Combines the channel control. + * + * Returns an index for each channel pair. + * + * @param channel The FTM peripheral channel number. + * @return 0 for channel pair 0 & 1\n + * 1 for channel pair 2 & 3\n + * 2 for channel pair 4 & 5\n + * 3 for channel pair 6 & 7 + */ +uint32_t FTM_HAL_GetChnPairIndex(uint8_t channel); + +/*! + * @brief Enables the FTM peripheral timer channel pair fault control. + * + * @param ftmBase The FTM base address pointer + * @param chnlPairNum The FTM peripheral channel pair number + * @param enable True to enable fault control, false to disable + */ +static inline void FTM_HAL_SetDualChnFaultCmd(FTM_Type *ftmBase, uint8_t chnlPairNum, bool enable) +{ + assert(chnlPairNum < (FSL_FEATURE_FTM_CHANNEL_COUNT / 2)); + + enable ? FTM_SET_COMBINE(ftmBase, FTM_COMBINE_FAULTEN0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH)): + FTM_CLR_COMBINE(ftmBase, FTM_COMBINE_FAULTEN0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH)); +} + +/*! + * @brief Enables or disables the FTM peripheral timer channel pair counter PWM sync. + * + * @param ftmBase The FTM base address pointer + * @param chnlPairNum The FTM peripheral channel pair number + * @param enable True to enable PWM synchronization, false to disable + */ +static inline void FTM_HAL_SetDualChnPwmSyncCmd(FTM_Type *ftmBase, uint8_t chnlPairNum, bool enable) +{ + assert(chnlPairNum < (FSL_FEATURE_FTM_CHANNEL_COUNT / 2)); + + enable ? FTM_SET_COMBINE(ftmBase, FTM_COMBINE_SYNCEN0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH)): + FTM_CLR_COMBINE(ftmBase, FTM_COMBINE_SYNCEN0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH)); +} + +/*! + * @brief Enables or disabled the FTM peripheral timer channel pair deadtime insertion. + * + * @param ftmBase The FTM base address pointer + * @param chnlPairNum The FTM peripheral channel pair number + * @param enable True to enable deadtime insertion, false to disable + */ +static inline void FTM_HAL_SetDualChnDeadtimeCmd(FTM_Type *ftmBase, uint8_t chnlPairNum, bool enable) +{ + assert(chnlPairNum < FSL_FEATURE_FTM_CHANNEL_COUNT); + + enable ? FTM_SET_COMBINE(ftmBase, FTM_COMBINE_DTEN0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH)): + FTM_CLR_COMBINE(ftmBase, FTM_COMBINE_DTEN0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH)); +} + +/*! + * @brief Enables or disables the FTM peripheral timer channel dual edge capture decap. + * + * @param ftmBase The FTM base address pointer + * @param chnlPairNum The FTM peripheral channel pair number + * @param enable True to enable dual edge capture mode, false to disable + */ +static inline void FTM_HAL_SetDualChnDecapCmd(FTM_Type *ftmBase, uint8_t chnlPairNum, bool enable) +{ + assert(chnlPairNum < (FSL_FEATURE_FTM_CHANNEL_COUNT / 2)); + + enable ? FTM_SET_COMBINE(ftmBase, FTM_COMBINE_DECAP0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH)): + FTM_CLR_COMBINE(ftmBase, FTM_COMBINE_DECAP0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH)); +} + +/*! + * @brief Enables the FTM peripheral timer dual edge capture mode. + * + * @param ftmBase The FTM base address pointer + * @param chnlPairNum The FTM peripheral channel pair number + * @param enable True to enable dual edge capture, false to disable + */ +static inline void FTM_HAL_SetDualEdgeCaptureCmd(FTM_Type *ftmBase, uint8_t chnlPairNum, bool enable) +{ + assert(chnlPairNum < (FSL_FEATURE_FTM_CHANNEL_COUNT / 2)); + + enable ? FTM_SET_COMBINE(ftmBase, FTM_COMBINE_DECAPEN0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH)): + FTM_CLR_COMBINE(ftmBase, FTM_COMBINE_DECAPEN0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH)); +} + +/*! + * @brief Enables or disables the FTM peripheral timer channel pair output complement mode. + * + * @param ftmBase The FTM base address pointer + * @param chnlPairNum The FTM peripheral channel pair number + * @param enable True to enable complementary mode, false to disable + */ +static inline void FTM_HAL_SetDualChnCompCmd(FTM_Type *ftmBase, uint8_t chnlPairNum, bool enable) +{ + assert(chnlPairNum < (FSL_FEATURE_FTM_CHANNEL_COUNT / 2)); + + enable ? FTM_SET_COMBINE(ftmBase, FTM_COMBINE_COMP0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH)): + FTM_CLR_COMBINE(ftmBase, FTM_COMBINE_COMP0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH)); + +} + +/*! + * @brief Enables or disables the FTM peripheral timer channel pair output combine mode. + * + * @param ftmBase The FTM base address pointer + * @param chnlPairNum The FTM peripheral channel pair number + * @param enable True to enable channel pair to combine, false to disable + */ +static inline void FTM_HAL_SetDualChnCombineCmd(FTM_Type *ftmBase, uint8_t chnlPairNum, bool enable) +{ + assert(chnlPairNum < (FSL_FEATURE_FTM_CHANNEL_COUNT / 2)); + + enable ? FTM_SET_COMBINE(ftmBase, FTM_COMBINE_COMBINE0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH)): + FTM_CLR_COMBINE(ftmBase, FTM_COMBINE_COMBINE0_MASK << (chnlPairNum * FTM_COMBINE_CHAN_CTRL_WIDTH)); +} + +/*FTM dead time insertion control*/ +/*! + * @brief Sets the FTM deadtime divider. + * + * @param ftmBase The FTM base address pointer + * @param divider The FTM peripheral prescale divider\n + * 0x :divided by 1, 10: divided by 4, 11:divided by 16 + */ +static inline void FTM_HAL_SetDeadtimePrescale(FTM_Type *ftmBase, ftm_deadtime_ps_t divider) +{ + FTM_WR_DEADTIME_DTPS(ftmBase, divider); +} + +/*! + * @brief Sets the FTM deadtime value. + * + * @param ftmBase The FTM base address pointer + * @param count The FTM peripheral prescale divider\n + * 0: no counts inserted, 1: 1 count is inserted, 2: 2 count is inserted.... + */ +static inline void FTM_HAL_SetDeadtimeCount(FTM_Type *ftmBase, uint8_t count) +{ + FTM_WR_DEADTIME_DTVAL(ftmBase, count); +} + +/*! +* @brief Enables or disables the generation of the trigger when the FTM counter is equal to the CNTIN register. +* +* @param ftmBase The FTM base address pointer +* @param enable True to enable, false to disable +*/ +static inline void FTM_HAL_SetInitTriggerCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_EXTTRIG_INITTRIGEN(ftmBase, enable ? 1 : 0); +} + +/*FTM external trigger */ +/*! + * @brief Enables or disables the generation of the FTM peripheral timer channel trigger. + * + * Enables or disables the generation of the FTM peripheral timer channel trigger when the + * FTM counter is equal to its initial value. Channels 6 and 7 cannot be used as triggers. + * + * @param ftmBase The FTM base address pointer + * @param channel Channel to be enabled, valid value 0, 1, 2, 3, 4, 5 + * @param val True to enable, false to disable + */ +void FTM_HAL_SetChnTriggerCmd(FTM_Type *ftmBase, uint8_t channel, bool val); + +/*! + * @brief Checks whether any channel trigger event has occurred. + * + * @param ftmBase The FTM base address pointer + * @return true if there is a channel trigger event, false if not. + */ +static inline bool FTM_HAL_IsChnTriggerGenerated(FTM_Type *ftmBase) +{ + return FTM_BRD_EXTTRIG_TRIGF(ftmBase); +} + +/*Fault mode status*/ +/*! + * @brief Gets the FTM detected fault input. + * + * This function reads the status for all fault inputs + * + * @param ftmBase The FTM base address pointer + * @return Return fault byte + */ +static inline uint8_t FTM_HAL_GetDetectedFaultInput(FTM_Type *ftmBase) +{ + return (FTM_RD_FMS(ftmBase) & 0x0f); +} + +/*! + * @brief Checks whether the write protection is enabled. + * + * @param ftmBase The FTM base address pointer + * @return True if enabled, false if not + */ +static inline bool FTM_HAL_IsWriteProtectionEnabled(FTM_Type *ftmBase) +{ + return FTM_BRD_FMS_WPEN(ftmBase) ? true : false; +} + +/*Quadrature decoder control*/ + +/*! + * @brief Enables the channel quadrature decoder. + * + * @param ftmBase The FTM base address pointer + * @param enable True to enable, false to disable + */ +static inline void FTM_HAL_SetQuadDecoderCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_QDCTRL_QUADEN(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Enables or disables the phase A input filter. + * + * @param ftmBase The FTM base address pointer + * @param enable true enables the phase input filter, false disables the filter + */ +static inline void FTM_HAL_SetQuadPhaseAFilterCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_QDCTRL_PHAFLTREN(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Enables or disables the phase B input filter. + * + * @param ftmBase The FTM base address pointer + * @param enable true enables the phase input filter, false disables the filter + */ +static inline void FTM_HAL_SetQuadPhaseBFilterCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_QDCTRL_PHBFLTREN(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Selects polarity for the quadrature decode phase A input. + * + * @param ftmBase The FTM base address pointer + * @param mode 0: Normal polarity, 1: Inverted polarity + */ +static inline void FTM_HAL_SetQuadPhaseAPolarity(FTM_Type *ftmBase, + ftm_quad_phase_polarity_t mode) +{ + FTM_BWR_QDCTRL_PHAPOL(ftmBase, mode); +} + +/*! + * @brief Selects polarity for the quadrature decode phase B input. + * + * @param ftmBase The FTM base address pointer + * @param mode 0: Normal polarity, 1: Inverted polarity + */ +static inline void FTM_HAL_SetQuadPhaseBPolarity(FTM_Type *ftmBase, + ftm_quad_phase_polarity_t mode) +{ + FTM_BWR_QDCTRL_PHBPOL(ftmBase, mode); +} + +/*! + * @brief Sets the encoding mode used in quadrature decoding mode. + * + * @param ftmBase The FTM base address pointer + * @param quadMode 0: Phase A and Phase B encoding mode\n + * 1: Count and direction encoding mode + */ +static inline void FTM_HAL_SetQuadMode(FTM_Type *ftmBase, ftm_quad_decode_mode_t quadMode) +{ + FTM_BWR_QDCTRL_QUADMODE(ftmBase, quadMode); +} + +/*! + * @brief Gets the FTM counter direction in quadrature mode. + * + * @param ftmBase The FTM base address pointer + * + * @return 1 if counting direction is increasing, 0 if counting direction is decreasing + */ +static inline uint8_t FTM_HAL_GetQuadDir(FTM_Type *ftmBase) +{ + return FTM_BRD_QDCTRL_QUADMODE(ftmBase); +} + +/*! + * @brief Gets the Timer overflow direction in quadrature mode. + * + * @param ftmBase The FTM base address pointer + * + * @return 1 if TOF bit was set on the top of counting, o if TOF bit was set on the bottom of counting + */ +static inline uint8_t FTM_HAL_GetQuadTimerOverflowDir(FTM_Type *ftmBase) +{ + return FTM_BRD_QDCTRL_TOFDIR(ftmBase); +} + +/*! + * @brief Sets the FTM peripheral timer channel input capture filter value. + * @param ftmBase The FTM base address pointer + * @param channel The FTM peripheral channel number, only 0,1,2,3, channel 4, 5,6, 7 don't have. + * @param val Filter value to be set + */ +void FTM_HAL_SetChnInputCaptureFilter(FTM_Type *ftmBase, uint8_t channel, uint8_t val); + +/*! + * @brief Sets the fault input filter value. + * + * @param ftmBase The FTM base address pointer + * @param val fault input filter value + */ +static inline void FTM_HAL_SetFaultInputFilterVal(FTM_Type *ftmBase, uint32_t val) +{ + FTM_BWR_FLTCTRL_FFVAL(ftmBase, val); +} + +/*! + * @brief Enables or disables the fault input filter. + * + * @param ftmBase The FTM base address pointer + * @param inputNum fault input to be configured, valid value 0, 1, 2, 3 + * @param val true to enable fault input filter, false to disable fault input filter + */ +static inline void FTM_HAL_SetFaultInputFilterCmd(FTM_Type *ftmBase, uint8_t inputNum, bool val) +{ + assert(inputNum < CHAN4_IDX); + val ? FTM_SET_FLTCTRL(ftmBase, (1U << (inputNum + 4))) : + FTM_CLR_FLTCTRL(ftmBase, (1U << (inputNum + 4))); +} + +/*! + * @brief Enables or disables the fault input. + * + * @param ftmBase The FTM base address pointer + * @param inputNum fault input to be configured, valid value 0, 1, 2, 3 + * @param val true to enable fault input, false to disable fault input + */ +static inline void FTM_HAL_SetFaultInputCmd(FTM_Type *ftmBase, uint8_t inputNum, bool val) +{ + assert(inputNum < CHAN4_IDX); + val ? FTM_SET_FLTCTRL(ftmBase, (1U << inputNum)) : + FTM_CLR_FLTCTRL(ftmBase, (1U << inputNum)); +} + +/*! + * @brief Enables or disables the channel invert for a channel pair. + * + * @param ftmBase The FTM base address pointer + * @param chnlPairNum The FTM peripheral channel pair number + * @param val true to enable channel inverting, false to disable channel inver + */ +static inline void FTM_HAL_SetDualChnInvertCmd(FTM_Type *ftmBase, uint8_t chnlPairNum, bool val) +{ + assert(chnlPairNum < (FSL_FEATURE_FTM_CHANNEL_COUNT / 2)); + + val ? FTM_SET_INVCTRL(ftmBase, (1U << chnlPairNum)) : + FTM_CLR_INVCTRL(ftmBase, (1U << chnlPairNum)); +} + +/*! + * @brief Writes the provided value to the Inverting control register. + * + * This function is enable/disable inverting control on multiple channel pairs. + * + * @param ftmBase The FTM base address pointer + * @param regVal value to be written to the register + */ +static inline void FTM_HAL_SetInvctrlReg(FTM_Type *ftmBase, uint32_t regVal) +{ + FTM_WR_INVCTRL(ftmBase, regVal); +} + +/*FTM software output control*/ +/*! + * @brief Enables or disables the channel software output control. + * @param ftmBase The FTM base address pointer + * @param channel Channel to be enabled or disabled + * @param val true to enable, channel output will be affected by software output control\n + false to disable, channel output is unaffected + */ +static inline void FTM_HAL_SetChnSoftwareCtrlCmd(FTM_Type *ftmBase, uint8_t channel, bool val) +{ + assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); + val ? FTM_SET_SWOCTRL(ftmBase, (1U << channel)) : + FTM_CLR_SWOCTRL(ftmBase, (1U << channel)); +} +/*! + * @brief Sets the channel software output control value. + * + * @param ftmBase The FTM base address pointer. + * @param channel Channel to be configured + * @param val True to set 1, false to set 0 + */ +static inline void FTM_HAL_SetChnSoftwareCtrlVal(FTM_Type *ftmBase, uint8_t channel, bool val) +{ + assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); + val ? FTM_SET_SWOCTRL(ftmBase, (1U << (channel + 8))) : + FTM_CLR_SWOCTRL(ftmBase, (1U << (channel + 8))); +} + +/*FTM PWM load control*/ +/*! + * @brief Enables or disables the loading of MOD, CNTIN and CV with values of their write buffer. + * + * @param ftmBase The FTM base address pointer + * @param enable true to enable, false to disable + */ +static inline void FTM_HAL_SetPwmLoadCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_PWMLOAD_LDOK(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Includes or excludes the channel in the matching process. + * + * @param ftmBase The FTM base address pointer + * @param channel Channel to be configured + * @param val true means include the channel in the matching process\n + * false means do not include channel in the matching process + */ +static inline void FTM_HAL_SetPwmLoadChnSelCmd(FTM_Type *ftmBase, uint8_t channel, bool val) +{ + assert(channel < FSL_FEATURE_FTM_CHANNEL_COUNT); + val ? FTM_SET_PWMLOAD(ftmBase, 1U << channel) : FTM_CLR_PWMLOAD(ftmBase, 1U << channel); +} + +/*FTM configuration*/ +/*! + * @brief Enables or disables the FTM global time base signal generation to other FTM's. + * + * @param ftmBase The FTM base address pointer + * @param enable True to enable, false to disable + */ +static inline void FTM_HAL_SetGlobalTimeBaseOutputCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_CONF_GTBEOUT(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Enables or disables the FTM timer global time base. + * + * @param ftmBase The FTM base address pointer + * @param enable True to enable, false to disable + */ +static inline void FTM_HAL_SetGlobalTimeBaseCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_CONF_GTBEEN(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Sets the BDM mode. + * + * @param ftmBase The FTM base address pointer + * @param val FTM behaviour in BDM mode, options are defined in the enum ftm_bdm_mode_t + */ +static inline void FTM_HAL_SetBdmMode(FTM_Type *ftmBase, ftm_bdm_mode_t val) +{ + FTM_WR_CONF_BDMMODE(ftmBase, val); +} + +/*! + * @brief Sets the FTM timer TOF Frequency + * + * @param ftmBase The FTM base address pointer + * @param val Value of the TOF bit set frequency + */ +static inline void FTM_HAL_SetTofFreq(FTM_Type *ftmBase, uint8_t val) +{ + FTM_WR_CONF_NUMTOF(ftmBase, val); +} + +/*FTM sync configuration*/ + +/*! + * @brief Sets the FTM register synchronization method. + * + * This function will set the necessary bits for the synchronization mode that user wishes to use. + * + * @param ftmBase The FTM base address pointer + * @param syncMethod Synchronization method defined by ftm_sync_method_t enum. User can choose + * multiple synch methods by OR'ing options + */ +void FTM_HAL_SetSyncMode(FTM_Type *ftmBase, uint32_t syncMethod); + +/*! + * @brief Sets the sync mode for the FTM SWOCTRL register when using a hardware trigger. + * + * @param ftmBase The FTM base address pointer + * @param enable true means the hardware trigger activates register sync\n + * false means the hardware trigger does not activate register sync. + */ +static inline void FTM_HAL_SetSwoctrlHardwareSyncModeCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_SYNCONF_HWSOC(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Sets sync mode for FTM INVCTRL register when using a hardware trigger. + * + * @param ftmBase The FTM base address pointer + * @param enable true means the hardware trigger activates register sync\n + * false means the hardware trigger does not activate register sync. + */ +static inline void FTM_HAL_SetInvctrlHardwareSyncModeCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_SYNCONF_HWINVC(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Sets sync mode for FTM OUTMASK register when using a hardware trigger. + * + * @param ftmBase The FTM base address pointer + * @param enable true means hardware trigger activates register sync\n + * false means hardware trigger does not activate register sync. + */ +static inline void FTM_HAL_SetOutmaskHardwareSyncModeCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_SYNCONF_HWOM(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Sets sync mode for FTM MOD, CNTIN and CV registers when using a hardware trigger. + * + * @param ftmBase The FTM base address pointer + * @param enable true means hardware trigger activates register sync\n + * false means hardware trigger does not activate register sync. + */ +static inline void FTM_HAL_SetModCntinCvHardwareSyncModeCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_SYNCONF_HWWRBUF(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Sets sync mode for FTM counter register when using a hardware trigger. + * + * @param ftmBase The FTM base address pointer + * @param enable true means hardware trigger activates register sync\n + * false means hardware trigger does not activate register sync. + */ +static inline void FTM_HAL_SetCounterHardwareSyncModeCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_SYNCONF_HWRSTCNT(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Sets sync mode for FTM SWOCTRL register when using a software trigger. + * + * @param ftmBase The FTM base address pointer + * @param enable true means software trigger activates register sync\n + * false means software trigger does not activate register sync. + */ +static inline void FTM_HAL_SetSwoctrlSoftwareSyncModeCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_SYNCONF_SWSOC(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Sets sync mode for FTM INVCTRL register when using a software trigger. + * + * @param ftmBase The FTM base address pointer + * @param enable true means software trigger activates register sync\n + * false means software trigger does not activate register sync. + */ +static inline void FTM_HAL_SetInvctrlSoftwareSyncModeCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_SYNCONF_SWINVC(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Sets sync mode for FTM OUTMASK register when using a software trigger. + * + * @param ftmBase The FTM base address pointer + * @param enable true means software trigger activates register sync\n + * false means software trigger does not activate register sync. + */ +static inline void FTM_HAL_SetOutmaskSoftwareSyncModeCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_SYNCONF_SWOM(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Sets synch mode for FTM MOD, CNTIN and CV registers when using a software trigger. + * + * @param ftmBase The FTM base address pointer + * @param enable true means software trigger activates register sync\n + * false means software trigger does not activate register sync. + */ +static inline void FTM_HAL_SetModCntinCvSoftwareSyncModeCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_SYNCONF_SWWRBUF(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Sets sync mode for FTM counter register when using a software trigger. + * + * @param ftmBase The FTM base address pointer + * @param enable true means software trigger activates register sync\n + * false means software trigger does not activate register sync. + */ +static inline void FTM_HAL_SetCounterSoftwareSyncModeCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_SYNCONF_SWRSTCNT(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Sets the PWM synchronization mode to enhanced or legacy. + * + * @param ftmBase The FTM base address pointer + * @param enable true means use Enhanced PWM synchronization\n + * false means to use Legacy mode + */ +static inline void FTM_HAL_SetPwmSyncModeCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_SYNCONF_SYNCMODE(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Sets the SWOCTRL register PWM synchronization mode. + * + * @param ftmBase The FTM base address pointer + * @param enable true means SWOCTRL register is updated by PWM synch\n + * false means SWOCTRL register is updated at all rising edges of system clock + */ +static inline void FTM_HAL_SetSwoctrlPwmSyncModeCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_SYNCONF_SWOC(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Sets the INVCTRL register PWM synchronization mode. + * + * @param ftmBase The FTM base address pointer + * @param enable true means INVCTRL register is updated by PWM synch\n + * false means INVCTRL register is updated at all rising edges of system clock + */ +static inline void FTM_HAL_SetInvctrlPwmSyncModeCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_SYNCONF_INVC(ftmBase, enable ? 1 : 0); +} + +/*! + * @brief Sets the CNTIN register PWM synchronization mode. + * + * @param ftmBase The FTM base address pointer + * @param enable true means CNTIN register is updated by PWM synch\n + * false means CNTIN register is updated at all rising edges of system clock + */ +static inline void FTM_HAL_SetCntinPwmSyncModeCmd(FTM_Type *ftmBase, bool enable) +{ + FTM_BWR_SYNCONF_CNTINC(ftmBase, enable ? 1 : 0); +} + + +/*HAL functionality*/ +/*! + * @brief Resets the FTM registers + * + * @param ftmBase The FTM base address pointer + */ +void FTM_HAL_Reset(FTM_Type *ftmBase); + +/*! + * @brief Initializes the FTM. + * + * @param ftmBase The FTM base address pointer. + */ +void FTM_HAL_Init(FTM_Type *ftmBase); + +/*! + * @brief Enables the FTM timer when it is PWM output mode. + * + * @param ftmBase The FTM base address pointer + * @param config PWM configuration parameter + * @param channel The channel or channel pair number(combined mode). + */ +void FTM_HAL_EnablePwmMode(FTM_Type *ftmBase, ftm_pwm_param_t *config, uint8_t channel); + +/*! + * @brief Disables the PWM output mode. + * + * @param ftmBase The FTM base address pointer + * @param config PWM configuration parameter + * @param channel The channel or channel pair number(combined mode). + */ +void FTM_HAL_DisablePwmMode(FTM_Type *ftmBase, ftm_pwm_param_t *config, uint8_t channel); + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_FEATURE_SOC_FTM_COUNT */ + +#endif /* __FSL_FTM_HAL_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_gpio_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_gpio_hal.h new file mode 100755 index 0000000..c555716 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_gpio_hal.h @@ -0,0 +1,621 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_GPIO_HAL_H__ +#define __FSL_GPIO_HAL_H__ + +#include <assert.h> +#include <stdint.h> +#include <stdbool.h> +#include "fsl_device_registers.h" + +/*! + * @addtogroup gpio_hal + * @{ + */ + +/*! + * @file fsl_gpio_hal.h + * + * @brief GPIO hardware driver configuration. Use these functions to set the GPIO input/output, + * set output logic or get input logic. Check the GPIO header file for base pointer. Each + * GPIO instance has 32 pins with numbers from 0 to 31. + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief GPIO direction definition*/ +typedef enum _gpio_pin_direction { + kGpioDigitalInput = 0U, /*!< Set current pin as digital input*/ + kGpioDigitalOutput = 1U /*!< Set current pin as digital output*/ +} gpio_pin_direction_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Configuration + * @{ + */ + +/*! + * @brief Sets the individual GPIO pin to general input or output. + * + * @param base GPIO base pointer(PTA, PTB, PTC, etc.) + * @param pin GPIO port pin number + * @param direction GPIO directions + * - kGpioDigitalInput: set to input + * - kGpioDigitalOutput: set to output + */ +void GPIO_HAL_SetPinDir(GPIO_Type * base, uint32_t pin, + gpio_pin_direction_t direction); + +/*! + * @brief Sets the GPIO port pins to general input or output. + * + * This function operates all 32 port pins. + * + * @param base GPIO base pointer (PTA, PTB, PTC, etc.) + * @param pinDirectionMap GPIO directions bit map + * - 0: set to input + * - 1: set to output + * - LSB: pin 0 + * - MSB: pin 31 + */ +static inline void GPIO_HAL_SetPortDir(GPIO_Type * base, uint32_t pinDirectionMap) +{ + GPIO_WR_PDDR(base, pinDirectionMap); +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the current direction of the individual GPIO pin. + * + * @param base GPIO base pointer(PTA, PTB, PTC, etc.) + * @param pin GPIO port pin number + * @return GPIO directions + * - kGpioDigitalInput: corresponding pin is set to input. + * - kGpioDigitalOutput: corresponding pin is set to output. + */ +static inline gpio_pin_direction_t GPIO_HAL_GetPinDir(GPIO_Type * base, uint32_t pin) +{ + assert(pin < 32); + return (gpio_pin_direction_t)((GPIO_RD_PDDR(base) >> pin) & 1U); +} + +/*! + * @brief Gets the GPIO port pins direction. + * + * This function gets all 32-pin directions as a 32-bit integer. + * + * @param base GPIO base pointer (PTA, PTB, PTC, etc.) + * @return GPIO directions. Each bit represents one pin. For each bit: + * - 0: corresponding pin is set to input + * - 1: corresponding pin is set to output + * - LSB: pin 0 + * - MSB: pin 31 + */ +static inline uint32_t GPIO_HAL_GetPortDir(GPIO_Type * base) +{ + return GPIO_RD_PDDR(base); +} + +/* @} */ + +/*! + * @name Output Operation + * @{ + */ + +/*! + * @brief Sets the output level of the individual GPIO pin to logic 1 or 0. + * + * @param base GPIO base pointer(PTA, PTB, PTC, etc.) + * @param pin GPIO port pin number + * @param output pin output logic level + */ +void GPIO_HAL_WritePinOutput(GPIO_Type * base, uint32_t pin, uint32_t output); + +/*! + * @brief Reads the current pin output. + * + * @param base GPIO base pointer (PTA, PTB, PTC, etc.) + * @param pin GPIO port pin number + * @return current pin output status. 0 - Low logic, 1 - High logic + */ +static inline uint32_t GPIO_HAL_ReadPinOutput(GPIO_Type * base, uint32_t pin) +{ + assert(pin < 32); + return ((GPIO_RD_PDOR(base) >> pin) & 0x1U); +} + +/*! + * @brief Sets the output level of the individual GPIO pin to logic 1. + * + * @param base GPIO base pointer(PTA, PTB, PTC, etc.) + * @param pin GPIO port pin number + */ +static inline void GPIO_HAL_SetPinOutput(GPIO_Type * base, uint32_t pin) +{ + assert(pin < 32); + GPIO_WR_PSOR(base, 1U << pin); +} + +/*! + * @brief Clears the output level of the individual GPIO pin to logic 0. + * + * @param base GPIO base pointer(PTA, PTB, PTC, etc.) + * @param pin GPIO port pin number + */ +static inline void GPIO_HAL_ClearPinOutput(GPIO_Type * base, uint32_t pin) +{ + assert(pin < 32); + GPIO_WR_PCOR(base, 1U << pin); +} + +/*! + * @brief Reverses the current output logic of the individual GPIO pin. + * + * @param base GPIO base pointer(PTA, PTB, PTC, etc.) + * @param pin GPIO port pin number + */ +static inline void GPIO_HAL_TogglePinOutput(GPIO_Type * base, uint32_t pin) +{ + assert(pin < 32); + GPIO_WR_PTOR(base, 1U << pin); +} + +/*! + * @brief Sets the output of the GPIO port pins to a specific logic value. + * + * This function operates all 32 port pins. + * + * @param base GPIO base pointer (PTA, PTB, PTC, etc.) + * @param portOutput data to configure the GPIO output. Each bit represents one pin. For each bit: + * - 0: set logic level 0 to pin + * - 1: set logic level 1 to pin + * - LSB: pin 0 + * - MSB: pin 31 + */ +static inline void GPIO_HAL_WritePortOutput(GPIO_Type * base, uint32_t portOutput) +{ + GPIO_WR_PDOR(base, portOutput); +} + +/*! + * @brief Reads out all pin output status of the current port. + * + * This function operates all 32 port pins. + * + * @param base GPIO base pointer (PTA, PTB, PTC, etc.) + * @return current port output status. Each bit represents one pin. For each bit: + * - 0: corresponding pin is outputting logic level 0 + * - 1: corresponding pin is outputting logic level 1 + * - LSB: pin 0 + * - MSB: pin 31 + */ +static inline uint32_t GPIO_HAL_ReadPortOutput(GPIO_Type * base) +{ + return GPIO_RD_PDOR(base); +} + +/*! + * @brief Sets the output level of the GPIO port pins to logic 1. + * + * This function operates all 32 port pins. + * + * @param base GPIO base pointer(PTA, PTB, PTC, etc.) + * @param portOutput GPIO output port pin mask. Each bit represents one pin. For each bit: + * - 0: pin output will not be changed. + * - 1: pin output will be set to logic level 1 + * - LSB: pin 0 + * - MSB: pin 31 + */ +static inline void GPIO_HAL_SetPortOutput(GPIO_Type * base, uint32_t portOutput) +{ + GPIO_WR_PSOR(base, portOutput); +} + +/*! + * @brief Clears the output level of the GPIO port pins to logic 0. + * + * This function operates all 32 port pins. + * + * @param base GPIO base pointer(PTA, PTB, PTC, etc.) + * @param portOutput mask of GPIO output pins. Each bit represents one pin. For each bit: + * - 0: pin output will not be changed. + * - 1: pin output will be set to logic level 0 + * - LSB: pin 0 + * - MSB: pin 31 + */ +static inline void GPIO_HAL_ClearPortOutput(GPIO_Type * base, uint32_t portOutput) +{ + GPIO_WR_PCOR(base, portOutput); +} + +/*! + * @brief Reverses the current output logic of the GPIO port pins. + * + * This function operates all 32 port pins. + * + * @param base GPIO base pointer(PTA, PTB, PTC, etc.) + * @param portOutput mask of GPIO output pins. Each bit represents one pin. For each bit: + * - 0: pin output will not be changed. + * - 1: pin output logic level will be reversed. + * - LSB: pin 0 + * - MSB: pin 31 + */ +static inline void GPIO_HAL_TogglePortOutput(GPIO_Type * base, uint32_t portOutput) +{ + GPIO_WR_PTOR(base, portOutput); +} + +/* @} */ + +/*! + * @name Input Operation + * @{ + */ + +/*! + * @brief Reads the current input value of the individual GPIO pin. + * + * @param base GPIO base pointer(PTA, PTB, PTC, etc.) + * @param pin GPIO port pin number + * @return GPIO port input value + * - 0: Pin logic level is 0, or is not configured for use by digital function. + * - 1: Pin logic level is 1 + */ +static inline uint32_t GPIO_HAL_ReadPinInput(GPIO_Type * base, uint32_t pin) +{ + assert(pin < 32); + return (GPIO_RD_PDIR(base) >> pin) & 1U; +} + +/*! + * @brief Reads the current input value of a specific GPIO port. + * + * This function gets all 32-pin input as a 32-bit integer. + * + * @param base GPIO base pointer(PTA, PTB, PTC, etc.) + * @return GPIO port input data. Each bit represents one pin. For each bit: + * - 0: Pin logic level is 0, or is not configured for use by digital function. + * - 1: Pin logic level is 1. + * - LSB: pin 0 + * - MSB: pin 31 + */ +static inline uint32_t GPIO_HAL_ReadPortInput(GPIO_Type * base) +{ + return GPIO_RD_PDIR(base); +} + +/* @} */ + +/*! + * @name FGPIO Operation + * + * @note FGPIO (Fast GPIO) is only available in a few MCUs. FGPIO and GPIO share the same + * peripheral but use different registers. FGPIO is closer to the core than the regular GPIO + * and it's faster to read and write. + * @{ + */ + +#if FSL_FEATURE_GPIO_HAS_FAST_GPIO + +/*! + * @name Configuration + * @{ + */ + +/*! + * @brief Sets the individual FGPIO pin to general input or output. + * + * @param base FGPIO base pointer(FPTA, FPTB, FPTC, etc.) + * @param pin FGPIO port pin number + * @param direction FGPIO directions + * - kGpioDigitalInput: set to input + * - kGpioDigitalOutput: set to output + */ +void FGPIO_HAL_SetPinDir(FGPIO_Type * base, uint32_t pin, + gpio_pin_direction_t direction); + +/*! + * @brief Sets the FGPIO port pins to general input or output. + * + * This function operates all 32 port pins. + * + * @param base FGPIO base pointer (FPTA, FPTB, FPTC, etc.) + * @param pinDirectionMap FGPIO directions bit map + * - 0: set to input + * - 1: set to output + * - LSB: pin 0 + * - MSB: pin 31 + */ +static inline void FGPIO_HAL_SetPortDir(FGPIO_Type * base, uint32_t pinDirectionMap) +{ + FGPIO_WR_PDDR(base, pinDirectionMap); +} + +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the current direction of the individual FGPIO pin. + * + * @param base FGPIO base pointer(FPTA, FPTB, FPTC, etc.) + * @param pin FGPIO port pin number + * @return FGPIO directions + * - kGpioDigitalInput: corresponding pin is set to input. + * - kGpioDigitalOutput: corresponding pin is set to output. + */ +static inline gpio_pin_direction_t FGPIO_HAL_GetPinDir(FGPIO_Type * base, uint32_t pin) +{ + assert(pin < 32); + return (gpio_pin_direction_t)((FGPIO_RD_PDDR(base) >> pin) & 1U); +} + +/*! + * @brief Gets the FGPIO port pins direction. + * + * This function gets all 32-pin directions as a 32-bit integer. + * + * @param base FGPIO base pointer (FPTA, FPTB, FPTC, etc.) + * @return FGPIO directions. Each bit represents one pin. For each bit: + * - 0: corresponding pin is set to input + * - 1: corresponding pin is set to output + * - LSB: pin 0 + * - MSB: pin 31 + */ +static inline uint32_t FGPIO_HAL_GetPortDir(FGPIO_Type * base) +{ + return FGPIO_RD_PDDR(base); +} + +/* @} */ + +/*! + * @name Output Operation + * @{ + */ + +/*! + * @brief Sets the output level of the individual FGPIO pin to logic 1 or 0. + * + * @param base FGPIO base pointer(FPTA, FPTB, FPTC, etc.) + * @param pin FGPIO port pin number + * @param output pin output logic level + */ +void FGPIO_HAL_WritePinOutput(FGPIO_Type * base, uint32_t pin, uint32_t output); + +/*! + * @brief Reads the current FGPIOpin output. + * + * @param base FGPIO base pointer (FPTA, FPTB, FPTC, etc.) + * @param pin FGPIO port pin number + * @return current pin output status. 0 - Low logic, 1 - High logic + */ +static inline uint32_t FGPIO_HAL_ReadPinOutput(FGPIO_Type * base, uint32_t pin) +{ + assert(pin < 32); + return ((FGPIO_RD_PDOR(base) >> pin) & 0x1U); +} + +/*! + * @brief Sets the output level of an individual FGPIO pin to logic 1. + * + * @param base GPIO base pointer(FPTA, FPTB, FPTC, etc.) + * @param pin FGPIO port pin number + */ +static inline void FGPIO_HAL_SetPinOutput(FGPIO_Type * base, uint32_t pin) +{ + assert(pin < 32); + FGPIO_WR_PSOR(base, 1U << pin); +} + +/*! + * @brief Clears the output level of an individual FGPIO pin to logic 0. + * + * @param base GPIO base pointer(FPTA, FPTB, FPTC, etc.) + * @param pin FGPIO port pin number + */ +static inline void FGPIO_HAL_ClearPinOutput(FGPIO_Type * base, uint32_t pin) +{ + assert(pin < 32); + FGPIO_WR_PCOR(base, 1U << pin); +} + +/*! + * @brief Reverses the current output logic of an individual FGPIO pin. + * + * @param base GPIO base pointer(FPTA, FPTB, FPTC, etc.) + * @param pin FGPIO port pin number + */ +static inline void FGPIO_HAL_TogglePinOutput(FGPIO_Type * base, uint32_t pin) +{ + assert(pin < 32); + FGPIO_WR_PTOR(base, 1U << pin); +} + +/*! + * @brief Sets the output of the FGPIO port pins to a specific logic value. + * + * This function affects all 32 port pins. + * + * @param base GPIO base pointer(FPTA, FPTB, FPTC, etc.) + * @param portOutput data to configure the GPIO output. Each bit represents one pin. For each bit: + * - 0: set logic level 0 to pin. + * - 1: set logic level 1 to pin. + * - LSB: pin 0 + * - MSB: pin 31 + */ +static inline void FGPIO_HAL_WritePortOutput(FGPIO_Type * base, uint32_t portOutput) +{ + FGPIO_WR_PDOR(base, portOutput); +} + +/*! + * @brief Reads out all pin output status of the current port. + * + * This function operates all 32 port pins. + * + * @param base FGPIO base pointer (FPTA, FPTB, FPTC, etc.) + * @return current port output status. Each bit represents one pin. For each bit: + * - 0: corresponding pin is outputting logic level 0 + * - 1: corresponding pin is outputting logic level 1 + * - LSB: pin 0 + * - MSB: pin 31 + */ +static inline uint32_t FGPIO_HAL_ReadPortOutput(FGPIO_Type * base) +{ + return FGPIO_RD_PDOR(base); +} + +/*! + * @brief Sets the output level of the FGPIO port pins to logic 1. + * + * This function affects all 32 port pins. + * + * @param base FGPIO base pointer(FPTA, FPTB, FPTC, etc.) + * @param portOutput mask of FGPIO output pins. Each bit represents one pin. For each bit: + * - 0: pin output will not be changed. + * - 1: pin output will be set to logic level 1 + * - LSB: pin 0 + * - MSB: pin 31 + */ +static inline void FGPIO_HAL_SetPortOutput(FGPIO_Type * base, uint32_t portOutput) +{ + FGPIO_WR_PSOR(base, portOutput); +} + +/*! + * @brief Clears the output level of the FGPIO port pins to logic 0. + * + * This function affects all 32 port pins. + * + * @param base FGPIO base pointer(FPTA, FPTB, FPTC, etc.) + * @param portOutput mask of FGPIO output pins. Each bit represents one pin. For each bit: + * - 0: pin output will not be changed. + * - 1: pin output will be set to logic level 0 + * - LSB: pin 0 + * - MSB: pin 31 + */ +static inline void FGPIO_HAL_ClearPortOutput(FGPIO_Type * base, uint32_t portOutput) +{ + FGPIO_WR_PCOR(base, portOutput); +} + +/*! + * @brief Reverses the current output logic of the FGPIO port pins. + * + * This function affects all 32 port pins. + * + * @param base FGPIO base pointer(FPTA, FPTB, FPTC, etc.) + * @param portOutput mask of FGPIO output pins. Each bit represents one pin. For each bit: + * - 0: pin output will not be changed. + * - 1: pin output logic level will be reversed. + * - LSB: pin 0 + * - MSB: pin 31 + */ +static inline void FGPIO_HAL_TogglePortOutput(FGPIO_Type * base, uint32_t portOutput) +{ + FGPIO_WR_PTOR(base, portOutput); +} + +/* @} */ + +/*! + * @name Input Operation + * @{ + */ + +/*! + * @brief Gets the current input value of an individual FGPIO pin. + * + * @param base GPIO base pointer(FPTA, FPTB, FPTC, etc.) + * @param pin FGPIO port pin number + * @return FGPIO port input data + * - 0: Pin logic level is 0, or is not configured for use by digital function. + * - 1: Pin logic level is 1. + */ +static inline uint32_t FGPIO_HAL_ReadPinInput(FGPIO_Type * base, uint32_t pin) +{ + assert(pin < 32); + return (FGPIO_RD_PDIR(base) >> pin) & 1U; +} + +/*! + * @brief Gets the current input value of a specific FGPIO port. + * + * This function gets all 32-pin input as a 32-bit integer. + * + * @param base GPIO base pointer(FPTA, FPTB, FPTC, etc.). + * @return FGPIO port input data. Each bit represents one pin. For each bit: + * - 0: Pin logic level is 0, or is not configured for use by digital function. + * - 1: Pin logic level is 1. + * - LSB: pin 0 + * - MSB: pin 31 + */ +static inline uint32_t FGPIO_HAL_ReadPortInput(FGPIO_Type * base) +{ + return FGPIO_RD_PDIR(base); +} + +/* @} */ + +#endif /* FSL_FEATURE_GPIO_HAS_FAST_GPIO*/ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* __FSL_GPIO_HAL_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_i2c_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_i2c_hal.h new file mode 100755 index 0000000..cbdf4f3 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_i2c_hal.h @@ -0,0 +1,811 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#if !defined(__FSL_I2C_HAL_H__) +#define __FSL_I2C_HAL_H__ + +#include <assert.h> +#include <stdbool.h> +#include "fsl_device_registers.h" + +/*! + * @addtogroup i2c_hal + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief I2C status return codes.*/ +typedef enum _i2c_status { + kStatus_I2C_Success = 0x0U, /*!< I2C operation has no error. */ + kStatus_I2C_Initialized = 0x1U, /*!< Current I2C is already initialized by one task.*/ + kStatus_I2C_Fail = 0x2U, /*!< I2C operation failed. */ + kStatus_I2C_Busy = 0x3U, /*!< The master is already performing a transfer.*/ + kStatus_I2C_Timeout = 0x4U, /*!< The transfer timed out.*/ + kStatus_I2C_ReceivedNak = 0x5U, /*!< The slave device sent a NAK in response to a byte.*/ + kStatus_I2C_SlaveTxUnderrun = 0x6U, /*!< I2C Slave TX Underrun error.*/ + kStatus_I2C_SlaveRxOverrun = 0x7U, /*!< I2C Slave RX Overrun error.*/ + kStatus_I2C_AribtrationLost = 0x8U, /*!< I2C Arbitration Lost error.*/ + kStatus_I2C_StopSignalFail = 0x9U, /*!< I2C STOP signal could not release bus. */ + kStatus_I2C_Idle = 0xAU, /*!< I2C Slave Bus is Idle. */ + kStatus_I2C_NoReceiveInProgress= 0xBU, /*!< Attempt to abort a receiving when no transfer + was in progress */ + kStatus_I2C_NoSendInProgress = 0xCU /*!< Attempt to abort a sending when no transfer + was in progress */ +} i2c_status_t; + +/*! @brief I2C status flags. */ +typedef enum _i2c_status_flag { + kI2CTransferComplete = I2C_S_TCF_SHIFT, + kI2CAddressAsSlave = I2C_S_IAAS_SHIFT, + kI2CBusBusy = I2C_S_BUSY_SHIFT, + kI2CArbitrationLost = I2C_S_ARBL_SHIFT, + kI2CAddressMatch = I2C_S_RAM_SHIFT, + kI2CSlaveTransmit = I2C_S_SRW_SHIFT, + kI2CInterruptPending = I2C_S_IICIF_SHIFT, + kI2CReceivedNak = I2C_S_RXAK_SHIFT +} i2c_status_flag_t; + +/*! @brief Direction of master and slave transfers.*/ +typedef enum _i2c_direction { + kI2CReceive = 0U, /*!< Master transmit, slave receive.*/ + kI2CSend = 1U /*!< Master receive, slave transmit.*/ +} i2c_direction_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Module controls + * @{ + */ + +/*! + * @brief Restores the I2C peripheral to reset state. + * + * @param base The I2C peripheral base pointer + */ +void I2C_HAL_Init(I2C_Type * base); + +/*! + * @brief Enables the I2C module operation. + * + * @param base The I2C peripheral base pointer + */ +static inline void I2C_HAL_Enable(I2C_Type * base) +{ + I2C_BWR_C1_IICEN(base, 0x1U); +} + +/*! + * @brief Disables the I2C module operation. + * + * @param base The I2C peripheral base pointer + */ +static inline void I2C_HAL_Disable(I2C_Type * base) +{ + I2C_BWR_C1_IICEN(base, 0x0U); +} + +/*@}*/ + +#if FSL_FEATURE_I2C_HAS_DMA_SUPPORT +/*! + * @name DMA + * @{ + */ + +/*! + * @brief Enables or disables the DMA support. + * + * @param base The I2C peripheral base pointer + * @param enable Pass true to enable DMA transfer signalling + */ +static inline void I2C_HAL_SetDmaCmd(I2C_Type * base, bool enable) +{ + I2C_BWR_C1_DMAEN(base, (uint8_t)enable); +} + +/*! + * @brief Returns whether I2C DMA support is enabled. + * + * @param base The I2C peripheral base pointer. + * @return Whether I2C DMA is enabled or not. + */ +static inline bool I2C_HAL_GetDmaCmd(I2C_Type * base) +{ + return I2C_BRD_C1_DMAEN(base); +} + +/*@}*/ +#endif /* FSL_FEATURE_I2C_HAS_DMA_SUPPORT */ + +/*! + * @name Pin functions + * @{ + */ + +#if FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION +/*! + * @brief Controls the drive capability of the I2C pads. + * + * @param base The I2C peripheral base pointer + * @param enable Passing true will enable high drive mode of the I2C pads. False sets normal + * drive mode. + */ +static inline void I2C_HAL_SetHighDriveCmd(I2C_Type * base, bool enable) +{ + I2C_BWR_C2_HDRS(base, (uint8_t)enable); +} +#endif /* FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION */ + +/*! + * @brief Controls the width of the programmable glitch filter. + * + * Controls the width of the glitch, in terms of bus clock cycles, that the filter must absorb. + * The filter does not allow any glitch whose size is less than or equal to this width setting, + * to pass. + * + * @param base The I2C peripheral base pointer + * @param glitchWidth Maximum width in bus clock cycles of the glitches that is filtered. + * Pass zero to disable the glitch filter. + */ +static inline void I2C_HAL_SetGlitchWidth(I2C_Type * base, uint8_t glitchWidth) +{ + assert(glitchWidth < FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH); + I2C_BWR_FLT_FLT(base, glitchWidth); +} + +/*@}*/ + +/*! + * @name Low power + * @{ + */ + +/*! + * @brief Controls the I2C wakeup enable. + * + * The I2C module can wake the MCU from low power mode with no peripheral bus running when + * slave address matching occurs. + * + * @param base The I2C peripheral base pointer. + * @param enable true - Enables the wakeup function in low power mode.<br> + * false - Normal operation. No interrupt is generated when address matching in + * low power mode. + */ +static inline void I2C_HAL_SetWakeupCmd(I2C_Type * base, bool enable) +{ + I2C_BWR_C1_WUEN(base, (uint8_t)enable); +} + +#if FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF +/*! + * @brief Controls the stop mode hold off. + * + * This function lets you enable the hold off entry to low power stop mode when any data transmission + * or reception is occurring. + * + * @param base The I2C peripheral base pointer + * @param enable false - Stop hold off is disabled. The MCU's entry to stop mode is not gated.<br> + * true - Stop hold off is enabled. + */ + +static inline void I2C_HAL_SetStopHoldoffCmd(I2C_Type * base, bool enable) +{ + I2C_BWR_FLT_SHEN(base, (uint8_t)enable); +} +#endif /* FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF*/ + +/*@}*/ + +/*! + * @name Baud rate + * @{ + */ + +/*! + * @brief Sets the I2C bus frequency for master transactions. + * + * @param base The I2C peripheral base pointer + * @param sourceClockInHz I2C source input clock in Hertz + * @param kbps Requested bus frequency in kilohertz. Common values are either 100 or 400. + * @param absoluteError_Hz If this parameter is not NULL, it is filled in with the + * difference in Hertz between the requested bus frequency and the closest frequency + * possible given available divider values. + */ +void I2C_HAL_SetBaudRate(I2C_Type * base, + uint32_t sourceClockInHz, + uint32_t kbps, + uint32_t * absoluteError_Hz); + +/*! + * @brief Sets the I2C baud rate multiplier and table entry. + * + * Use this function to set the I2C bus frequency register values directly, if they are + * known in advance. + * + * @param base The I2C peripheral base pointer + * @param mult Value of the MULT bitfield, ranging from 0-2. + * @param icr The ICR bitfield value, which is the index into an internal table in the I2C + * hardware that selects the baud rate divisor and SCL hold time. + */ +static inline void I2C_HAL_SetFreqDiv(I2C_Type * base, uint8_t mult, uint8_t icr) +{ + I2C_WR_F(base, I2C_F_MULT(mult) | I2C_F_ICR(icr)); +} + +/*! + * @brief Slave baud rate control + * + * Enables an independent slave mode baud rate at the maximum frequency. This forces clock stretching + * on the SCL in very fast I2C modes. + * + * @param base The I2C peripheral base pointer + * @param enable true - Slave baud rate is independent of the master baud rate;<br> + * false - The slave baud rate follows the master baud rate and clock stretching may occur. + */ +static inline void I2C_HAL_SetSlaveBaudCtrlCmd(I2C_Type * base, bool enable) +{ + I2C_BWR_C2_SBRC(base, (uint8_t)enable); +} + +/*@}*/ + +/*! + * @name Bus operations + * @{ + */ + +/*! + * @brief Sends a START or a Repeated START signal on the I2C bus. + * + * This function is used to initiate a new master mode transfer by sending the START signal. It + * is also used to send a Repeated START signal when a transfer is already in progress. + * + * @param base The I2C peripheral base pointer + */ +void I2C_HAL_SendStart(I2C_Type * base); + +/*! + * @brief Sends a STOP signal on the I2C bus. + * + * This function changes the direction to receive. + * + * @param base The I2C peripheral base pointer + * @return Whether the sending of STOP single is success or not. + */ +i2c_status_t I2C_HAL_SendStop(I2C_Type * base); + +/*! + * @brief Causes an ACK to be sent on the bus. + * + * This function specifies that an ACK signal is sent in response to the next received byte. + * + * Note that the behavior of this function is changed when the I2C peripheral is placed in + * Fast ACK mode. In this case, this function causes an ACK signal to be sent in + * response to the current byte, rather than the next received byte. + * + * @param base The I2C peripheral base pointer + */ +static inline void I2C_HAL_SendAck(I2C_Type * base) +{ + I2C_BWR_C1_TXAK(base, 0x0U); +} + +/*! + * @brief Causes a NAK to be sent on the bus. + * + * This function specifies that a NAK signal is sent in response to the next received byte. + * + * Note that the behavior of this function is changed when the I2C peripheral is placed in the + * Fast ACK mode. In this case, this function causes an NAK signal to be sent in + * response to the current byte, rather than the next received byte. + * + * @param base The I2C peripheral base pointer + */ +static inline void I2C_HAL_SendNak(I2C_Type * base) +{ + I2C_BWR_C1_TXAK(base, 0x1U); +} + +/*! + * @brief Selects either transmit or receive mode. + * + * @param base The I2C peripheral base pointer. + * @param direction Specifies either transmit mode or receive mode. The valid values are: + * - #kI2CTransmit + * - #kI2CReceive + */ +static inline void I2C_HAL_SetDirMode(I2C_Type * base, i2c_direction_t direction) +{ + I2C_BWR_C1_TX(base, (uint8_t)direction); +} + +/*! + * @brief Returns the currently selected transmit or receive mode. + * + * @param base The I2C peripheral base pointer. + * @return Current I2C transfer mode. + * @retval #kI2CTransmit I2C is configured for master or slave transmit mode. + * @retval #kI2CReceive I2C is configured for master or slave receive mode. + */ +static inline i2c_direction_t I2C_HAL_GetDirMode(I2C_Type * base) +{ + return (i2c_direction_t)I2C_BRD_C1_TX(base); +} + +/*@}*/ + +/*! + * @name Data transfer + * @{ + */ + +/*! + * @brief Returns the last byte of data read from the bus and initiate another read. + * + * In a master receive mode, calling this function initiates receiving the next byte of data. + * + * @param base The I2C peripheral base pointer + * @return This function returns the last byte received while the I2C module is configured in master + * receive or slave receive mode. + */ +static inline uint8_t I2C_HAL_ReadByte(I2C_Type * base) +{ + return I2C_RD_D(base); +} + +/*! + * @brief Writes one byte of data to the I2C bus. + * + * When this function is called in the master transmit mode, a data transfer is initiated. In slave + * mode, the same function is available after an address match occurs. + * + * In a master transmit mode, the first byte of data written following the start bit or repeated + * start bit is used for the address transfer and must consist of the slave address (in bits 7-1) + * concatenated with the required R/\#W bit (in position bit 0). + * + * @param base The I2C peripheral base pointer. + * @param byte The byte of data to transmit. + */ +static inline void I2C_HAL_WriteByte(I2C_Type * base, uint8_t byte) +{ +#if FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING + while (!I2C_BRD_S2_EMPTY(base)) + {} +#endif + + I2C_WR_D(base, byte); +} + +/*! + * @brief Returns the last byte of data read from the bus and initiate another read. + * It will wait till the transfer is actually completed. + * + * @param base The I2C peripheral base pointer + * @return Returns the last byte received + */ +uint8_t I2C_HAL_ReadByteBlocking(I2C_Type * base); + +/*! + * @brief Writes one byte of data to the I2C bus and wait till that byte is + * transfered successfully. + * + * @param base The I2C peripheral base pointer. + * @param byte The byte of data to transmit. + * @return Whether ACK is received(TRUE) or not(FALSE). + */ +bool I2C_HAL_WriteByteBlocking(I2C_Type * base, uint8_t byte); + +/*! + * @brief Performs a polling receive transaction on the I2C bus. + * + * @param base The I2C peripheral base pointer. + * @param slaveAddr The slave address to communicate. + * @param cmdBuff The pointer to the commands to be transferred. + * @param cmdSize The length in bytes of the commands to be transferred. + * @param rxBuff The pointer to the data to be transferred. + * @param rxSize The length in bytes of the data to be transferred. + * @return Error or success status returned by API. + */ +i2c_status_t I2C_HAL_MasterReceiveDataPolling(I2C_Type * base, + uint16_t slaveAddr, + const uint8_t * cmdBuff, + uint32_t cmdSize, + uint8_t * rxBuff, + uint32_t rxSize); + +/*! + * @brief Performs a polling send transaction on the I2C bus. + * + * @param base The I2C peripheral base pointer. + * @param slaveAddr The slave address to communicate. + * @param cmdBuff The pointer to the commands to be transferred. + * @param cmdSize The length in bytes of the commands to be transferred. + * @param txBuff The pointer to the data to be transferred. + * @param txSize The length in bytes of the data to be transferred. + * @return Error or success status returned by API. + */ +i2c_status_t I2C_HAL_MasterSendDataPolling(I2C_Type * base, + uint16_t slaveAddr, + const uint8_t * cmdBuff, + uint32_t cmdSize, + const uint8_t * txBuff, + uint32_t txSize); + +/*! +* @brief Send out multiple bytes of data using polling method. +* +* @param base I2C module base pointer. +* @param txBuff The buffer pointer which saves the data to be sent. +* @param txSize Size of data to be sent in unit of byte. +* @return Whether the transaction is success or not. +* @retval kStatus_I2C_ReceivedNak if received NACK bit +* @retval Error or success status returned by API. +*/ +i2c_status_t I2C_HAL_SlaveSendDataPolling(I2C_Type * base, const uint8_t* txBuff, uint32_t txSize); + +/*! +* @brief Receive multiple bytes of data using polling method. +* +* @param base I2C module base pointer. +* @param rxBuff The buffer pointer which saves the data to be received. +* @param rxSize Size of data need to be received in unit of byte. +* @return Error or success status returned by API. +*/ +i2c_status_t I2C_HAL_SlaveReceiveDataPolling(I2C_Type * base, uint8_t *rxBuff, uint32_t rxSize); + +/*@}*/ + +/*! + * @name Slave address + * @{ + */ + +/*! + * @brief Sets the primary 7-bit slave address. + * + * @param base The I2C peripheral base pointer + * @param address The slave address in the upper 7 bits. Bit 0 of this value must be 0. + */ +void I2C_HAL_SetAddress7bit(I2C_Type * base, uint8_t address); + +/*! + * @brief Sets the primary slave address and enables 10-bit address mode. + * + * @param base The I2C peripheral base pointer + * @param address The 10-bit slave address, in bits [10:1] of the value. Bit 0 must be 0. + */ +void I2C_HAL_SetAddress10bit(I2C_Type * base, uint16_t address); + +/*! + * @brief Enables or disables the extension address (10-bit). + * + * @param base The I2C peripheral base pointer + * @param enable true: 10-bit address is enabled. + * false: 10-bit address is not enabled. + */ +static inline void I2C_HAL_SetExtensionAddrCmd(I2C_Type * base, bool enable) +{ + I2C_BWR_C2_ADEXT(base, (uint8_t)enable); +} + +/*! + * @brief Returns whether the extension address is enabled or not. + * + * @param base The I2C peripheral base pointer + * @return true: 10-bit address is enabled. + * false: 10-bit address is not enabled. + */ +static inline bool I2C_HAL_GetExtensionAddrCmd(I2C_Type * base) +{ + return I2C_BRD_C2_ADEXT(base); +} + +/*! + * @brief Controls whether the general call address is recognized. + * + * @param base The I2C peripheral base pointer + * @param enable Whether to enable the general call address. + */ +static inline void I2C_HAL_SetGeneralCallCmd(I2C_Type * base, bool enable) +{ + I2C_BWR_C2_GCAEN(base, (uint8_t)enable); +} + +/*! + * @brief Enables or disables the slave address range matching. + * + * @param base The I2C peripheral base pointer. + * @param enable Pass true to enable range address matching. You must also call + * I2C_HAL_SetUpperAddress7bit() to set the upper address. + */ +static inline void I2C_HAL_SetRangeMatchCmd(I2C_Type * base, bool enable) +{ + I2C_BWR_C2_RMEN(base, (uint8_t)enable); +} + +/*! + * @brief Sets the upper slave address. + * + * This slave address is used as a secondary slave address. If range address + * matching is enabled, this slave address acts as the upper bound on the slave address + * range. + * + * This function sets only a 7-bit slave address. If 10-bit addressing was enabled by calling + * I2C_HAL_SetAddress10bit(), then the top 3 bits set with that function are also used + * with the address set with this function to form a 10-bit address. + * + * Passing 0 for the @a address parameter disables matching the upper slave address. + * + * @param base The I2C peripheral base pointer + * @param address The upper slave address in the upper 7 bits. Bit 0 of this value must be 0. + * In addition, this address must be greater than the primary slave address that is set by + * calling I2C_HAL_SetAddress7bit(). + */ +static inline void I2C_HAL_SetUpperAddress7bit(I2C_Type * base, uint8_t address) +{ + assert((address & 1) == 0); + assert((address == 0) || (address > I2C_RD_A1(base))); + I2C_WR_RA(base, address); +} + +/*@}*/ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the I2C status flag state. + * + * @param base The I2C peripheral base pointer. + * @param statusFlag The status flag, defined in type i2c_status_flag_t. + * @return State of the status flag: asserted (true) or not-asserted (false). + * - true: related status flag is being set. + * - false: related status flag is not set. + */ +static inline bool I2C_HAL_GetStatusFlag(I2C_Type * base, i2c_status_flag_t statusFlag) +{ + return (bool)((I2C_RD_S(base) >> statusFlag) & 0x1U); +} + +/*! + * @brief Returns whether the I2C module is in master mode. + * + * @param base The I2C peripheral base pointer. + * @return Whether current I2C is in master mode or not. + * @retval true The module is in master mode, which implies it is also performing a transfer. + * @retval false The module is in slave mode. + */ +static inline bool I2C_HAL_IsMaster(I2C_Type * base) +{ + return (bool)I2C_BRD_C1_MST(base); +} + +/*! + * @brief Clears the arbitration lost flag. + * + * @param base The I2C peripheral base pointer + */ +static inline void I2C_HAL_ClearArbitrationLost(I2C_Type * base) +{ + I2C_WR_S(base, I2C_S_ARBL_MASK); +} + +/*@}*/ + +/*! + * @name Interrupt + * @{ + */ + +/*! + * @brief Enables or disables I2C interrupt requests. + * + * @param base The I2C peripheral base pointer + * @param enable Pass true to enable interrupt, false to disable. + */ +static inline void I2C_HAL_SetIntCmd(I2C_Type * base, bool enable) +{ + I2C_BWR_C1_IICIE(base, (uint8_t)enable); +} + +/*! + * @brief Returns whether the I2C interrupts are enabled. + * + * @param base The I2C peripheral base pointer + * @return Whether I2C interrupts are enabled or not. + */ +static inline bool I2C_HAL_GetIntCmd(I2C_Type * base) +{ + return (bool)I2C_BRD_C1_IICIE(base); +} + +/*! + * @brief Returns the current I2C interrupt flag. + * + * @param base The I2C peripheral base pointer + * @return Whether I2C interrupt is pending or not. + */ +static inline bool I2C_HAL_IsIntPending(I2C_Type * base) +{ + return (bool)I2C_BRD_S_IICIF(base); +} + +/*! + * @brief Clears the I2C interrupt if set. + * + * @param base The I2C peripheral base pointer + */ +static inline void I2C_HAL_ClearInt(I2C_Type * base) +{ + I2C_WR_S(base, I2C_S_IICIF_MASK); +} + +/*@}*/ + +#if FSL_FEATURE_I2C_HAS_START_STOP_DETECT || FSL_FEATURE_I2C_HAS_STOP_DETECT + +/*! + * @name Bus stop detection flag + * @{ + */ + +/*! + * @brief Gets the flag indicating a STOP signal was detected on the I2C bus. + * + * @param base The I2C peripheral base pointer + * @return Whether a STOP signal is detected on bus or not. + */ +static inline bool I2C_HAL_GetStopFlag(I2C_Type * base) +{ + return (bool)I2C_BRD_FLT_STOPF(base); +} + +/*! + * @brief Clears the bus STOP signal detected flag. + * + * @param base The I2C peripheral base pointer + */ +static inline void I2C_HAL_ClearStopFlag(I2C_Type * base) +{ + I2C_BWR_FLT_STOPF(base, 0x1U); +} + +/*@}*/ +#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT || FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ + +#if FSL_FEATURE_I2C_HAS_STOP_DETECT + +/*! + * @name Bus stop detection interrupt + * @{ + */ + +/*! + * @brief Enables the I2C bus stop detection interrupt. + * + * @param base The I2C peripheral base pointer. + * @param enable Pass true to enable interrupt, false to disable. + */ +static inline void I2C_HAL_SetStopIntCmd(I2C_Type * base, bool enable) +{ + I2C_BWR_FLT_STOPIE(base, enable); +} + +/*! + * @brief Returns whether the I2C bus stop detection interrupts are enabled. + * + * @param base The I2C peripheral base pointer + * @return Whether the STOP detection interrupt is enabled or not. + */ +static inline bool I2C_HAL_GetStopIntCmd(I2C_Type * base) +{ + return (bool)I2C_BRD_FLT_STOPIE(base); +} + +/*@}*/ + +#endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT */ + +#if FSL_FEATURE_I2C_HAS_START_STOP_DETECT + +/*! + * @name Bus start/stop detection interrupt + * @{ + */ + +/*! + * @brief Enables the I2C bus start/stop detection interrupt. + * + * @param base The I2C peripheral base pointer + * @param enable Pass true to enable interrupt, flase to disable. + */ +static inline void I2C_HAL_SetStartStopIntCmd(I2C_Type * base, bool enable) +{ + I2C_BWR_FLT_SSIE(base, enable); +} + +/*! + * @brief Returns whether the I2C bus start/stop detection interrupts are enabled. + * + * @param base The I2C peripheral base pointer + * @return Whether stop detect interrupt is enabled or not. + */ +static inline bool I2C_HAL_GetStartStopIntCmd(I2C_Type * base) +{ + return (bool)I2C_BRD_FLT_SSIE(base); +} + +/*! + * @brief Gets the flag indicating a START signal was detected on the I2C bus. + * + * @param base The I2C peripheral base pointer + * @return Whether START signal is detected on bus or not. + */ +static inline bool I2C_HAL_GetStartFlag(I2C_Type * base) +{ + return (bool)I2C_BRD_FLT_STARTF(base); +} + +/*! + * @brief Clears the bus START signal detected flag. + * + * @param base The I2C peripheral base pointer + */ +static inline void I2C_HAL_ClearStartFlag(I2C_Type * base) +{ + I2C_BWR_FLT_STARTF(base, 0x1U); +} + +/*@}*/ + +#endif /* FSL_FEATURE_I2C_HAS_START_STOP_DETECT */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* __FSL_I2C_HAL_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_llwu_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_llwu_hal.h new file mode 100755 index 0000000..daf9355 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_llwu_hal.h @@ -0,0 +1,352 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#if !defined(__FSL_LLWU_HAL_H__) +#define __FSL_LLWU_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> +#include <assert.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_LLWU_COUNT + +/*! @addtogroup llwu_hal*/ +/*! @{*/ + +/*! @file fsl_llwu_hal.h */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief External input pin control modes */ +typedef enum _llwu_external_pin_modes { + kLlwuExternalPinDisabled, /*!< Pin disabled as wakeup input */ + kLlwuExternalPinRisingEdge, /*!< Pin enabled with rising edge detection */ + kLlwuExternalPinFallingEdge, /*!< Pin enabled with falling edge detection */ + kLlwuExternalPinChangeDetect /*!< Pin enabled with any change detection */ +} llwu_external_pin_modes_t; + +/*! @brief Digital filter control modes */ +typedef enum _llwu_filter_modes { + kLlwuFilterDisabled, /*!< Filter disabled */ + kLlwuFilterPosEdgeDetect, /*!< Filter positive edge detection */ + kLlwuFilterNegEdgeDetect, /*!< Filter negative edge detection */ + kLlwuFilterAnyEdgeDetect /*!< Filter any edge detection */ +} llwu_filter_modes_t; + +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN +/*! @brief LLWU external wakeup pin. */ +typedef enum _llwu_wakeup_pin { +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 + kLlwuWakeupPin0 = 0U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 + kLlwuWakeupPin1 = 1U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 + kLlwuWakeupPin2 = 2U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 + kLlwuWakeupPin3 = 3U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 + kLlwuWakeupPin4 = 4U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 + kLlwuWakeupPin5 = 5U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 + kLlwuWakeupPin6 = 6U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 + kLlwuWakeupPin7 = 7U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 + kLlwuWakeupPin8 = 8U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 + kLlwuWakeupPin9 = 9U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 + kLlwuWakeupPin10 = 10U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 + kLlwuWakeupPin11 = 11U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 + kLlwuWakeupPin12 = 12U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 + kLlwuWakeupPin13 = 13U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 + kLlwuWakeupPin14 = 14U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 + kLlwuWakeupPin15 = 15U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 + kLlwuWakeupPin16 = 16U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 + kLlwuWakeupPin17 = 17U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 + kLlwuWakeupPin18 = 18U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 + kLlwuWakeupPin19 = 19U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 + kLlwuWakeupPin20 = 20U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 + kLlwuWakeupPin21 = 21U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 + kLlwuWakeupPin22 = 22U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 + kLlwuWakeupPin23 = 23U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 + kLlwuWakeupPin24 = 24U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 + kLlwuWakeupPin25 = 25U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 + kLlwuWakeupPin26 = 26U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 + kLlwuWakeupPin27 = 27U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 + kLlwuWakeupPin28 = 28U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 + kLlwuWakeupPin29 = 29U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 + kLlwuWakeupPin30 = 30U, +#endif +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 + kLlwuWakeupPin31 = 31U +#endif +} llwu_wakeup_pin_t; +#endif + +#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE +/*! @brief LLWU wakeup module. */ +typedef enum _llwu_wakeup_module { +#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 + kLlwuWakeupModule0 = 0U, +#endif +#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 + kLlwuWakeupModule1 = 1U, +#endif +#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 + kLlwuWakeupModule2 = 2U, +#endif +#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 + kLlwuWakeupModule3 = 3U, +#endif +#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 + kLlwuWakeupModule4 = 4U, +#endif +#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 + kLlwuWakeupModule5 = 5U, +#endif +#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 + kLlwuWakeupModule6 = 6U, +#endif +#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 + kLlwuWakeupModule7 = 7U +#endif +} llwu_wakeup_module_t; +#endif + +/*! @brief External input pin filter control structure */ +typedef struct _llwu_external_pin_filter_mode { + llwu_filter_modes_t filterMode; /*!< Filter mode */ + llwu_wakeup_pin_t pinNumber; /*!< Pin number */ +} llwu_external_pin_filter_mode_t; + +/*! @brief Reset pin control structure */ +typedef struct _llwu_reset_pin_mode { + bool enable; /*!< RESET pin is enabled as low-leakage mode exit source. */ + bool filter; /*!< Digital filter on RESET pin. */ +} llwu_reset_pin_mode_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Low-Leakage Wakeup Unit Control APIs + * @{ + */ + +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN +/*! + * @brief Sets the external input pin source mode. + * + * This function sets the external input pin source mode that is used + * as a wake up source. + * + * @param base Register base address of LLWU + * @param pinMode pin configuration mode defined in llwu_external_pin_modes_t + * @param pinNumber pin number specified + */ +void LLWU_HAL_SetExternalInputPinMode(LLWU_Type * base, + llwu_external_pin_modes_t pinMode, + llwu_wakeup_pin_t pinNumber); + +#endif + +#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE +/*! + * @brief Enables/disables the internal module source. + * + * This function enables/disables the internal module source mode that is used + * as a wake up source. + * + * @param base Register base address of LLWU + * @param moduleNumber module number specified + * @param enable enable or disable setting + */ +void LLWU_HAL_SetInternalModuleCmd(LLWU_Type * base, llwu_wakeup_module_t moduleNumber, bool enable); +#endif + +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN +/*! + * @brief Gets the external wakeup source flag. + * + * This function checks the external pin flag to detect whether the MCU is + * woke up by the specific pin. + * + * @param base Register base address of LLWU + * @param pinNumber pin number specified + * @return true if the specific pin is wake up source. + */ +bool LLWU_HAL_GetExternalPinWakeupFlag(LLWU_Type * base, llwu_wakeup_pin_t pinNumber); + +/*! + * @brief Clears the external wakeup source flag. + * + * This function clears the external wakeup source flag for a specific pin. + * + * @param base Register base address of LLWU + * @param pinNumber pin number specified + */ +void LLWU_HAL_ClearExternalPinWakeupFlag(LLWU_Type * base, llwu_wakeup_pin_t pinNumber); +#endif + +#if FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE +/*! + * @brief Gets the internal module wakeup source flag. + * + * This function checks the internal module wake up flag to detect whether the MCU is + * woke up by the specific internal module. + * + * @param base Register base address of LLWU + * @param moduleNumber module number specified + * @return true if the specific module is wake up source. + */ +bool LLWU_HAL_GetInternalModuleWakeupFlag(LLWU_Type * base, llwu_wakeup_module_t moduleNumber); +#endif + +#if FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN +/*! + * @brief Sets the pin filter configuration. + * + * This function sets the pin filter configuration. + * + * @param base Register base address of LLWU + * @param filterNumber filter number specified + * @param pinFilterMode filter mode configuration + */ +void LLWU_HAL_SetPinFilterMode(LLWU_Type * base, uint32_t filterNumber, + llwu_external_pin_filter_mode_t pinFilterMode); + +/*! + * @brief Gets the filter detect flag. + * + * This function checks the filter detect flag to detect whether the external + * pin selected by the specific filter is the wake up source. + * + * @param base Register base address of LLWU + * @param filterNumber filter number specified + * @return true if the the pin is wakeup source + */ +bool LLWU_HAL_GetFilterDetectFlag(LLWU_Type * base, uint32_t filterNumber); + +/*! + * @brief Clears the filter detect flag. + * + * This function will clear the filter detect flag. + * + * @param base Register base address of LLWU + * @param filterNumber filter number specified + */ +void LLWU_HAL_ClearFilterDetectFlag(LLWU_Type * base, uint32_t filterNumber); +#endif + +#if FSL_FEATURE_LLWU_HAS_RESET_ENABLE +/*! + * @brief Sets the RESET pin mode. + * + * This function sets how the RESET pin is used as low leakage mode exit source. + * + * @param base Register base address of LLWU + * @param resetPinMode RESET pin mode defined in llwu_reset_pin_mode_t + */ +void LLWU_HAL_SetResetPinMode(LLWU_Type * base, llwu_reset_pin_mode_t resetPinMode); + +#endif + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif +#endif /* __FSL_LLWU_HAL_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_lmem_cache_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_lmem_cache_hal.h new file mode 100755 index 0000000..927f524 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_lmem_cache_hal.h @@ -0,0 +1,462 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#if !defined(__FSL_LMEM_CACHE_HAL_H__) +#define __FSL_LMEM_CACHE_HAL_H__ + +#include "fsl_device_registers.h" +#include <stdint.h> +#include <stdbool.h> + +#if FSL_FEATURE_SOC_LMEM_COUNT + +/*! + * @addtogroup local_memory_controller_cache_hal + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Error codes for the LMEM CACHE driver. */ +typedef enum _lmem_cache_status +{ + kStatus_LMEM_CACHE_Success = 0, + kStatus_LMEM_CACHE_Busy, /*!< CACHE busy performing an operation*/ + kStatus_LMEM_CACHE_DemoteError, /*!< CACHE region demotion error */ + kStatus_LMEM_CACHE_Error, /*!< CACHE driver error */ +} lmem_cache_status_t; + +/*! @brief LMEM CACHE mode options. */ +typedef enum _lmem_cache_mode { + kCacheNonCacheable = 0x0U, /*!< CACHE mode: non-cacheable */ + kCacheWriteThrough = 0x2U, /*!< CACHE mode: write-through */ + kCacheWriteBack = 0x3U, /*!< CACHE mode: write-back */ +} lmem_cache_mode_t; + +/*! @brief LMEM CACHE Regions. */ +typedef enum _lmem_cache_region { + kCacheRegion0 = 0U, /*!< Cache Region 0 */ + kCacheRegion1 = 1U, /*!< Cache Region 1 */ + kCacheRegion2 = 2U, /*!< Cache Region 2 */ + kCacheRegion3 = 3U, /*!< Cache Region 3 */ + kCacheRegion4 = 4U, /*!< Cache Region 4 */ + kCacheRegion5 = 5U, /*!< Cache Region 5 */ + kCacheRegion6 = 6U, /*!< Cache Region 6 */ + kCacheRegion7 = 7U, /*!< Cache Region 7 */ + kCacheRegion8 = 8U, /*!< Cache Region 8 */ + kCacheRegion9 = 9U, /*!< Cache Region 9 */ + kCacheRegion10 = 10U, /*!< Cache Region 10 */ + kCacheRegion11 = 11U, /*!< Cache Region 11 */ + kCacheRegion12 = 12U, /*!< Cache Region 12 */ + kCacheRegion13 = 13U, /*!< Cache Region 13 */ + kCacheRegion14 = 14U, /*!< Cache Region 14 */ + kCacheRegion15 = 15U /*!< Cache Region 15 */ +} lmem_cache_region_t; + +/*! @brief LMEM CACHE line command. */ +typedef enum _lmem_cache_way { + kCacheLineSearchReadOrWrite = 0U, /*!< Cache line search and read or write */ + kCacheLineInvalidate = 1U, /*!< Cache line invalidate */ + kCacheLinePush = 2U, /*!< Cache line push */ + kCacheLineClear = 3U, /*!< Cache line clear */ +} lmem_cache_line_command_t; + +/*! @brief LMEM CACHE Line Size in bytes. */ +#define LMEM_CACHE_LINE_SIZE 0x10 /*!< Cache line is 32 bytes (or 4-words) */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Processor Code Bus Cache Control + *@{ + */ + +/*! + * @brief Enables or disables the Processor Code bus cache and write buffer. + * + * This function enables or disables the Processor Code bus cache and write buffer. + * + * @param base Module base pointer of type LMEM_Type. + * @param enable Enable (true) or disable (false) the Processor Code bus cache and write buffer + */ +static inline void LMEM_HAL_SetCodeCacheEnableCmd(LMEM_Type * base, bool enable) +{ + LMEM_BWR_PCCCR_ENCACHE(base, (enable == true)); + LMEM_BWR_PCCCR_ENWRBUF(base, (enable == true)); +} + +/*! + * @brief Enable or disable the Processor Code bus option to invalidate all lines. + * + * This function enables or disables the Processor Code bus option to invalidate all + * lines in both WAYs. + * + * @param base Module base pointer of type LMEM_Type. + * @param enable Enable (true) or disable (false) the Processor Code bus option to + * invalidate all lines + */ +void LMEM_HAL_SetCodeCacheInvalidateAllCmd(LMEM_Type * base, bool enable); + +/*! + * @brief Enable or disable the Processor Code bus option to push all modified lines. + * + * This function enables or disables the Processor Code bus option to push all modified + * lines to both WAYs. + * + * @param base Module base pointer of type LMEM_Type. + * @param enable Enable (true) or disable (false) the Processor Code bus option to push + all modified lines + */ +void LMEM_HAL_SetCodeCachePushAllCmd(LMEM_Type * base, bool enable); + +/*! + * @brief Enable or disable the Processor Code bus option to push and invalidate all modified + * lines. + * + * This function enables or disables the Processor Code bus option to push and invalidate all + * modified lines. + * + * @param base Module base pointer of type LMEM_Type. + * @param enable Enable (true) or disable (false) the Processor Code bus option to push + all modified lines + */ +void LMEM_HAL_SetCodeCacheClearAllCmd(LMEM_Type * base, bool enable); + +/*! + * @brief Initiate the Processor Code bus cache command. + * + * This function initiates the Processor Code bus cache command to execute + * an invalidate command and/or push command. + * + * @param base Module base pointer of type LMEM_Type. + */ +static inline void LMEM_HAL_InitiateCodeCacheCommand(LMEM_Type * base) +{ + LMEM_BWR_PCCCR_GO(base, true); +} + +/*! + * @brief Returns whether or not the Processor Code bus cache command is in progress. + * + * This function returns the state of the Processor Code bus cache command. The + * command is either active (in progress) or idle. + * + * @param base Module base pointer of type LMEM_Type. + * @return True if the cache command is in progress or false if the command is idle + */ +static inline bool LMEM_HAL_IsCodeCacheCommandActive(LMEM_Type * base) +{ + return (bool)LMEM_RD_PCCCR_GO(base); +} + + +/*! + * @brief Initiate the Processor Code bus cache line command. + * + * This function initiates the Processor Code bus cache line command to execute + * a search and read or write command, an invalidate command, a push command, or + * a clear command. + * + * @param base Module base pointer of type LMEM_Type. + */ +static inline void LMEM_HAL_InitiateCodeCacheLineCommand(LMEM_Type * base) +{ + LMEM_BWR_PCCLCR_LGO(base, true); +} + + +/*! + * @brief Returns whether or not the Processor Code bus cache line command is in + * progress. + * + * This function returns the state of the Processor Code bus cache line command. The + * command is either active (in progress) or idle. + * + * @param base Module base pointer of type LMEM_Type. + * @return True if the cache line command is in progress or false if the command is idle + */ +static inline bool LMEM_HAL_IsCodeCacheLineCommandActive(LMEM_Type * base) +{ + return (bool)LMEM_RD_PCCLCR_LGO(base); +} + +/*! + * @brief Sets the cache line command for the Processor Code bus. + * + * This function sets the cache line command for the Processor Code bus. The + * command can be search and read or write, invalidate, push, or clear. + * + * @param base Module base pointer of type LMEM_Type. + * @param command The cache line command of type lmem_cache_line_command_t + */ +static inline void LMEM_HAL_SetCodeCacheLineCommand(LMEM_Type * base, + lmem_cache_line_command_t command) +{ + LMEM_BWR_PCCLCR_LCMD(base, command); +} + +/*! + * @brief Sets the physical address for cache line commands for the Processor + * Code bus. + * + * This function sets the physical address for cache line commands for the Processor + * Code bus. The commands are specified in the CLCR[LADSEL] bits. + * + * @param base Module base pointer of type LMEM_Type. + * @param addr The physical address for cache line commands + */ +static inline void LMEM_HAL_SetCodeCachePhysicalAddr(LMEM_Type * base, uint32_t addr) +{ + LMEM_WR_PCCSAR(base, (addr & LMEM_PCCSAR_PHYADDR_MASK)); +} + +/*! + * @brief Sets the cache mode for a specific region for the Processor + * Code bus. + * + * This function sets the cache mode for a specific region for the Processor + * Code bus. Note that you can only demote the cache mode. + * + * @param base Module base pointer of type LMEM_Type. + * @param region The region to demote the cache mode of type lmem_cache_region_t + * @param cacheMode The specified demoted cache mode of type lmem_cache_mode_t + */ +void LMEM_HAL_SetCodeCacheRegionMode(LMEM_Type * base, lmem_cache_region_t region, + lmem_cache_mode_t cacheMode); + +/*! + * @brief Gets the current cache mode for a specific region for the Processor + * Code bus. + * + * This function gets the current cache mode for a specific region for the Processor + * Code bus. + * + * @param base Module base pointer of type LMEM_Type. + * @param region The region to obtain the cache mode of type lmem_cache_region_t + * @return The current cache mode for the specified region + */ +uint32_t LMEM_HAL_GetCodeCacheRegionMode(LMEM_Type * base, lmem_cache_region_t region); + +/*@}*/ + +#if FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE +/*! + * @name Processor System Bus Cache Control + *@{ + */ + +/*! + * @brief Enables or disables the Processor System bus cache and write buffer. + * + * This function enables or disables the Processor System bus cache and write buffer. + * + * @param base Module base pointer of type LMEM_Type. + * @param enable Enable (true) or disable (false) the Processor Code bus cache and write buffer + */ +static inline void LMEM_HAL_SetSystemCacheEnableCmd(LMEM_Type * base, bool enable) +{ + LMEM_BWR_PSCCR_ENCACHE(base, (enable == true)); + LMEM_BWR_PSCCR_ENWRBUF(base, (enable == true)); +} + +/*! + * @brief Enable or disable the Processor System bus option to invalidate all lines. + * + * This function enables or disables the Processor System bus option to invalidate all + * lines in both WAYs. + * + * @param base Module base pointer of type LMEM_Type. + * @param enable Enable (true) or disable (false) the Processor System bus option to + * invalidate all lines + */ +void LMEM_HAL_SetSystemCacheInvalidateAllCmd(LMEM_Type * base, bool enable); + +/*! + * @brief Enable or disable the Processor System bus option to push all modified lines. + * + * This function enables or disables the Processor System bus option to push all + * modified lines to both WAYs. + * + * @param base Module base pointer of type LMEM_Type. + * @param enable Enable (true) or disable (false) the Processor System bus option to + * push all modified lines + */ +void LMEM_HAL_SetSystemCachePushAllCmd(LMEM_Type * base, bool enable); + +/*! + * @brief Enable or disable the Processor System bus option to push and invalidate all modified + * lines. + * + * This function enables or disables the Processor System bus option to push and invalidate all + * modified lines to both WAYs. + * + * @param base Module base pointer of type LMEM_Type. + * @param enable Enable (true) or disable (false) the Processor System bus option to + * push all modified lines + */ +void LMEM_HAL_SetSystemCacheClearAllCmd(LMEM_Type * base, bool enable); + +/*! + * @brief Initiate the Processor System bus cache command. + * + * This function initiates the Processor System bus cache command to execute + * an invalidate command and/or push command. + * + * @param base Module base pointer of type LMEM_Type. + */ +static inline void LMEM_HAL_InitiateSystemCacheCommand(LMEM_Type * base) +{ + LMEM_BWR_PSCCR_GO(base, true); +} + +/*! + * @brief Returns whether or not the Processor System bus cache command is in progress. + * + * This function returns the state of the Processor System bus cache command. The + * command is either active (in progress) or idle. + * + * @param base Module base pointer of type LMEM_Type. + * @return True if the cache command is in progress or false if the command is idle + */ +static inline bool LMEM_HAL_IsSystemCacheCommandActive(LMEM_Type * base) +{ + return (bool)LMEM_RD_PSCCR_GO(base); +} + +/*! + * @brief Initiate the Processor System bus cache line command. + * + * This function initiates the Processor System bus cache command to execute + * a search and read or write command, an invalidate command, a push command, or + * a clear command. + * + * @param base Module base pointer of type LMEM_Type. + */ +static inline void LMEM_HAL_InitiateSystemCacheLineCommand(LMEM_Type * base) +{ + LMEM_BWR_PSCLCR_LGO(base, true); +} + +/*! + * @brief Returns whether or not the Processor System bus cache line command is in + * progress. + * + * This function returns the state of the Processor System bus cache line command. The + * command is either active (in progress) or idle. + * + * @param base Module base pointer of type LMEM_Type. + * @return True if the cache line command is in progress or false if the command is idle + */ +static inline bool LMEM_HAL_IsSystemCacheLineCommandActive(LMEM_Type * base) +{ + return (bool)LMEM_RD_PSCLCR_LGO(base); +} + +/*! + * @brief Sets the cache line command for the Processor System bus. + * + * This function sets the cache line command for the Processor System bus. The + * command can be search and read or write, invalidate, push, or clear. + * + * @param base Module base pointer of type LMEM_Type. + * @param command The cache line command of type lmem_cache_line_command_t + */ +static inline void LMEM_HAL_SetSystemCacheLineCommand(LMEM_Type * base, + lmem_cache_line_command_t command) +{ + LMEM_BWR_PSCLCR_LCMD(base, command); +} + +/*! + * @brief Sets the physical address for cache line commands for the Processor + * System bus. + * + * This function sets the physical address for cache line commands for the Processor + * System bus. The commands are specified in the CLCR[LADSEL] bits. + * + * @param base Module base pointer of type LMEM_Type. + * @param addr The physical address for cache line commands + */ +static inline void LMEM_HAL_SetSystemCachePhysicalAddr(LMEM_Type * base, uint32_t addr) +{ + LMEM_WR_PSCSAR(base, (addr & LMEM_PSCSAR_PHYADDR_MASK)); +} + +/*! + * @brief Sets the cache mode for a specific region for the Processor + * System bus. + * + * This function sets the cache mode for a specific region for the Processor + * System bus. Note that you can only demote the cache mode. + * + * @param base Module base pointer of type LMEM_Type. + * @param region The region to demote the cache mode of type lmem_cache_region_t + * @param cacheMode The specified demoted cache mode of type lmem_cache_mode_t + */ +void LMEM_HAL_SetSystemCacheRegionMode(LMEM_Type * base, lmem_cache_region_t region, + lmem_cache_mode_t cacheMode); + +/*! + * @brief Gets the current cache mode for a specific region for the Processor + * System bus. + * + * This function gets the current cache mode for a specific region for the Processor + * System bus. + * + * @param base Module base pointer of type LMEM_Type. + * @param region The region to obtain the cache mode of type lmem_cache_region_t + * @return The current cache mode for the specified region + */ +uint32_t LMEM_HAL_GetSystemCacheRegionMode(LMEM_Type * base, lmem_cache_region_t region); + +/*@}*/ +#endif /* #if FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_FEATURE_SOC_LMEM_COUNT */ +#endif /* __FSL_LMEM_CACHE_HAL_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_lpsci_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_lpsci_hal.h new file mode 100755 index 0000000..cce2938 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_lpsci_hal.h @@ -0,0 +1,1051 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_LPSCI_HAL_H__ +#define __FSL_LPSCI_HAL_H__ + +#include <assert.h> +#include <stdint.h> +#include <stdbool.h> +#include "fsl_device_registers.h" + +/*! + * @addtogroup lpsci_hal + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define LPSCI_SHIFT (8U) + +/*! @brief Error codes for the LPSCI driver. */ +typedef enum _lpsci_status +{ + kStatus_LPSCI_Success = 0x00U, + kStatus_LPSCI_Fail = 0x01U, + kStatus_LPSCI_BaudRateCalculationError = 0x02U, + kStatus_LPSCI_RxStandbyModeError = 0x03U, + kStatus_LPSCI_ClearStatusFlagError = 0x04U, + kStatus_LPSCI_TxNotDisabled = 0x05U, + kStatus_LPSCI_RxNotDisabled = 0x06U, + kStatus_LPSCI_TxOrRxNotDisabled = 0x07U, + kStatus_LPSCI_TxBusy = 0x08U, + kStatus_LPSCI_RxBusy = 0x09U, + kStatus_LPSCI_NoTransmitInProgress = 0x0AU, + kStatus_LPSCI_NoReceiveInProgress = 0x0BU, + kStatus_LPSCI_Timeout = 0x0CU, + kStatus_LPSCI_Initialized = 0x0DU, + kStatus_LPSCI_NoDataToDeal = 0x0EU, + kStatus_LPSCI_RxOverRun = 0x0FU +} lpsci_status_t; + +/*! + * @brief LPSCI number of stop bits. + * + * These constants define the number of allowable stop bits to configure in a LPSCI base. + */ +typedef enum _lpsci_stop_bit_count { + kLpsciOneStopBit = 0U, /*!< one stop bit */ + kLpsciTwoStopBit = 1U, /*!< two stop bits */ +} lpsci_stop_bit_count_t; + +/*! + * @brief LPSCI parity mode. + * + * These constants define the LPSCI parity mode options: disabled or enabled of type even or odd. + */ +typedef enum _lpsci_parity_mode { + kLpsciParityDisabled = 0x0U, /*!< parity disabled */ + kLpsciParityEven = 0x2U, /*!< parity enabled, type even, bit setting: PE|PT = 10 */ + kLpsciParityOdd = 0x3U, /*!< parity enabled, type odd, bit setting: PE|PT = 11 */ +} lpsci_parity_mode_t; + +/*! + * @brief LPSCI number of bits in a character. + * + * These constants define the number of allowable data bits per LPSCI character. Note, check the + * LPSCI documentation to determine if the desired LPSCI base supports the desired number + * of data bits per LPSCI character. + */ +typedef enum _lpsci_bit_count_per_char { + kLpsci8BitsPerChar = 0U, /*!< 8-bit data characters */ + kLpsci9BitsPerChar = 1U, /*!< 9-bit data characters */ +} lpsci_bit_count_per_char_t; + +/*! + * @brief LPSCI operation configuration constants. + * + * This provides constants for LPSCI operational states: "operates normally" + * or "stops/ceases operation" + */ +typedef enum _lpsci_operation_config { + kLpsciOperates = 0U, /*!< LPSCI continues to operate normally */ + kLpsciStops = 1U, /*!< LPSCI ceases operation */ +} lpsci_operation_config_t; + +/*! @brief LPSCI receiver source select mode. */ +typedef enum _lpsci_receiver_source { + kLpsciLoopBack = 0U, /*!< Internal loop back mode. */ + kLpsciSingleWire = 1U,/*!< Single wire mode. */ +} lpsci_receiver_source_t ; + +/*! + * @brief LPSCI wakeup from standby method constants. + * + * This provides constants for the two LPSCI wakeup methods: idle-line or address-mark. + */ +typedef enum _lpsci_wakeup_method { + kLpsciIdleLineWake = 0U, /*!< The idle-line wakes LPSCI receiver from standby */ + kLpsciAddrMarkWake = 1U, /*!< The address-mark wakes LPSCI receiver from standby */ +} lpsci_wakeup_method_t; + +/*! + * @brief LPSCI idle-line detect selection types. + * + * This provides constants for the LPSCI idle character bit-count start: either after start or + * stop bit. + */ +typedef enum _lpsci_idle_line_select { + kLpsciIdleLineAfterStartBit = 0U, /*!< LPSCI idle character bit count start after start bit */ + kLpsciIdleLineAfterStopBit = 1U, /*!< LPSCI idle character bit count start after stop bit */ +} lpsci_idle_line_select_t; + +/*! + * @brief LPSCI break character length settings for transmit/detect. + * + * This provides constants for the LPSCI break character length for both transmission and detection + * purposes. Note that the actual maximum bit times may vary depending on the LPSCI base. + */ +typedef enum _lpsci_break_char_length { + kLpsciBreakChar10BitMinimum = 0U, /*!< LPSCI break char length 10 bit times (if M = 0, SBNS = 0) or + 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, + SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1) */ + kLpsciBreakChar13BitMinimum = 1U, /*!< LPSCI break char length 13 bit times (if M = 0, SBNS = 0) or + 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, + SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1) */ +} lpsci_break_char_length_t; + +/*! + * @brief LPSCI single-wire mode transmit direction. + * + * This provides constants for the LPSCI transmit direction when configured for single-wire mode. + * The transmit line TXDIR is either an input or output. + */ +typedef enum _lpsci_singlewire_txdir { + kLpsciSinglewireTxdirIn = 0U, /*!< LPSCI Single-Wire mode TXDIR input */ + kLpsciSinglewireTxdirOut = 1U, /*!< LPSCI Single-Wire mode TXDIR output */ +} lpsci_singlewire_txdir_t; + +/*! + * @brief LPSCI infrared transmitter pulse width options. + * + * This provides constants for the LPSCI infrared (IR) pulse widths. Options include 3/16, 1/16 + * 1/32, and 1/4 pulse widths. + */ +typedef enum _lpsci_ir_tx_pulsewidth { + kLpsciIrThreeSixteenthsWidth = 0U, /*!< 3/16 pulse */ + kLpsciIrOneSixteenthWidth = 1U, /*!< 1/16 pulse */ + kLpsciIrOneThirtysecondsWidth = 2U, /*!< 1/32 pulse */ + kLpsciIrOneFourthWidth = 3U, /*!< 1/4 pulse */ +} lpsci_ir_tx_pulsewidth_t; + +/*! + * @brief LPSCI status flags. + * + * This provides constants for the LPSCI status flags for use in the LPSCI functions. + */ +typedef enum _lpsci_status_flag { + kLpsciTxDataRegEmpty = 0U << LPSCI_SHIFT | UART0_S1_TDRE_SHIFT, /*!< Tx data register empty flag, sets when Tx buffer is empty */ + kLpsciTxComplete = 0U << LPSCI_SHIFT | UART0_S1_TC_SHIFT, /*!< Transmission complete flag, sets when transmission activity complete */ + kLpsciRxDataRegFull = 0U << LPSCI_SHIFT | UART0_S1_RDRF_SHIFT, /*!< Rx data register full flag, sets when the receive data buffer is full */ + kLpsciIdleLineDetect = 0U << LPSCI_SHIFT | UART0_S1_IDLE_SHIFT, /*!< Idle line detect flag, sets when idle line detected */ + kLpsciRxOverrun = 0U << LPSCI_SHIFT | UART0_S1_OR_SHIFT, /*!< Rxr Overrun, sets when new data is received before data is read from receive register */ + kLpsciNoiseDetect = 0U << LPSCI_SHIFT | UART0_S1_NF_SHIFT, /*!< Rxr takes 3 samples of each received bit. If any of these samples differ, noise flag sets */ + kLpsciFrameErr = 0U << LPSCI_SHIFT | UART0_S1_FE_SHIFT, /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */ + kLpsciParityErr = 0U << LPSCI_SHIFT | UART0_S1_PF_SHIFT, /*!< If parity enabled, sets upon parity error detection */ + kLpsciLineBreakDetect = 1U << LPSCI_SHIFT | UART0_S2_LBKDIF_SHIFT, /*!< LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled */ + kLpsciRxActiveEdgeDetect = 1U << LPSCI_SHIFT | UART0_S2_RXEDGIF_SHIFT, /*!< Rx pin active edge interrupt flag, sets when active edge detected */ + kLpsciRxActive = 1U << LPSCI_SHIFT | UART0_S2_RAF_SHIFT, /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */ +#if FSL_FEATURE_LPSCI_HAS_EXTENDED_DATA_REGISTER_FLAGS + kLpsciNoiseInCurrentWord = 2U << LPSCI_SHIFT | UART0_ED_NOISY_SHIFT, /*!< NOISY bit, sets if noise detected in current data word */ + kLpsciParityErrInCurrentWord = 2U << LPSCI_SHIFT | UART0_ED_PARITYE_SHIFT, /*!< PARITYE bit, sets if noise detected in current data word */ +#endif +} lpsci_status_flag_t; + +/*! + * @brief LPSCI interrupt configuration structure, default settings are 0 (disabled). + * + * This structure contains the settings for all of the LPSCI interrupt configurations. + */ +typedef enum _lpsci_interrupt { + kLpsciIntLinBreakDetect = 0U << LPSCI_SHIFT | UART0_BDH_LBKDIE_SHIFT, /*!< LIN break detect. */ + kLpsciIntRxActiveEdge = 0U << LPSCI_SHIFT | UART0_BDH_RXEDGIE_SHIFT, /*!< RX Active Edge. */ + kLpsciIntTxDataRegEmpty = 1U << LPSCI_SHIFT | UART0_C2_TIE_SHIFT, /*!< Transmit data register empty. */ + kLpsciIntTxComplete = 1U << LPSCI_SHIFT | UART0_C2_TCIE_SHIFT, /*!< Transmission complete. */ + kLpsciIntRxDataRegFull = 1U << LPSCI_SHIFT | UART0_C2_RIE_SHIFT, /*!< Receiver data register full. */ + kLpsciIntIdleLine = 1U << LPSCI_SHIFT | UART0_C2_ILIE_SHIFT, /*!< Idle line. */ + kLpsciIntRxOverrun = 2U << LPSCI_SHIFT | UART0_C3_ORIE_SHIFT, /*!< Receiver Overrun. */ + kLpsciIntNoiseErrFlag = 2U << LPSCI_SHIFT | UART0_C3_NEIE_SHIFT, /*!< Noise error flag. */ + kLpsciIntFrameErrFlag = 2U << LPSCI_SHIFT | UART0_C3_FEIE_SHIFT, /*!< Framing error flag. */ + kLpsciIntParityErrFlag = 2U << LPSCI_SHIFT | UART0_C3_PEIE_SHIFT, /*!< Parity error flag. */ +} lpsci_interrupt_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name LPSCI Common Configurations + * @{ + */ + +/*! + * @brief Initializes the LPSCI controller. + * + * This function initializes the module to a known state. + * + * @param base LPSCI module base pointer. + */ +void LPSCI_HAL_Init(UART0_Type * base); + +/*! + * @brief Enables the LPSCI transmitter. + * + * This function allows the user to enable the LPSCI transmitter. + * + * @param base LPSCI module base pointer. + */ +static inline void LPSCI_HAL_EnableTransmitter(UART0_Type * base) +{ + UART0_BWR_C2_TE(base, 1U); +} + +/*! + * @brief Disables the LPSCI transmitter. + * + * This function allows the user to disable the LPSCI transmitter. + * + * @param base LPSCI module base pointer. + */ +static inline void LPSCI_HAL_DisableTransmitter(UART0_Type * base) +{ + UART0_BWR_C2_TE(base, 0U); +} + +/*! + * @brief Gets the LPSCI transmitter enabled/disabled configuration setting. + * + * This function allows the user to get the setting of the LPSCI transmitter. + * + * @param base LPSCI module base pointer. + * @return The state of LPSCI transmitter enable(true)/disable(false) setting. + */ +static inline bool LPSCI_HAL_IsTransmitterEnabled(UART0_Type * base) +{ + return (bool)UART0_BRD_C2_TE(base); +} + +/*! + * @brief Enables the LPSCI receiver. + * + * This function allows the user to enable the LPSCI receiver. + * + * @param base LPSCI module base pointer. + */ +static inline void LPSCI_HAL_EnableReceiver(UART0_Type * base) +{ + UART0_BWR_C2_RE(base, 1U); +} + +/*! + * @brief Disables the LPSCI receiver. + * + * This function allows the user to disable the LPSCI receiver. + * + * @param base LPSCI module base pointer. + */ +static inline void LPSCI_HAL_DisableReceiver(UART0_Type * base) +{ + UART0_BWR_C2_RE(base, 0U); +} + +/*! + * @brief Gets the LPSCI receiver enabled/disabled configuration setting. + * + * This function allows the user to get the setting of the LPSCI receiver. + * + * @param base LPSCI module base pointer. + * @return The state of LPSCI receiver enable(true)/disable(false) setting. + */ +static inline bool LPSCI_HAL_IsReceiverEnabled(UART0_Type * base) +{ + return (bool)UART0_BRD_C2_RE(base); +} + +/*! + * @brief Configures the LPSCI baud rate. + * + * This function programs the LPSCI baud rate to the desired value passed in by the user. The user + * must also pass in the module source clock so that the function can calculate the baud + * rate divisors to their appropriate values. + * In some LPSCI bases it is required that the transmitter/receiver be disabled + * before calling this function. + * Generally this is applied to all LPSCIs to ensure safe operation. + * + * @param base LPSCI module base pointer. + * @param sourceClockInHz LPSCI source input clock in Hz. + * @param baudRate LPSCI desired baud rate. + * @return An error code or kStatus_LPSCI_Success + */ +lpsci_status_t LPSCI_HAL_SetBaudRate(UART0_Type * base, uint32_t sourceClockInHz, uint32_t baudRate); + +/*! + * @brief Sets the LPSCI baud rate modulo divisor value. + * + * This function allows the user to program the baud rate divisor directly in situations + * where the divisor value is known. In this case, the user may not want to call the + * LPSCI_HAL_SetBaudRate() function, as the divisor is already known. + * + * @param base LPSCI module base pointer. + * @param baudRateDivisor The baud rate modulo division "SBR" value. + */ +void LPSCI_HAL_SetBaudRateDivisor(UART0_Type * base, uint16_t baudRateDivisor); + +#if FSL_FEATURE_LPSCI_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT +/*! + * @brief Sets the LPSCI baud rate fine adjust. (Note: Feature available on select + * LPSCI bases used in conjunction with baud rate programming) + * + * This function, which programs the baud rate fine adjust, is used together with + * programming the baud rate modulo divisor in situations where these divisors value are known. + * In this case, the user may not want to call the LPSCI_HAL_SetBaudRate() function, as the + * divisors are already known. + * + * @param base LPSCI module base pointer. + * @param baudFineAdjust Value of 5-bit field used to add more timing resolution to average + * baud rate frequency is 1/32 increments. + */ +static inline void LPSCI_HAL_SetBaudRateFineAdjust(UART0_Type * base, uint8_t baudFineAdjust) +{ + assert(baudFineAdjust < 0x1F); + UART0_BWR_C4_BRFA(base, baudFineAdjust); +} +#endif + +/*! + * @brief Configures the number of bits per character in the LPSCI controller. + * + * This function allows the user to configure the number of bits per character according to the + * typedef lpsci_bit_count_per_char_t. + * + * @param base LPSCI module base pointer. + * @param bitCountPerChar Number of bits per char (8, 9, or 10, depending on the LPSCI base). + */ +static inline void LPSCI_HAL_SetBitCountPerChar(UART0_Type * base, + lpsci_bit_count_per_char_t bitCountPerChar) +{ + /* config 8- (M=0) or 9-bits (M=1) */ + UART0_BWR_C1_M(base, bitCountPerChar); +} + +/*! + * @brief Configures the parity mode in LPSCI controller. + * + * This function allows the user to configure the parity mode of the LPSCI controller to disable + * it or enable it for even parity or for odd parity. + * + * @param base LPSCI module base pointer. + * @param parityMode Parity mode setting (enabled, disable, odd, even - see + * parity_mode_t struct). + */ +void LPSCI_HAL_SetParityMode(UART0_Type * base, lpsci_parity_mode_t parityMode); + +#if FSL_FEATURE_LPSCI_HAS_STOP_BIT_CONFIG_SUPPORT +/*! + * @brief Configures the number of stop bits in the LPSCI controller. + * + * This function allows the user to configure the number of stop bits in the LPSCI controller + * to be one or two stop bits. + * + * @param base LPSCI module base pointer. + * @param stopBitCount Number of stop bits setting (1 or 2 - see lpsci_stop_bit_count_t struct). + * @return An error code (an unsupported setting in some LPSCIs) or kStatus_LPSCI_Success. + */ +static inline void LPSCI_HAL_SetStopBitCount(UART0_Type * base, lpsci_stop_bit_count_t stopBitCount) +{ + UART0_BWR_BDH_SBNS(base, stopBitCount); +} +#endif + +/*@}*/ + +/*! + * @name LPSCI Interrupts and DMA + * @{ + */ + +/*! + * @brief Configures the LPSCI module interrupts to enable/disable various interrupt sources. + * + * @param base LPSCI module base pointer. + * @param interrupt LPSCI interrupt configuration data. + * @param enable true: enable, false: disable. + */ +void LPSCI_HAL_SetIntMode(UART0_Type * base, lpsci_interrupt_t interrupt, bool enable); + +/*! + * @brief Returns whether the LPSCI module interrupts is enabled/disabled. + * + * @param base LPSCI module base pointer. + * @param interrupt LPSCI interrupt configuration data. + * @return true: enable, false: disable. + */ +bool LPSCI_HAL_GetIntMode(UART0_Type * base, lpsci_interrupt_t interrupt); + +#if FSL_FEATURE_LPSCI_HAS_DMA_ENABLE +/*! + * @brief Enable or disable LPSCI DMA request for Transmitter. + * + * This function allows the user to configure the receive data register full + * flag to generate a DMA request. + * + * @param base LPSCI module base pointer. + * @param enable Transmit DMA request configuration setting (enable: true /disable: false). + */ +void LPSCI_HAL_SetTxDmaCmd(UART0_Type * base, bool enable); + +/*! + * @brief Enable or disable LPSCI DMA request for Receiver. + * + * This function allows the user to configure the receive data register full + * flag to generate a DMA request. + * + * @param base LPSCI module base pointer. + * @param enable Receive DMA request configuration setting (enable: true/disable: false). + */ +void LPSCI_HAL_SetRxDmaCmd(UART0_Type * base, bool enable); + +/*! + * @brief Gets the LPSCI Transmit DMA request configuration setting. + * + * This function returns the configuration setting of the Transmit DMA request. + * + * @param base LPSCI module base pointer. + * @return Transmit DMA request configuration setting (enable: true /disable: false). + */ +static inline bool LPSCI_HAL_GetTxDmaCmd(UART0_Type * base) +{ + return UART0_BRD_C5_TDMAE(base); +} + +/*! + * @brief Gets the LPSCI Receive DMA request configuration setting. + * + * This function returns the configuration setting of the Receive DMA request. + * + * @param base LPSCI module base pointer. + * @return Receive DMA request configuration setting (enable: true /disable: false). + */ +static inline bool LPSCI_HAL_GetRxDmaCmd(UART0_Type * base) +{ + return UART0_BRD_C5_RDMAE(base); +} +#endif /* FSL_FEATURE_LPSCI_HAS_DMA_ENABLE */ + +/*! + * @brief Get LPSCI tx/rx data register address. + * + * This function is used for DMA transfer. + * + * @param base LPSCI module base address. + * @return LPSCI tx/rx data register address. + */ +static inline uint32_t LPSCI_HAL_GetDataRegAddr(UART0_Type * base) +{ + return (uint32_t)(&UART0_D_REG(base)); +} + +/*@}*/ + +/*! + * @name LPSCI Transfer Functions + * @{ + */ + +/*! + * @brief This function allows the user to send an 8-bit character from the LPSCI data register. + * + * @param base LPSCI module base pointer. + * @param data The data to send of size 8-bit. + */ +static inline void LPSCI_HAL_Putchar(UART0_Type * base, uint8_t data) +{ + UART0_WR_D(base, data); +} + +/*! + * @brief This function allows the user to send a 9-bit character from the LPSCI data register. + * + * @param base LPSCI module base pointer. + * @param data The data to send of size 9-bit. + */ +void LPSCI_HAL_Putchar9(UART0_Type * base, uint16_t data); + +/*! + * @brief This function allows the user to send a 10-bit character from the LPSCI data register. + * + * @param base LPSCI module base pointer. + * @param data The data to send of size 10-bit. + */ +void LPSCI_HAL_Putchar10(UART0_Type * base, uint16_t data); + +/*! + * @brief This function gets a received 8-bit character from the LPSCI data register. + * + * @param base LPSCI module base pointer. + * @param readData The received data read from data register of size 8-bit. + */ +static inline void LPSCI_HAL_Getchar(UART0_Type * base, uint8_t *readData) +{ + *readData = UART0_RD_D(base); +} + +/*! + * @brief This function gets a received 9-bit character from the LPSCI data register. + * + * @param base LPSCI module base pointer. + * @param readData The received data read from data register of size 9-bit. + */ +void LPSCI_HAL_Getchar9(UART0_Type * base, uint16_t *readData); + +/*! + * @brief This function gets a received 10-bit character from the LPSCI data register. + * + * @param base LPSCI module base pointer. + * @param readData The received data read from data register of size 10-bit. + */ +void LPSCI_HAL_Getchar10(UART0_Type * base, uint16_t *readData); + +/*! + * @brief Send out multiple bytes of data using polling method. + * + * This function only supports 8-bit transaction. + * + * @param base LPSCI module base pointer. + * @param txBuff The buffer pointer which saves the data to be sent. + * @param txSize Size of data to be sent in unit of byte. + */ +void LPSCI_HAL_SendDataPolling(UART0_Type * base, const uint8_t *txBuff, uint32_t txSize); + +/*! + * @brief Receive multiple bytes of data using polling method. + * + * This function only supports 8-bit transaction. + * + * @param base LPSCI module base pointer. + * @param rxBuff The buffer pointer which saves the data to be received. + * @param rxSize Size of data need to be received in unit of byte. + * @return Whether the transaction is success or rx overrun. + */ +lpsci_status_t LPSCI_HAL_ReceiveDataPolling(UART0_Type * base, uint8_t *rxBuff, uint32_t rxSize); + +#if FSL_FEATURE_LPSCI_HAS_EXTENDED_DATA_REGISTER_FLAGS +/*! + * @brief Configures the LPSCI bit 10 (if enabled) or bit 9 (if disabled) as the parity bit in the + * serial transmission. + * + * This function configures bit 10 or bit 9 to be the parity bit. To configure bit 10 as the parity + * bit, the function sets LPSCIx_C4[M10]; it also sets LPSCIx_C1[M] and LPSCIx_C1[PE] as required. + * + * @param base LPSCI module base pointer. + * @param enable The setting to enable (true), which configures bit 10 as the parity bit or to + * disable (false), which configures bit 9 as the parity bit in the serial transmission. + */ +static inline void LPSCI_HAL_SetBit10AsParitybit(UART0_Type * base, bool enable) +{ + /* to enable the parity bit as the tenth data bit, along with enabling LPSCIx_C4[M10] + * need to also enable parity and set LPSCIx_C1[M] bit + * assumed that the user has already set the appropriate bits */ + UART0_BWR_C4_M10(base, enable); +} + +/*! + * @brief Gets the configuration of the LPSCI bit 10 (if enabled) or bit 9 (if disabled) as the + * parity bit in the serial transmission. + * + * This function returns true if bit 10 is configured as the parity bit, otherwise it returns + * false if bit 9 is configured as the parity bit. + * + * @param base LPSCI module base pointer. + * @return The configuration setting of bit 10 (true), or bit 9 (false) as the parity bit in + * the serial transmission. + */ +static inline bool LPSCI_HAL_IsBit10SetAsParitybit(UART0_Type * base) +{ + /* to see if the parity bit is set as the tenth data bit, + * return value of LPSCIx_C4[M10] */ + return UART0_BRD_C4_M10(base); +} + +/*! + * @brief Determines whether the LPSCI received data word was received with noise. + * + * This function returns true if the received data word was received with noise. Otherwise, + * it returns false indicating no noise was detected. + * + * @param base LPSCI module base pointer. + * @return The status of the NOISY bit in the LPSCI extended data register. + */ +static inline bool LPSCI_HAL_IsCurrentDataWithNoise(UART0_Type * base) +{ + return UART0_BRD_ED_NOISY(base); +} + +/*! + * @brief Determines whether the LPSCI received data word was received with a parity error. + * + * This function returns true if the received data word was received with a parity error. + * Otherwise, it returns false indicating no parity error was detected. + * + * @param base LPSCI module base pointer. + * @return The status of the PARITYE (parity error) bit in the LPSCI extended data register. + */ +static inline bool LPSCI_HAL_IsCurrentDataWithParityError(UART0_Type * base) +{ + return UART0_BRD_ED_PARITYE(base); +} + +#endif /* FSL_FEATURE_LPSCI_HAS_EXTENDED_DATA_REGISTER_FLAGS*/ + +/*@}*/ + +/*! + * @name LPSCI Status Flags + * @{ + */ + +/*! + * @brief Gets all LPSCI status flag states. + * + * @param base LPSCI module base pointer. + * @param statusFlag Status flag name. + */ +bool LPSCI_HAL_GetStatusFlag(UART0_Type * base, lpsci_status_flag_t statusFlag); + +/*! + * @brief Clears an individual and specific LPSCI status flag. + * + * This function allows the user to clear an individual and specific LPSCI status flag. Refer to + * structure definition lpsci_status_flag_t for list of status bits. + * + * @param base LPSCI module base pointer. + * @param statusFlag The desired LPSCI status flag to clear. + * @return An error code or kStatus_LPSCI_Success. + */ +lpsci_status_t LPSCI_HAL_ClearStatusFlag(UART0_Type * base, lpsci_status_flag_t statusFlag); + +/*@}*/ + +/*! + * @name LPSCI Special Feature Configurations + * @{ + */ + +/*! + * @brief Configures the LPSCI to either operate or cease to operate in WAIT mode. + * + * The function configures the LPSCI to either operate or cease to operate when WAIT mode is + * entered. + * + * @param base LPSCI module base pointer. + * @param mode The LPSCI WAIT mode operation - operates or ceases to operate in WAIT mode. + */ +static inline void LPSCI_HAL_SetWaitModeOperation(UART0_Type * base, lpsci_operation_config_t mode) +{ + /*In CPU wait mode: 0 - lpsci is enabled; 1 - lpsci is disabled */ + UART0_BWR_C1_DOZEEN(base, mode); +} + +/*! + * @brief Determines if the LPSCI operates or ceases to operate in WAIT mode. + * + * This function returns kLpsciOperates if the LPSCI has been configured to operate in WAIT mode. + * Else it returns KLpsciStops if the LPSCI has been configured to cease-to-operate in WAIT mode. + * + * @param base LPSCI module base pointer. + * @return The LPSCI WAIT mode operation configuration, returns either kLpsciOperates or KLpsciStops. + */ +static inline lpsci_operation_config_t LPSCI_HAL_GetWaitModeOperation(UART0_Type * base) +{ + /*In CPU wait mode: 0 - lpsci is enabled; 1 - lpsci is disabled */ + return (lpsci_operation_config_t)UART0_BRD_C1_DOZEEN(base); +} + +/*! + * @brief Configures the LPSCI loopback operation. + * + * This function enables or disables the LPSCI loopback operation. + * + * @param base LPSCI module base pointer. + * @param enable The LPSCI loopback mode configuration, either disabled (false) or enabled (true). + */ +static inline void LPSCI_HAL_SetLoopCmd(UART0_Type * base, bool enable) +{ + UART0_BWR_C1_LOOPS(base, enable); +} + +/*! + * @brief Configures the LPSCI single-wire operation. + * + * This function enables or disables the LPSCI single-wire operation. + * In some LPSCI bases it is required that the transmitter/receiver be disabled + * before calling this function. + * This may be applied to all LPSCIs to ensure safe operation. + * + * @param base LPSCI module base pointer. + * @param source The LPSCI single-wire mode configuration, either disabled (false) or enabled (true). + */ +static inline void LPSCI_HAL_SetReceiverSource(UART0_Type * base, lpsci_receiver_source_t source) +{ + UART0_BWR_C1_RSRC(base, source); +} +/*! + * @brief Configures the LPSCI transmit direction while in single-wire mode. + * + * This function configures the transmitter direction when the LPSCI is configured for single-wire + * operation. + * + * @param base LPSCI module base pointer. + * @param direction The LPSCI single-wire mode transmit direction configuration of type + * lpsci_singlewire_txdir_t (either kLpsciSinglewireTxdirIn or + * kLpsciSinglewireTxdirOut. + */ +static inline void LPSCI_HAL_SetTransmitterDir(UART0_Type * base, lpsci_singlewire_txdir_t direction) +{ + /* configure LPSCI transmit direction (input or output) when in single-wire mode + * it is assumed LPSCI is in single-wire mode */ + UART0_BWR_C3_TXDIR(base, direction); +} + +/*! + * @brief Places the LPSCI receiver in standby mode. + * + * This function, when called, places the LPSCI receiver into standby mode. + * In some LPSCI bases, there are conditions that must be met before placing Rx in standby mode. + * Before placing LPSCI in standby, determine if receiver is set to + * wake on idle, and if receiver is already in idle state. + * NOTE: RWU should only be set with C1[WAKE] = 0 (wakeup on idle) if the channel is currently + * not idle. + * This can be determined by the S2[RAF] flag. If set to wake up FROM an IDLE event and the channel + * is already idle, it is possible that the LPSCI will discard data because data must be received + * (or a LIN break detect) after an IDLE is detected before IDLE is allowed to be reasserted. + * + * @param base LPSCI module base pointer. + * @return Error code or kStatus_LPSCI_Success. + */ +lpsci_status_t LPSCI_HAL_PutReceiverInStandbyMode(UART0_Type * base); + +/*! + * @brief Places the LPSCI receiver in normal mode (disable standby mode operation). + * + * This function, when called, places the LPSCI receiver into normal mode and out of + * standby mode. + * + * @param base LPSCI module base pointer. + */ +static inline void LPSCI_HAL_PutReceiverInNormalMode(UART0_Type * base) +{ + UART0_CLR_C2(base, UART0_C2_RWU_MASK); +} + +/*! + * @brief Determines if the LPSCI receiver is currently in standby mode. + * + * This function determines the state of the LPSCI receiver. If it returns true, this means + * that the LPSCI receiver is in standby mode; if it returns false, the LPSCI receiver + * is in normal mode. + * + * @param base LPSCI module base pointer. + * @return The LPSCI receiver is in normal mode (false) or standby mode (true). + */ +static inline bool LPSCI_HAL_IsReceiverInStandby(UART0_Type * base) +{ + return UART0_BRD_C2_RWU(base); +} + +/*! + * @brief Selects the LPSCI receiver wakeup method (idle-line or address-mark) from standby mode. + * + * This function configures the wakeup method of the LPSCI receiver from standby mode. The options + * are idle-line wake or address-mark wake. + * + * @param base LPSCI module base pointer. + * @param method The LPSCI receiver wakeup method options: kLpsciIdleLineWake - Idle-line wake or + * kLpsciAddrMarkWake - address-mark wake. + */ +static inline void LPSCI_HAL_SetReceiverWakeupMethod(UART0_Type * base, lpsci_wakeup_method_t method) +{ + UART0_BWR_C1_WAKE(base, method); +} + +/*! + * @brief Gets the LPSCI receiver wakeup method (idle-line or address-mark) from standby mode. + * + * This function returns how the LPSCI receiver is configured to wake from standby mode. The + * wake method options that can be returned are kLpsciIdleLineWake or kLpsciAddrMarkWake. + * + * @param base LPSCI module base pointer. + * @return The LPSCI receiver wakeup from standby method, false: kLpsciIdleLineWake (idle-line wake) + * or true: kLpsciAddrMarkWake (address-mark wake). + */ +static inline lpsci_wakeup_method_t LPSCI_HAL_GetReceiverWakeupMethod(UART0_Type * base) +{ + return (lpsci_wakeup_method_t)UART0_BRD_C1_WAKE(base); +} + +/*! + * @brief Configures the operation options of the LPSCI idle line detect. + * + * This function allows the user to configure the LPSCI idle-line detect operation. There are two + * separate operations for the user to configure, the idle line bit-count start and the receive + * wake up affect on IDLE status bit. The user will pass in a structure of type + * lpsci_idle_line_config_t. + * + * @param base LPSCI module base pointer. + * @param idleLine Idle bit count start: 0 - after start bit (default), 1 - after stop bit + * @param rxWakeIdleDetect Receiver Wake Up Idle Detect. IDLE status bit operation during receive + * standby. Controls whether idle character that wakes up receiver will also set IDLE status + * bit. 0 - IDLE status bit doesn't get set (default), 1 - IDLE status bit gets set + */ +void LPSCI_HAL_ConfigIdleLineDetect(UART0_Type * base, uint8_t idleLine, uint8_t rxWakeIdleDetect); + +/*! + * @brief Configures the LPSCI break character transmit length. + * + * This function allows the user to configure the LPSCI break character transmit length. Refer to + * the typedef lpsci_break_char_length_t for setting options. + * In some LPSCI bases it is required that the transmitter be disabled before calling + * this function. This may be applied to all LPSCIs to ensure safe operation. + * + * @param base LPSCI module base pointer. + * @param length The LPSCI break character length setting of type lpsci_break_char_length_t, either a + * minimum 10-bit times or a minimum 13-bit times. + */ +static inline void LPSCI_HAL_SetBreakCharTransmitLength(UART0_Type * base, + lpsci_break_char_length_t length) +{ + /* Configure BRK13 - Break Character transmit length configuration + * LPSCI break character length setting: + * 0 - minimum 10-bit times (default), + * 1 - minimum 13-bit times */ + UART0_BWR_S2_BRK13(base, length); +} + +/*! + * @brief Configures the LPSCI break character detect length. + * + * This function allows the user to configure the LPSCI break character detect length. Refer to + * the typedef lpsci_break_char_length_t for setting options. + * + * @param base LPSCI module base pointer. + * @param length The LPSCI break character length setting of type lpsci_break_char_length_t, either a + * minimum 10-bit times or a minimum 13-bit times. + */ +static inline void LPSCI_HAL_SetBreakCharDetectLength(UART0_Type * base, + lpsci_break_char_length_t length) +{ + /* Configure LBKDE - Break Character detect length configuration + * LPSCI break character length setting: + * 0 - minimum 10-bit times (default), + * 1 - minimum 13-bit times */ + UART0_BWR_S2_LBKDE(base, length); +} + +/*! + * @brief Configures the LPSCI transmit send break character operation. + * + * This function allows the user to queue a LPSCI break character to send. If true is passed into + * the function, then a break character is queued for transmission. A break character will + * continuously be queued until this function is called again when a false is passed into this + * function. + * + * @param base LPSCI module base pointer. + * @param enable If false, the LPSCI normal/queue break character setting is disabled, which + * configures the LPSCI for normal transmitter operation. If true, a break + * character is queued for transmission. + */ +static inline void LPSCI_HAL_SetBreakCharCmd(UART0_Type * base, bool enable) +{ + UART0_BWR_C2_SBK(base, enable); +} + +/*! + * @brief Configures the LPSCI match address mode control operation. (Note: Feature available on + * select LPSCI bases) + * + * The function allows the user to configure the LPSCI match address control operation. The user + * has the option to enable the match address mode and to program the match address value. There + * are two match address modes, each with its own enable and programmable match address value. + * + * @param base LPSCI module base pointer. + * @param matchAddrMode1 If true, this enables match address mode 1 (MAEN1), where false disables. + * @param matchAddrMode2 If true, this enables match address mode 2 (MAEN2), where false disables. + * @param matchAddrValue1 The match address value to program for match address mode 1. + * @param matchAddrValue2 The match address value to program for match address mode 2. + */ +void LPSCI_HAL_SetMatchAddress(UART0_Type * base, bool matchAddrMode1, bool matchAddrMode2, + uint8_t matchAddrValue1, uint8_t matchAddrValue2); + +#if FSL_FEATURE_LPSCI_HAS_BIT_ORDER_SELECT +/*! + * @brief Configures the LPSCI to send data MSB first + * (Note: Feature available on select LPSCI bases) + * + * The function allows the user to configure the LPSCI to send data MSB first or LSB first. + * In some LPSCI bases it is required that the transmitter/receiver be disabled + * before calling this function. + * This may be applied to all LPSCIs to ensure safe operation. + * + * @param base LPSCI module base pointer. + * @param enable This configures send MSB first mode configuration. If true, the data is sent MSB + * first; if false, it is sent LSB first. + */ +static inline void LPSCI_HAL_SetSendMsbFirstCmd(UART0_Type * base, bool enable) +{ + UART0_BWR_S2_MSBF(base, enable); +} +#endif + +#if FSL_FEATURE_LPSCI_HAS_MODEM_SUPPORT +/*! + * @brief Enables the LPSCI receiver request-to-send functionality. + * + * This function allows the user to enable the LPSCI receiver request-to-send (RTS) functionality. + * By enabling, it allows the RTS output to control the CTS input of the transmitting device to + * prevent receiver overrun. RTS is deasserted if the number of characters in the receiver data + * register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the + * number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. + * Do not set both RXRTSE and TXRTSE. + * + * @param base LPSCI module base pointer. + * @param enable Enable or disable receiver rts. + */ +static inline void LPSCI_HAL_SetReceiverRtsCmd(UART0_Type * base, bool enable) +{ + UART0_BWR_MODEM_RXRTSE(base, enable); +} + +/*! + * @brief Enables the LPSCI transmitter request-to-send functionality. + * + * This function allows the user to enable the LPSCI transmitter request-to-send (RTS) functionality. + * When enabled, it allows the LPSCI to control the RTS assertion before and after a transmission + * such that when a character is placed into an empty transmitter data buffer, RTS + * asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all + * characters in the transmitter data buffer and shift register are completely sent, including + * the last stop bit. + * + * @param base LPSCI module base pointer. + * @param enable Enable or disable transmitter RTS. + */ +static inline void LPSCI_HAL_SetTransmitterRtsCmd(UART0_Type * base, bool enable) +{ + UART0_BWR_MODEM_TXRTSE(base, enable); +} + +/*! + * @brief Configures the LPSCI transmitter RTS polarity. + * + * This function allows the user configure the transmitter RTS polarity to be either active low + * or active high. + * + * @param base LPSCI module base pointer. + * @param polarity The LPSCI transmitter RTS polarity setting (false - active low, + * true - active high). + */ +static inline void LPSCI_HAL_SetTransmitterRtsPolarityMode(UART0_Type * base, bool polarity) +{ + UART0_BWR_MODEM_TXRTSPOL(base, polarity); +} + +/*! + * @brief Enables the LPSCI transmitter clear-to-send functionality. + * + * This function allows the user to enable the LPSCI transmitter clear-to-send (CTS) functionality. + * When enabled, the transmitter checks the state of CTS each time it is ready to send a character. + * If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in + * the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a + * character is being sent do not affect its transmission. + * + * @param base LPSCI module base pointer. + * @param enable Enable or disable transmitter CTS. + */ +static inline void LPSCI_HAL_SetTransmitterCtsCmd(UART0_Type * base, bool enable) +{ + UART0_BWR_MODEM_TXCTSE(base, enable); +} + +#endif /* FSL_FEATURE_LPSCI_HAS_MODEM_SUPPORT*/ + +#if FSL_FEATURE_LPSCI_HAS_IR_SUPPORT +/*! + * @brief Configures the LPSCI infrared operation. + * + * The function allows the user to enable or disable the LPSCI infrared (IR) operation + * and to configure the IR pulse width. + * + * @param base LPSCI module base pointer. + * @param enable Enable (true) or disable (false) the infrared operation. + * @param pulseWidth The LPSCI transmit narrow pulse width setting of type lpsci_ir_tx_pulsewidth_t. + */ +void LPSCI_HAL_SetInfraredOperation(UART0_Type * base, + bool enable, + lpsci_ir_tx_pulsewidth_t pulseWidth); +#endif /* FSL_FEATURE_LPSCI_HAS_IR_SUPPORT*/ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __FSL_LPSCI_HAL_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_lptmr_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_lptmr_hal.h new file mode 100755 index 0000000..4bfe094 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_lptmr_hal.h @@ -0,0 +1,261 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_LPTMR_HAL_H__ +#define __FSL_LPTMR_HAL_H__ + +#include <assert.h> +#include <stdint.h> +#include <stdbool.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_LPTMR_COUNT + +/*! + * @addtogroup lptmr_hal + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @brief LPTMR pin selection, used in pulse counter mode.*/ +typedef enum _lptmr_pin_select { + kLptmrPinSelectInput0 = 0x0U, /*!< Pulse counter input 0 is selected. @internal gui name="Input0"*/ + kLptmrPinSelectInput1 = 0x1U, /*!< Pulse counter input 1 is selected. @internal gui name="Input1"*/ + kLptmrPinSelectInput2 = 0x2U, /*!< Pulse counter input 2 is selected. @internal gui name="Input2"*/ + kLptmrPinSelectInput3 = 0x3U /*!< Pulse counter input 3 is selected. @internal gui name="Input3"*/ +} lptmr_pin_select_t; + +/*! @brief LPTMR pin polarity, used in pulse counter mode.*/ +typedef enum _lptmr_pin_polarity { + kLptmrPinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high. @internal gui name="Active-high"*/ + kLptmrPinPolarityActiveLow = 0x1U /*!< Pulse Counter input source is active-low. @internal gui name="Active-low"*/ +} lptmr_pin_polarity_t; + +/*! @brief LPTMR timer mode selection.*/ +typedef enum _lptmr_timer_mode { + kLptmrTimerModeTimeCounter = 0x0U, /*!< Time Counter mode. @internal gui name="Time Counter mode"*/ + kLptmrTimerModePulseCounter = 0x1U /*!< Pulse Counter mode. @internal gui name="Pulse Counter mode"*/ +} lptmr_timer_mode_t; + +/*! @brief LPTMR prescaler value.*/ +typedef enum _lptmr_prescaler_value { + kLptmrPrescalerDivide2 = 0x0U, /*!< Prescaler divide 2, glitch filter invalid. @internal gui name="2/invalid"*/ + kLptmrPrescalerDivide4GlitchFilter2 = 0x1U, /*!< Prescaler divide 4, glitch filter 2. @internal gui name="4/2"*/ + kLptmrPrescalerDivide8GlitchFilter4 = 0x2U, /*!< Prescaler divide 8, glitch filter 4. @internal gui name="8/4"*/ + kLptmrPrescalerDivide16GlitchFilter8 = 0x3U, /*!< Prescaler divide 16, glitch filter 8. @internal gui name="16/8"*/ + kLptmrPrescalerDivide32GlitchFilter16 = 0x4U, /*!< Prescaler divide 32, glitch filter 16. @internal gui name="32/16"*/ + kLptmrPrescalerDivide64GlitchFilter32 = 0x5U, /*!< Prescaler divide 64, glitch filter 32. @internal gui name="64/32"*/ + kLptmrPrescalerDivide128GlitchFilter64 = 0x6U, /*!< Prescaler divide 128, glitch filter 64. @internal gui name="128/64"*/ + kLptmrPrescalerDivide256GlitchFilter128 = 0x7U, /*!< Prescaler divide 256, glitch filter 128. @internal gui name="256/128"*/ + kLptmrPrescalerDivide512GlitchFilter256 = 0x8U, /*!< Prescaler divide 512, glitch filter 256. @internal gui name="512/256"*/ + kLptmrPrescalerDivide1024GlitchFilter512 = 0x9U, /*!< Prescaler divide 1024, glitch filter 512. @internal gui name="1024/512"*/ + kLptmrPrescalerDivide2048GlitchFilter1024 = 0xAU, /*!< Prescaler divide 2048 glitch filter 1024. @internal gui name="2048/1024"*/ + kLptmrPrescalerDivide4096GlitchFilter2048 = 0xBU, /*!< Prescaler divide 4096, glitch filter 2048.@internal gui name="4096/2048"*/ + kLptmrPrescalerDivide8192GlitchFilter4096 = 0xCU, /*!< Prescaler divide 8192, glitch filter 4096. @internal gui name="8192/4096"*/ + kLptmrPrescalerDivide16384GlitchFilter8192 = 0xDU, /*!< Prescaler divide 16384, glitch filter 8192. @internal gui name="16384/8192"*/ + kLptmrPrescalerDivide32768GlitchFilter16384 = 0xEU, /*!< Prescaler divide 32768, glitch filter 16384. @internal gui name="32768/16384"*/ + kLptmrPrescalerDivide65536GlitchFilter32768 = 0xFU /*!< Prescaler divide 65536, glitch filter 32768. @internal gui name="65535/32768"*/ +} lptmr_prescaler_value_t; + +/*! @brief LPTMR prescaler/glitch filter clock select. */ +typedef enum _lptmr_prescaler_clock_select{ + kLptmrPrescalerClock0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */ + kLptmrPrescalerClock1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */ + kLptmrPrescalerClock2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */ + kLptmrPrescalerClock3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */ +} lptmr_prescaler_clock_select_t; + +/*! @brief LPTMR status return codes.*/ +typedef enum _lptmr_status { + kStatus_LPTMR_Success = 0x0U, /*!< Succeed. */ + kStatus_LPTMR_NotInitlialized = 0x1U, /*!< LPTMR is not initialized yet. */ + kStatus_LPTMR_NullArgument = 0x2U, /*!< Argument is NULL.*/ + kStatus_LPTMR_InvalidPrescalerValue = 0x3U, /*!< Value 0 is not valid in pulse counter mode. */ + kStatus_LPTMR_InvalidInTimeCounterMode = 0x4U, /*!< Function cannot be called in time counter mode. */ + kStatus_LPTMR_InvalidInPulseCounterMode = 0x5U, /*!< Function cannot be called in pulse counter mode. */ + kStatus_LPTMR_TcfNotSet = 0x6U, /*!< If LPTMR is enabled, compare register can only altered when TCF is set. */ + kStatus_LPTMR_TimerPeriodUsTooSmall = 0x7U, /*!< Timer period time is too small for current clock source. */ + kStatus_LPTMR_TimerPeriodUsTooLarge = 0x8U /*!< Timer period time is too large for current clock source. */ + } lptmr_status_t; + +/*! @brief Define LPTMR prescaler user configure. */ +typedef struct LptmrPrescalerUserConfig { + bool prescalerBypass; /*!< Set this value will by pass the Prescaler or glitch filter. */ + lptmr_prescaler_clock_select_t prescalerClockSelect; /*!< Selects the clock to be used by the LPTMR prescaler/glitch filter. */ + lptmr_prescaler_value_t prescalerValue; /*!< Configures the size of the Prescaler in Time Counter mode + or width of the glitch filter in Pulse Counter mode. */ +} lptmr_prescaler_user_config_t; + +/*! @brief Define LPTMR working mode user configure. */ +typedef struct LptmrWorkingModeUserConfig { + lptmr_timer_mode_t timerModeSelect; /*!< Selects the LPTMR working mode: Timer or Pulse Counter. */ + bool freeRunningEnable; /*!< Enables or disables the LPTMR free running. */ + lptmr_pin_polarity_t pinPolarity; /*!< Specifies LPTMR pulse input pin polarity. */ + lptmr_pin_select_t pinSelect; /*!< Specifies LPTMR pulse input pin select. */ +} lptmr_working_mode_user_config_t; + +/******************************************************************************* + ** Variables + *******************************************************************************/ + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name LPTMR HAL. + * @{ + */ + +/*! + * @brief Enables the LPTMR module operation. + * + * @param base The LPTMR peripheral base address. + */ +static inline void LPTMR_HAL_Enable(LPTMR_Type * base) +{ + LPTMR_BWR_CSR_TEN(base, (uint8_t)true); +} + +/*! + * @brief Disables the LPTMR module operation. + * + * @param base The LPTMR peripheral base address. + */ +static inline void LPTMR_HAL_Disable(LPTMR_Type * base) +{ + LPTMR_BWR_CSR_TEN(base, (uint8_t)false); +} + +/*! + * @brief Clears the LPTMR interrupt flag if set. + * + * @param base The LPTMR peripheral base address. + */ +static inline void LPTMR_HAL_ClearIntFlag(LPTMR_Type * base) +{ + LPTMR_BWR_CSR_TCF(base, 1); +} + +/*! + * @brief Returns the current LPTMR interrupt flag. + * + * @param base The LPTMR peripheral base address + * @return State of LPTMR interrupt flag + * @retval true An interrupt is pending. + * @retval false No interrupt is pending. + */ +static inline bool LPTMR_HAL_IsIntPending(LPTMR_Type * base) +{ + return ((bool)LPTMR_BRD_CSR_TCF(base)); +} + +/*! + * @brief Enables or disables the LPTMR interrupt. + * + * @param baseAddr The LPTMR peripheral base address + * @param enable Pass true to enable LPTMR interrupt + */ +static inline void LPTMR_HAL_SetIntCmd(LPTMR_Type * baseAddr, bool enable) +{ + LPTMR_BWR_CSR_TIE(baseAddr, enable); +} + +/*! + * @brief Configures the LPTMR working mode. + * + * @param base The LPTMR peripheral base address. + * @param timerMode Specifies LPTMR working mode configure, see #lptmr_working_mode_user_config_t + */ +void LPTMR_HAL_SetTimerWorkingMode(LPTMR_Type * base, lptmr_working_mode_user_config_t timerMode); + +/*! + * @brief Sets the LPTMR prescaler mode. + * + * @param base The LPTMR peripheral base address. + * @param prescaler_config Specifies LPTMR prescaler configure, see #lptmr_prescaler_user_config_t + */ +void LPTMR_HAL_SetPrescalerMode(LPTMR_Type * base, lptmr_prescaler_user_config_t prescaler_config); + +/*! + * @brief Sets the LPTMR compare value. + * + * @param base The LPTMR peripheral base address. + * @param compareValue Specifies LPTMR compare value, less than 0xFFFFU + */ +static inline void LPTMR_HAL_SetCompareValue(LPTMR_Type * base, uint32_t compareValue) +{ + LPTMR_BWR_CMR_COMPARE(base, compareValue); +} + +/*! + * @brief Gets the LPTMR compare value. + * + * @param base The LPTMR peripheral base address. + */ +static inline uint32_t LPTMR_HAL_GetCompareValue(LPTMR_Type * base) +{ + return LPTMR_BRD_CMR_COMPARE(base); +} + +/*! + * @brief Gets the LPTMR counter value. + * + * @param base The LPTMR peripheral base address. + * @return Current LPTMR counter value + */ +uint32_t LPTMR_HAL_GetCounterValue(LPTMR_Type * base); + +/*! + * @brief Restores the LPTMR module to reset state. + * + * @param base The LPTMR peripheral base address + */ +void LPTMR_HAL_Init(LPTMR_Type * base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif +#endif /* __FSL_LPTMR_HAL_H__*/ +/******************************************************************************* + * EOF + *******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_lpuart_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_lpuart_hal.h new file mode 100755 index 0000000..c581109 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_lpuart_hal.h @@ -0,0 +1,1031 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_LPUART_HAL_H__ +#define __FSL_LPUART_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> +#include <assert.h> +#include "fsl_device_registers.h" + +/*! + * @addtogroup lpuart_hal + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define LPUART_SHIFT (16U) +#define LPUART_BAUD_REG_ID (0U) +#define LPUART_STAT_REG_ID (1U) +#define LPUART_CTRL_REG_ID (2U) +#define LPUART_DATA_REG_ID (3U) +#define LPUART_MATCH_REG_ID (4U) +#define LPUART_MODIR_REG_ID (5U) + +/*! @brief Error codes for the LPUART driver.*/ +typedef enum _lpuart_status +{ + kStatus_LPUART_Success = 0x00U, + kStatus_LPUART_Fail = 0x01U, + kStatus_LPUART_BaudRateCalculationError = 0x02U, + kStatus_LPUART_RxStandbyModeError = 0x03U, + kStatus_LPUART_ClearStatusFlagError = 0x04U, + kStatus_LPUART_TxNotDisabled = 0x05U, + kStatus_LPUART_RxNotDisabled = 0x06U, + kStatus_LPUART_TxBusy = 0x07U, + kStatus_LPUART_RxBusy = 0x08U, + kStatus_LPUART_NoTransmitInProgress = 0x09U, + kStatus_LPUART_NoReceiveInProgress = 0x0AU, + kStatus_LPUART_Timeout = 0x0BU, + kStatus_LPUART_Initialized = 0x0CU, + kStatus_LPUART_NoDataToDeal = 0x0DU, + kStatus_LPUART_RxOverRun = 0x0EU +} lpuart_status_t; + +/*! @brief LPUART number of stop bits*/ +typedef enum _lpuart_stop_bit_count { + kLpuartOneStopBit = 0x0U, /*!< one stop bit @internal gui name="1" */ + kLpuartTwoStopBit = 0x1U, /*!< two stop bits @internal gui name="2" */ +} lpuart_stop_bit_count_t; + +/*! @brief LPUART parity mode*/ +typedef enum _lpuart_parity_mode { + kLpuartParityDisabled = 0x0U, /*!< parity disabled @internal gui name="Disabled" */ + kLpuartParityEven = 0x2U, /*!< parity enabled, type even, bit setting: PE|PT = 10 @internal gui name="Even" */ + kLpuartParityOdd = 0x3U, /*!< parity enabled, type odd, bit setting: PE|PT = 11 @internal gui name="Odd" */ +} lpuart_parity_mode_t; + +/*! @brief LPUART number of bits in a character*/ +typedef enum _lpuart_bit_count_per_char { + kLpuart8BitsPerChar = 0x0U, /*!< 8-bit data characters @internal gui name="8" */ + kLpuart9BitsPerChar = 0x1U, /*!< 9-bit data characters @internal gui name="9" */ + kLpuart10BitsPerChar = 0x2U, /*!< 10-bit data characters @internal gui name="10" */ +} lpuart_bit_count_per_char_t; + +/*! @brief LPUART operation configuration constants*/ +typedef enum _lpuart_operation_config { + kLpuartOperates = 0x0U, /*!< LPUART continues to operate normally.*/ + kLpuartStops = 0x1U, /*!< LPUART stops operation. */ +} lpuart_operation_config_t; + +/*! @brief LPUART wakeup from standby method constants*/ +typedef enum _lpuart_wakeup_method { + kLpuartIdleLineWake = 0x0U, /*!< Idle-line wakes the LPUART receiver from standby. */ + kLpuartAddrMarkWake = 0x1U, /*!< Addr-mark wakes LPUART receiver from standby.*/ +} lpuart_wakeup_method_t; + +/*! @brief LPUART idle line detect selection types*/ +typedef enum _lpuart_idle_line_select { + kLpuartIdleLineAfterStartBit = 0x0U, /*!< LPUART idle character bit count start after start bit */ + kLpuartIdleLineAfterStopBit = 0x1U, /*!< LPUART idle character bit count start after stop bit */ +} lpuart_idle_line_select_t; + +/*! + * @brief LPUART break character length settings for transmit/detect. + * + * The actual maximum bit times may vary depending on the LPUART instance. + */ +typedef enum _lpuart_break_char_length { + kLpuartBreakChar10BitMinimum = 0x0U, /*!< LPUART break char length 10 bit times (if M = 0, SBNS = 0) + or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, + SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1) */ + kLpuartBreakChar13BitMinimum = 0x1U, /*!< LPUART break char length 13 bit times (if M = 0, SBNS = 0 + or M10 = 0, SBNS = 1) or 14 (if M = 1, SBNS = 0 or M = 1, + SBNS = 1) or 15 (if M10 = 1, SBNS = 1 or M10 = 1, SNBS = 0) */ +} lpuart_break_char_length_t; + +/*! @brief LPUART single-wire mode TX direction*/ +typedef enum _lpuart_singlewire_txdir { + kLpuartSinglewireTxdirIn = 0x0U, /*!< LPUART Single Wire mode TXDIR input*/ + kLpuartSinglewireTxdirOut = 0x1U, /*!< LPUART Single Wire mode TXDIR output*/ +} lpuart_singlewire_txdir_t; + +/*! @brief LPUART Configures the match addressing mode used.*/ +typedef enum _lpuart_match_config { + kLpuartAddressMatchWakeup = 0x0U, /*!< Address Match Wakeup*/ + kLpuartIdleMatchWakeup = 0x1U, /*!< Idle Match Wakeup*/ + kLpuartMatchOnAndMatchOff = 0x2U, /*!< Match On and Match Off*/ + kLpuartEnablesRwuOnDataMatch = 0x3U, /*!< Enables RWU on Data Match and Match On/Off for transmitter CTS input*/ +} lpuart_match_config_t; + +/*! @brief LPUART infra-red transmitter pulse width options*/ +typedef enum _lpuart_ir_tx_pulsewidth { + kLpuartIrThreeSixteenthsWidth = 0x0U, /*!< 3/16 pulse*/ + kLpuartIrOneSixteenthWidth = 0x1U, /*!< 1/16 pulse*/ + kLpuartIrOneThirtysecondsWidth = 0x2U, /*!< 1/32 pulse*/ + kLpuartIrOneFourthWidth = 0x3U, /*!< 1/4 pulse*/ +} lpuart_ir_tx_pulsewidth_t; + +/*! + * @brief LPUART Configures the number of idle characters that must be received + * before the IDLE flag is set. + */ +typedef enum _lpuart_idle_char { + kLpuart_1_IdleChar = 0x0U, /*!< 1 idle character*/ + kLpuart_2_IdleChar = 0x1U, /*!< 2 idle character*/ + kLpuart_4_IdleChar = 0x2U, /*!< 4 idle character*/ + kLpuart_8_IdleChar = 0x3U, /*!< 8 idle character*/ + kLpuart_16_IdleChar = 0x4U, /*!< 16 idle character*/ + kLpuart_32_IdleChar = 0x5U, /*!< 32 idle character*/ + kLpuart_64_IdleChar = 0x6U, /*!< 64 idle character*/ + kLpuart_128_IdleChar = 0x7U, /*!< 128 idle character*/ +} lpuart_idle_char_t; + +/*! @brief LPUART Transmits the CTS Configuration. Configures the source of the CTS input.*/ +typedef enum _lpuart_cts_source { + kLpuartCtsSourcePin = 0x0U, /*!< CTS input is the LPUART_CTS pin.*/ + kLpuartCtsSourceInvertedReceiverMatch = 0x1U, /*!< CTS input is the inverted Receiver Match result.*/ +} lpuart_cts_source_t; + +/*! + * @brief LPUART Transmits CTS Source.Configures if the CTS state is checked at + * the start of each character or only when the transmitter is idle. + */ +typedef enum _lpuart_cts_config { + kLpuartCtsSampledOnEachChar = 0x0U, /*!< CTS input is sampled at the start of each character.*/ + kLpuartCtsSampledOnIdle = 0x1U, /*!< CTS input is sampled when the transmitter is idle.*/ +} lpuart_cts_config_t; + +/*! @brief Structure for idle line configuration settings*/ +typedef struct LpuartIdleLineConfig { + unsigned idleLineType : 1; /*!< ILT, Idle bit count start: 0 - after start bit (default), + 1 - after stop bit */ + unsigned rxWakeIdleDetect : 1; /*!< RWUID, Receiver Wake Up Idle Detect. IDLE status bit + operation during receive standbyControls whether idle + character that wakes up receiver will also set + IDLE status bit 0 - IDLE status bit doesn't + get set (default), 1 - IDLE status bit gets set*/ +} lpuart_idle_line_config_t; + +/*! + * @brief LPUART status flags. + * + * This provides constants for the LPUART status flags for use in the UART functions. + */ +typedef enum _lpuart_status_flag { + kLpuartTxDataRegEmpty = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_TDRE_SHIFT, /*!< Tx data register empty flag, sets when Tx buffer is empty */ + kLpuartTxComplete = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_TC_SHIFT, /*!< Transmission complete flag, sets when transmission activity complete */ + kLpuartRxDataRegFull = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_RDRF_SHIFT, /*!< Rx data register full flag, sets when the receive data buffer is full */ + kLpuartIdleLineDetect = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_IDLE_SHIFT, /*!< Idle line detect flag, sets when idle line detected */ + kLpuartRxOverrun = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_OR_SHIFT, /*!< Rx Overrun, sets when new data is received before data is read from receive register */ + kLpuartNoiseDetect = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_NF_SHIFT, /*!< Rx takes 3 samples of each received bit. If any of these samples differ, noise flag sets */ + kLpuartFrameErr = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_FE_SHIFT, /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */ + kLpuartParityErr = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_PF_SHIFT, /*!< If parity enabled, sets upon parity error detection */ + kLpuartLineBreakDetect = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_LBKDE_SHIFT, /*!< LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled */ + kLpuartRxActiveEdgeDetect = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_RXEDGIF_SHIFT, /*!< Rx pin active edge interrupt flag, sets when active edge detected */ + kLpuartRxActive = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_RAF_SHIFT, /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */ + kLpuartNoiseInCurrentWord = LPUART_DATA_REG_ID << LPUART_SHIFT | LPUART_DATA_NOISY_SHIFT, /*!< NOISY bit, sets if noise detected in current data word */ + kLpuartParityErrInCurrentWord = LPUART_DATA_REG_ID << LPUART_SHIFT | LPUART_DATA_PARITYE_SHIFT, /*!< PARITYE bit, sets if noise detected in current data word */ +#if FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + kLpuartMatchAddrOne = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_MA1F_SHIFT, /*!< Address one match flag */ + kLpuartMatchAddrTwo = LPUART_STAT_REG_ID << LPUART_SHIFT | LPUART_STAT_MA2F_SHIFT, /*!< Address two match flag */ +#endif +} lpuart_status_flag_t; + +/*! @brief LPUART interrupt configuration structure, default settings are 0 (disabled)*/ +typedef enum _lpuart_interrupt { + kLpuartIntLinBreakDetect = LPUART_BAUD_REG_ID << LPUART_SHIFT | LPUART_BAUD_LBKDIE_SHIFT, /*!< LIN break detect. */ + kLpuartIntRxActiveEdge = LPUART_BAUD_REG_ID << LPUART_SHIFT | LPUART_BAUD_RXEDGIE_SHIFT, /*!< RX Active Edge. */ + kLpuartIntTxDataRegEmpty = LPUART_CTRL_REG_ID << LPUART_SHIFT | LPUART_CTRL_TIE_SHIFT, /*!< Transmit data register empty. */ + kLpuartIntTxComplete = LPUART_CTRL_REG_ID << LPUART_SHIFT | LPUART_CTRL_TCIE_SHIFT, /*!< Transmission complete. */ + kLpuartIntRxDataRegFull = LPUART_CTRL_REG_ID << LPUART_SHIFT | LPUART_CTRL_RIE_SHIFT, /*!< Receiver data register full. */ + kLpuartIntIdleLine = LPUART_CTRL_REG_ID << LPUART_SHIFT | LPUART_CTRL_ILIE_SHIFT, /*!< Idle line. */ + kLpuartIntRxOverrun = LPUART_CTRL_REG_ID << LPUART_SHIFT | LPUART_CTRL_ORIE_SHIFT, /*!< Receiver Overrun. */ + kLpuartIntNoiseErrFlag = LPUART_CTRL_REG_ID << LPUART_SHIFT | LPUART_CTRL_NEIE_SHIFT, /*!< Noise error flag. */ + kLpuartIntFrameErrFlag = LPUART_CTRL_REG_ID << LPUART_SHIFT | LPUART_CTRL_FEIE_SHIFT, /*!< Framing error flag. */ + kLpuartIntParityErrFlag = LPUART_CTRL_REG_ID << LPUART_SHIFT | LPUART_CTRL_PEIE_SHIFT, /*!< Parity error flag. */ +#if FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING + kLpuartIntMatchAddrOne = LPUART_CTRL_REG_ID << LPUART_SHIFT | LPUART_CTRL_MA1IE_SHIFT, /*!< Match address one flag. */ + kLpuartIntMatchAddrTwo = LPUART_CTRL_REG_ID << LPUART_SHIFT | LPUART_CTRL_MA2IE_SHIFT, /*!< Match address two flag. */ +#endif +} lpuart_interrupt_t; + + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name LPUART Common Configurations + * @{ + */ + +/*! + * @brief Initializes the LPUART controller to known state. + * + * @param base LPUART base pointer. + */ +void LPUART_HAL_Init(LPUART_Type * base); + +/*! + * @brief Enable/Disable the LPUART transmitter. + * + * @param base LPUART base pointer. + * @param enable Enable(true) or disable(false) transmitter. + */ +static inline void LPUART_HAL_SetTransmitterCmd(LPUART_Type * base, bool enable) +{ + LPUART_BWR_CTRL_TE(base, enable); +} + +/*! + * @brief Gets the LPUART transmitter enabled/disabled configuration. + * + * @param base LPUART base pointer + * @return State of LPUART transmitter enable(true)/disable(false) + */ +static inline bool LPUART_HAL_GetTransmitterCmd(LPUART_Type * base) +{ + return LPUART_BRD_CTRL_TE(base); +} + +/*! + * @brief Enable/Disable the LPUART receiver. + * + * @param base LPUART base pointer + * @param enable Enable(true) or disable(false) receiver. + */ +static inline void LPUART_HAL_SetReceiverCmd(LPUART_Type * base, bool enable) +{ + LPUART_BWR_CTRL_RE(base, enable); +} + +/*! + * @brief Gets the LPUART receiver enabled/disabled configuration. + * + * @param base LPUART base pointer + * @return State of LPUART receiver enable(true)/disable(false) + */ +static inline bool LPUART_HAL_GetReceiverCmd(LPUART_Type * base) +{ + return LPUART_BRD_CTRL_RE(base); +} + +/*! + * @brief Configures the LPUART baud rate. + * + * In some LPUART instances the user must disable the transmitter/receiver + * before calling this function. + * Generally, this may be applied to all LPUARTs to ensure safe operation. + * + * @param base LPUART base pointer. + * @param sourceClockInHz LPUART source input clock in Hz. + * @param desiredBaudRate LPUART desired baud rate. + * @return An error code or kStatus_Success + */ +lpuart_status_t LPUART_HAL_SetBaudRate(LPUART_Type * base, + uint32_t sourceClockInHz, + uint32_t desiredBaudRate); + +/*! + * @brief Sets the LPUART baud rate modulo divisor. + * + * @param base LPUART base pointer. + * @param baudRateDivisor The baud rate modulo division "SBR" + */ +static inline void LPUART_HAL_SetBaudRateDivisor(LPUART_Type * base, uint32_t baudRateDivisor) +{ + assert ((baudRateDivisor < 0x1FFF) && (baudRateDivisor > 1)); + LPUART_BWR_BAUD_SBR(base, baudRateDivisor); +} + +#if FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT +/*! + * @brief Sets the LPUART baud rate oversampling ratio (Note: Feature available on select + * LPUART instances used together with baud rate programming) + * The oversampling ratio should be set between 4x (00011) and 32x (11111). Writing + * an invalid oversampling ratio results in an error and is set to a default + * 16x (01111) oversampling ratio. + * IDisable the transmitter/receiver before calling + * this function. + * + * @param base LPUART base pointer. + * @param overSamplingRatio The oversampling ratio "OSR" + */ +static inline void LPUART_HAL_SetOversamplingRatio(LPUART_Type * base, uint32_t overSamplingRatio) +{ + assert(overSamplingRatio < 0x1F); + LPUART_BWR_BAUD_OSR(base, overSamplingRatio); +} +#endif + +#if FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT +/*! + * @brief Configures the LPUART baud rate both edge sampling (Note: Feature available on select + * LPUART instances used with baud rate programming) + * When enabled, the received data is sampled on both edges of the baud rate clock. + * This must be set when the oversampling ratio is between 4x and 7x. + * This function should only be called when the receiver is disabled. + * + * @param base LPUART base pointer. + * @param enable Enable (1) or Disable (0) Both Edge Sampling + * @return An error code or kStatus_Success + */ +static inline void LPUART_HAL_SetBothEdgeSamplingCmd(LPUART_Type * base, bool enable) +{ + LPUART_BWR_BAUD_BOTHEDGE(base, enable); +} +#endif + +/*! + * @brief Configures the number of bits per character in the LPUART controller. + * + * In some LPUART instances, the user should disable the transmitter/receiver + * before calling this function. + * Generally, this may be applied to all LPUARTs to ensure safe operation. + * + * @param base LPUART base pointer. + * @param bitCountPerChar Number of bits per char (8, 9, or 10, depending on the LPUART instance) + */ +void LPUART_HAL_SetBitCountPerChar(LPUART_Type * base, lpuart_bit_count_per_char_t bitCountPerChar); + +/*! + * @brief Configures parity mode in the LPUART controller. + * + * In some LPUART instances, the user should disable the transmitter/receiver + * before calling this function. + * Generally, this may be applied to all LPUARTs to ensure safe operation. + * + * @param base LPUART base pointer. + * @param parityModeType Parity mode (enabled, disable, odd, even - see parity_mode_t struct) + */ +void LPUART_HAL_SetParityMode(LPUART_Type * base, lpuart_parity_mode_t parityModeType); + +/*! + * @brief Configures the number of stop bits in the LPUART controller. + * In some LPUART instances, the user should disable the transmitter/receiver + * before calling this function. + * Generally, this may be applied to all LPUARTs to ensure safe operation. + * + * @param base LPUART base pointer. + * @param stopBitCount Number of stop bits (1 or 2 - see lpuart_stop_bit_count_t struct) + * @return An error code (an unsupported setting in some LPUARTs) or kStatus_Success + */ +static inline void LPUART_HAL_SetStopBitCount(LPUART_Type * base, lpuart_stop_bit_count_t stopBitCount) +{ + LPUART_BWR_BAUD_SBNS(base, stopBitCount); +} + +/*! + * @brief Get LPUART tx/rx data register address. + * + * @return LPUART tx/rx data register address. + */ +static inline uint32_t LPUART_HAL_GetDataRegAddr(LPUART_Type * base) +{ + return (uint32_t)(&LPUART_DATA_REG(base)); +} + +/*@}*/ + +/*! + * @name LPUART Interrupts and DMA + * @{ + */ + +/*! + * @brief Configures the LPUART module interrupts to enable/disable various interrupt sources. + * + * @param base LPUART module base pointer. + * @param interrupt LPUART interrupt configuration data. + * @param enable true: enable, false: disable. + */ +void LPUART_HAL_SetIntMode(LPUART_Type * base, lpuart_interrupt_t interrupt, bool enable); + +/*! + * @brief Returns whether the LPUART module interrupts is enabled/disabled. + * + * @param base LPUART module base pointer. + * @param interrupt LPUART interrupt configuration data. + * @return true: enable, false: disable. + */ +bool LPUART_HAL_GetIntMode(LPUART_Type * base, lpuart_interrupt_t interrupt); + +#if FSL_FEATURE_LPUART_HAS_DMA_ENABLE +/*! + * @brief LPUART configures DMA requests for Transmitter and Receiver. + * + * @param base LPUART base pointer + * @param enable Transmit DMA request configuration (enable:1 /disable: 0) + */ +static inline void LPUART_HAL_SetTxDmaCmd(LPUART_Type * base, bool enable) +{ + LPUART_BWR_BAUD_TDMAE(base, enable); +} + +/*! + * @brief LPUART configures DMA requests for Transmitter and Receiver. + * + * @param base LPUART base pointer + * @param enable Receive DMA request configuration (enable: 1/disable: 0) + */ +static inline void LPUART_HAL_SetRxDmaCmd(LPUART_Type * base, bool enable) +{ + LPUART_BWR_BAUD_RDMAE(base, enable); +} + +/*! + * @brief Gets the LPUART Transmit DMA request configuration. + * + * @param base LPUART base pointer + * @return Transmit DMA request configuration (enable: 1/disable: 0) + */ +static inline bool LPUART_HAL_IsTxDmaEnabled(LPUART_Type * base) +{ + return LPUART_BRD_BAUD_TDMAE(base); +} + +/*! + * @brief Gets the LPUART receive DMA request configuration. + * + * @param base LPUART base pointer + * @return Receives the DMA request configuration (enable: 1/disable: 0). + */ +static inline bool LPUART_HAL_IsRxDmaEnabled(LPUART_Type * base) +{ + return LPUART_BRD_BAUD_RDMAE(base); +} + +#endif + +/*@}*/ + +/*! + * @name LPUART Transfer Functions + * @{ + */ + +/*! + * @brief Sends the LPUART 8-bit character. + * + * @param base LPUART Instance + * @param data data to send (8-bit) + */ +static inline void LPUART_HAL_Putchar(LPUART_Type * base, uint8_t data) +{ + LPUART_WR_DATA(base, data); +} + +/*! + * @brief Sends the LPUART 9-bit character. + * + * @param base LPUART Instance + * @param data data to send (9-bit) + */ +void LPUART_HAL_Putchar9(LPUART_Type * base, uint16_t data); + +/*! + * @brief Sends the LPUART 10-bit character (Note: Feature available on select LPUART instances). + * + * @param base LPUART Instance + * @param data data to send (10-bit) + * @return An error code or kStatus_Success + */ +lpuart_status_t LPUART_HAL_Putchar10(LPUART_Type * base, uint16_t data); + +/*! + * @brief Gets the LPUART 8-bit character. + * + * @param base LPUART base pointer + * @param readData Data read from receive (8-bit) + */ +static inline void LPUART_HAL_Getchar(LPUART_Type * base, uint8_t *readData) +{ + *readData = (uint8_t)LPUART_RD_DATA(base); +} + +/*! + * @brief Gets the LPUART 9-bit character. + * + * @param base LPUART base pointer + * @param readData Data read from receive (9-bit) + */ +void LPUART_HAL_Getchar9(LPUART_Type * base, uint16_t *readData); + +/*! + * @brief Gets the LPUART 10-bit character. + * + * @param base LPUART base pointer + * @param readData Data read from receive (10-bit) + */ +void LPUART_HAL_Getchar10(LPUART_Type * base, uint16_t *readData); + +/*! + * @brief Send out multiple bytes of data using polling method. + * + * This function only supports 8-bit transaction. + * + * @param base LPUART module base pointer. + * @param txBuff The buffer pointer which saves the data to be sent. + * @param txSize Size of data to be sent in unit of byte. + */ +void LPUART_HAL_SendDataPolling(LPUART_Type * base, const uint8_t *txBuff, uint32_t txSize); + +/*! + * @brief Receive multiple bytes of data using polling method. + * + * This function only supports 8-bit transaction. + * + * @param base LPUART module base pointer. + * @param rxBuff The buffer pointer which saves the data to be received. + * @param rxSize Size of data need to be received in unit of byte. + * @return Whether the transaction is success or rx overrun. + */ +lpuart_status_t LPUART_HAL_ReceiveDataPolling(LPUART_Type * base, uint8_t *rxBuff, uint32_t rxSize); + +/*@}*/ + +/*! + * @name LPUART Status Flags + * @{ + */ + +/*! + * @brief LPUART get status flag + * + * @param base LPUART base pointer + * @param statusFlag The status flag to query + * @return Whether the current status flag is set(true) or not(false). + */ +bool LPUART_HAL_GetStatusFlag(LPUART_Type * base, lpuart_status_flag_t statusFlag); + +/*! + * @brief LPUART clears an individual status flag (see lpuart_status_flag_t for list of status bits). + * + * @param base LPUART base pointer + * @param statusFlag Desired LPUART status flag to clear + * @return An error code or kStatus_Success + */ +lpuart_status_t LPUART_HAL_ClearStatusFlag(LPUART_Type * base, lpuart_status_flag_t statusFlag); + +/*@}*/ + +/*! + * @name LPUART Special Feature Configurations + * @{ + */ + +/*! + * @brief Configures the number of idle characters that must be received before the IDLE flag is set. + * + * @param base LPUART base pointer + * @param idleConfig Idle characters configuration + */ +static inline void LPUART_HAL_SetIdleChar(LPUART_Type * base, lpuart_idle_char_t idleConfig) +{ + LPUART_BWR_CTRL_IDLECFG(base, idleConfig); +} + +/*! + * @brief Gets the configuration of the number of idle characters that must be received + * before the IDLE flag is set. + * + * @param base LPUART base pointer + * @return idle characters configuration + */ +static inline lpuart_idle_char_t LPUART_HAL_GetIdleChar(LPUART_Type * base) +{ + return (lpuart_idle_char_t)LPUART_BRD_CTRL_IDLECFG(base); +} + +/*! + * @brief Checks whether the current data word was received with noise. + * + * @param base LPUART base pointer. + * @return The status of the NOISY bit in the LPUART extended data register + */ +static inline bool LPUART_HAL_IsCurrentDataWithNoise(LPUART_Type * base) +{ + return LPUART_BRD_DATA_NOISY(base); +} + +/*! + * @brief Checks whether the current data word was received with frame error. + * + * @param base LPUART base pointer + * @return The status of the FRETSC bit in the LPUART extended data register + */ +static inline bool LPUART_HAL_IsCurrentDataWithFrameError(LPUART_Type * base) +{ + return LPUART_BRD_DATA_FRETSC(base); +} + +/*! + * @brief Set this bit to indicate a break or idle character is to be transmitted + * instead of the contents in DATA[T9:T0]. + * + * @param base LPUART base pointer + * @param specialChar T9 is used to indicate a break character when 0 an idle + * character when 1, the contents of DATA[T8:T0] should be zero. + */ +static inline void LPUART_HAL_SetTxSpecialChar(LPUART_Type * base, uint8_t specialChar) +{ + LPUART_BWR_DATA_FRETSC(base, specialChar); +} + +/*! + * @brief Checks whether the current data word was received with parity error. + * + * @param base LPUART base pointer + * @return The status of the PARITYE bit in the LPUART extended data register + */ +static inline bool LPUART_HAL_IsCurrentDataWithParityError(LPUART_Type * base) +{ + return LPUART_BRD_DATA_PARITYE(base); +} + +/*! + * @brief Checks whether the receive buffer is empty. + * + * @param base LPUART base pointer + * @return TRUE if the receive-buffer is empty, else FALSE. + */ +static inline bool LPUART_HAL_IsReceiveBufferEmpty(LPUART_Type * base) +{ + return LPUART_BRD_DATA_RXEMPT(base); +} + +/*! + * @brief Checks whether the previous BUS state was idle before this byte is received. + * + * @param base LPUART base pointer + * @return TRUE if the previous BUS state was IDLE, else FALSE. + */ +static inline bool LPUART_HAL_WasPreviousReceiverStateIdle(LPUART_Type * base) +{ + return LPUART_BRD_DATA_IDLINE(base); +} + +/*! + * @brief Configures the LPUART operation in wait mode (operates or stops operations in wait mode). + * + * In some LPUART instances, the user should disable the transmitter/receiver + * before calling this function. + * Generally, this may be applied to all LPUARTs to ensure safe operation. + * + * @param base LPUART base pointer + * @param mode LPUART wait mode operation - operates or stops to operate in wait mode. + */ +static inline void LPUART_HAL_SetWaitModeOperation(LPUART_Type * base, lpuart_operation_config_t mode) +{ + /* In CPU wait mode: 0 - lpuart clocks continue to run; 1 - lpuart clocks freeze */ + LPUART_BWR_CTRL_DOZEEN(base, mode); +} + +/*! + * @brief Gets the LPUART operation in wait mode (operates or stops operations in wait mode). + * + * @param base LPUART base pointer + * @return LPUART wait mode operation configuration + * - kLpuartOperates or KLpuartStops in wait mode + */ +static inline lpuart_operation_config_t LPUART_HAL_GetWaitModeOperation(LPUART_Type * base) +{ + /* In CPU wait mode: 0 - lpuart clocks continue to run; 1 - lpuart clocks freeze */ + return (lpuart_operation_config_t)LPUART_BRD_CTRL_DOZEEN(base); +} + +/*! + * @brief Configures the LPUART loopback operation (enable/disable loopback operation) + * + * In some LPUART instances, the user should disable the transmitter/receiver + * before calling this function. + * Generally, this may be applied to all LPUARTs to ensure safe operation. + * + * @param base LPUART base pointer + * @param enable LPUART loopback mode - disabled (0) or enabled (1) + */ +void LPUART_HAL_SetLoopbackCmd(LPUART_Type * base, bool enable); + +/*! + * @brief Configures the LPUART single-wire operation (enable/disable single-wire mode) + * + * In some LPUART instances, the user should disable the transmitter/receiver + * before calling this function. + * Generally, this may be applied to all LPUARTs to ensure safe operation. + * + * @param base LPUART base pointer + * @param enable LPUART loopback mode - disabled (0) or enabled (1) + */ +void LPUART_HAL_SetSingleWireCmd(LPUART_Type * base, bool enable); + +/*! + * @brief Configures the LPUART transmit direction while in single-wire mode. + * + * @param base LPUART base pointer + * @param direction LPUART single-wire transmit direction - input or output + */ +static inline void LPUART_HAL_SetTxdirInSinglewireMode(LPUART_Type * base, + lpuart_singlewire_txdir_t direction) +{ + LPUART_BWR_CTRL_TXDIR(base, direction); +} + +/*! + * @brief Places the LPUART receiver in standby mode. + * + * @param base LPUART base pointer + * @return Error code or kStatus_Success + */ +lpuart_status_t LPUART_HAL_SetReceiverInStandbyMode(LPUART_Type * base); + +/*! + * @brief Places the LPUART receiver in a normal mode (disable standby mode operation). + * + * @param base LPUART base pointer + */ +static inline void LPUART_HAL_PutReceiverInNormalMode(LPUART_Type * base) +{ + LPUART_BWR_CTRL_RWU(base, 0); +} + +/*! + * @brief Checks whether the LPUART receiver is in a standby mode. + * + * @param base LPUART base pointer + * @return LPUART in normal more (0) or standby (1) + */ +static inline bool LPUART_HAL_IsReceiverInStandby(LPUART_Type * base) +{ + return LPUART_BRD_CTRL_RWU(base); +} + +/*! + * @brief LPUART receiver wakeup method (idle line or addr-mark) from standby mode + * + * @param base LPUART base pointer + * @param method LPUART wakeup method: 0 - Idle-line wake (default), 1 - addr-mark wake + */ +static inline void LPUART_HAL_SetReceiverWakeupMode(LPUART_Type * base, + lpuart_wakeup_method_t method) +{ + LPUART_BWR_CTRL_WAKE(base, method); +} + +/*! + * @brief Gets the LPUART receiver wakeup method (idle line or addr-mark) from standby mode. + * + * @param base LPUART base pointer + * @return LPUART wakeup method: kLpuartIdleLineWake: 0 - Idle-line wake (default), + * kLpuartAddrMarkWake: 1 - addr-mark wake + */ +static inline lpuart_wakeup_method_t LPUART_HAL_GetReceiverWakeupMode(LPUART_Type * base) +{ + return (lpuart_wakeup_method_t)LPUART_BRD_CTRL_WAKE(base); +} + +/*! + * @brief LPUART idle-line detect operation configuration (idle line bit-count start and wake + * up affect on IDLE status bit). + * + * In some LPUART instances, the user should disable the transmitter/receiver + * before calling this function. + * Generally, this may be applied to all LPUARTs to ensure safe operation. + * + * @param base LPUART base pointer + * @param config LPUART configuration data for idle line detect operation + */ +void LPUART_HAL_SetIdleLineDetect(LPUART_Type * base, + const lpuart_idle_line_config_t *config); + +/*! + * @brief LPUART break character transmit length configuration + * + * In some LPUART instances, the user should disable the transmitter before calling + * this function. Generally, this may be applied to all LPUARTs to ensure safe operation. + * + * @param base LPUART base pointer + * @param length LPUART break character length setting: 0 - minimum 10-bit times (default), + * 1 - minimum 13-bit times + */ +static inline void LPUART_HAL_SetBreakCharTransmitLength(LPUART_Type * base, + lpuart_break_char_length_t length) +{ + LPUART_BWR_STAT_BRK13(base, length); +} + +/*! + * @brief LPUART break character detect length configuration + * + * @param base LPUART base pointer + * @param length LPUART break character length setting: 0 - minimum 10-bit times (default), + * 1 - minimum 13-bit times + */ +static inline void LPUART_HAL_SetBreakCharDetectLength(LPUART_Type * base, + lpuart_break_char_length_t length) +{ + LPUART_BWR_STAT_LBKDE(base, length); +} + +/*! + * @brief LPUART transmit sends break character configuration. + * + * @param base LPUART base pointer + * @param enable LPUART normal/queue break char - disabled (normal mode, default: 0) or + * enabled (queue break char: 1) + */ +static inline void LPUART_HAL_QueueBreakCharToSend(LPUART_Type * base, bool enable) +{ + LPUART_BWR_CTRL_SBK(base, enable); +} + +/*! + * @brief LPUART configures match address mode control + * + * @param base LPUART base pointer + * @param config MATCFG: Configures the match addressing mode used. + */ +static inline void LPUART_HAL_SetMatchAddressMode(LPUART_Type * base, lpuart_match_config_t config) +{ + LPUART_BWR_BAUD_MATCFG(base, config); +} + +/*! + * @brief Configures address match register 1 + * + * The MAEN bit must be cleared before configuring MA value, so the enable/disable + * and set value must be included inside one function. + * + * @param base LPUART base pointer + * @param enable Match address model enable (true)/disable (false) + * @param value Match address value to program into match address register 1 + */ +void LPUART_HAL_SetMatchAddressReg1(LPUART_Type * base, bool enable, uint8_t value); + +/*! + * @brief Configures address match register 2 + * + * The MAEN bit must be cleared before configuring MA value, so the enable/disable + * and set value must be included inside one function. + * + * @param base LPUART base pointer + * @param enable Match address model enable (true)/disable (false) + * @param value Match address value to program into match address register 2 + */ +void LPUART_HAL_SetMatchAddressReg2(LPUART_Type * base, bool enable, uint8_t value); + +/*! + * @brief LPUART sends the MSB first configuration + * + * In some LPUART instances, the user should disable the transmitter/receiver + * before calling this function. + * Generally, this may be applied to all LPUARTs to ensure safe operation. + * + * @param base LPUART base pointer + * @param enable false - LSB (default, disabled), true - MSB (enabled) + */ +static inline void LPUART_HAL_SetSendMsbFirstCmd(LPUART_Type * base, bool enable) +{ + LPUART_BWR_STAT_MSBF(base, enable); +} + +/*! + * @brief LPUART enable/disable re-sync of received data configuration + * + * @param base LPUART base pointer + * @param enable re-sync of received data word configuration: + * true - re-sync of received data word (default) + * false - disable the re-sync + */ +static inline void LPUART_HAL_SetReceiveResyncCmd(LPUART_Type * base, bool enable) +{ + /* When disabled, the resynchronization of the received data word when a data + * one followed by data zero transition is detected. This bit should only be + * changed when the receiver is disabled. */ + LPUART_BWR_BAUD_RESYNCDIS(base, enable); +} + +#if FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT +/*! + * @brief Transmits the CTS source configuration. + * + * @param base LPUART base pointer + * @param source LPUART CTS source + */ +static inline void LPUART_HAL_SetCtsSource(LPUART_Type * base, + lpuart_cts_source_t source) +{ + LPUART_BWR_MODIR_TXCTSSRC(base, source); +} + +/*! + * @brief Transmits the CTS configuration. + * + * Note: configures if the CTS state is checked at the start of each character + * or only when the transmitter is idle. + * + * @param base LPUART base pointer + * @param mode LPUART CTS configuration + */ +static inline void LPUART_HAL_SetCtsMode(LPUART_Type * base, lpuart_cts_config_t mode) +{ + LPUART_BWR_MODIR_TXCTSC(base, mode); +} + +/*! + * @brief Enable/Disable the transmitter clear-to-send. + * + * @param base LPUART base pointer + * @param enable disable(0)/enable(1) transmitter CTS. + */ +static inline void LPUART_HAL_SetTxCtsCmd(LPUART_Type * base, bool enable) +{ + LPUART_BWR_MODIR_TXCTSE(base, enable); +} + +/*! + * @brief Enable/Disable the receiver request-to-send. + * + * Note: do not enable both Receiver RTS (RXRTSE) and Transmit RTS (TXRTSE). + * + * @param base LPUART base pointer + * @param enable disable(0)/enable(1) receiver RTS. + */ +static inline void LPUART_HAL_SetRxRtsCmd(LPUART_Type * base, bool enable) +{ + LPUART_BWR_MODIR_RXRTSE(base, enable); +} + +/*! + * @brief Enable/Disable the transmitter request-to-send. + * Note: do not enable both Receiver RTS (RXRTSE) and Transmit RTS (TXRTSE). + * + * @param base LPUART base pointer + * @param enable disable(0)/enable(1) transmitter RTS. + */ +static inline void LPUART_HAL_SetTxRtsCmd(LPUART_Type * base, bool enable) +{ + LPUART_BWR_MODIR_TXRTSE(base, enable); +} + +/*! + * @brief Configures the transmitter RTS polarity. + * + * @param base LPUART base pointer + * @param polarity Settings to choose RTS polarity (0=active low, 1=active high) + */ +static inline void LPUART_HAL_SetTxRtsPolarityMode(LPUART_Type * base, bool polarity) +{ + LPUART_BWR_MODIR_TXRTSPOL(base, polarity); +} + +#endif /* FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT */ + +#if FSL_FEATURE_LPUART_HAS_IR_SUPPORT +/*! + * @brief Configures the LPUART infrared operation. + * + * @param base LPUART base pointer + * @param enable Enable (1) or disable (0) the infrared operation + * @param pulseWidth The transmit narrow pulse width of type lpuart_ir_tx_pulsewidth_t + */ +void LPUART_HAL_SetInfrared(LPUART_Type * base, bool enable, + lpuart_ir_tx_pulsewidth_t pulseWidth); +#endif /* FSL_FEATURE_LPUART_HAS_IR_SUPPORT */ + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __FSL_LPUART_HAL_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_mcg_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_mcg_hal.h new file mode 100755 index 0000000..3fb934c --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_mcg_hal.h @@ -0,0 +1,1429 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#if !defined(__FSL_MCG_HAL_H__) +#define __FSL_MCG_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> +#include <assert.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_MCG_COUNT + +/*! @addtogroup mcg_hal*/ +/*! @{*/ + +/*! @file fsl_mcg_hal.h */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief MCG constant definitions*/ +enum _mcg_constant +{ + kMcgConstant0 = (0u), + kMcgConstant31250 = (31250u), + kMcgConstant32768 = (32768u), + kMcgConstant39063 = (39063u), + kMcgConstant8000000 = (8000000u), + kMcgConstant16000000 = (16000000u), +}; + +/*! @brief MCG internal reference clock source select */ +typedef enum _mcg_fll_src +{ + kMcgFllSrcExternal, /*!< External reference clock is selected */ + kMcgFllSrcInternal /*!< The slow internal reference clock is selected */ +} mcg_fll_src_t; + +/*! @brief MCG OSC frequency range select */ +typedef enum _osc_range +{ + kOscRangeLow, /*!< Low frequency range selected for the crystal OSC */ + kOscRangeHigh, /*!< High frequency range selected for the crystal OSC */ + kOscRangeVeryHigh, /*!< Very High frequency range selected for the crystal OSC */ + kOscRangeVeryHigh1 /*!< Very High frequency range selected for the crystal OSC */ +} osc_range_t; + +/*! @brief MCG high gain oscillator select */ +typedef enum _osc_gain +{ + kOscGainLow, /*!< Configure crystal oscillator for low-power operation */ + kOscGainHigh /*!< Configure crystal oscillator for high-gain operation */ +} osc_gain_t; + +/*! @brief MCG external reference clock select */ +typedef enum _osc_src +{ + kOscSrcExt, /*!< External reference clock requested */ + kOscSrcOsc /*!< Oscillator requested */ +} osc_src_t; + +/*! @brief MCG internal reference clock select */ +typedef enum _mcg_irc_mode +{ + kMcgIrcSlow, /*!< Slow internal reference clock selected */ + kMcgIrcFast /*!< Fast internal reference clock selected */ +} mcg_irc_mode_t; + +/*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */ +typedef enum _mcg_dmx32_select +{ + kMcgDmx32Default, /*!< DCO has a default range of 25% */ + kMcgDmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */ +} mcg_dmx32_select_t; + +/*! @brief MCG DCO range select */ +typedef enum _mcg_dco_range_select +{ + kMcgDcoRangeSelLow, /*!< Low frequency range */ + kMcgDcoRangeSelMid, /*!< Mid frequency range*/ + kMcgDcoRangeSelMidHigh, /*!< Mid-High frequency range */ + kMcgDcoRangeSelHigh /*!< High frequency range */ +} mcg_dco_range_select_t; + +/*! @brief MCG PLL external reference clock select */ +typedef enum _mcg_pll_ref_mode +{ + kMcgPllRefOsc0, /*!< Selects OSC0 clock source as its external reference clock */ + kMcgPllRefOsc1 /*!< Selects OSC1 clock source as its external reference clock */ +} mcg_pll_ref_mode_t; + +/*! @brief MCGOUT clock source. */ +typedef enum _mcg_clkout_src +{ + kMcgClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */ + kMcgClkOutSrcInternal, /*!< Internal reference clock is selected */ + kMcgClkOutSrcExternal, /*!< External reference clock is selected */ +} mcg_clkout_src_t; + +/*! @brief MCG clock mode status */ +typedef enum _mcg_clkout_stat +{ + kMcgClkOutStatFll, /*!< Output of the FLL is selected (reset default) */ + kMcgClkOutStatInternal, /*!< Internal reference clock is selected */ + kMcgClkOutStatExternal, /*!< External reference clock is selected */ + kMcgClkOutStatPll /*!< Output of the PLL is selected */ +} mcg_clkout_stat_t; + +/*! @brief MCG Automatic Trim Machine Select */ +typedef enum _mcg_atm_select +{ + kMcgAtmSel32k, /*!< 32 kHz Internal Reference Clock selected */ + kMcgAtmSel4m /*!< 4 MHz Internal Reference Clock selected */ +} mcg_atm_select_t; + +/*! @brief MCG OSC Clock Select */ +typedef enum _mcg_oscsel_select +{ + kMcgOscselOsc, /*!< Selects System Oscillator (OSCCLK) */ + kMcgOscselRtc, /*!< Selects 32 kHz RTC Oscillator */ +#if FSL_FEATURE_MCG_HAS_IRC_48M + kMcgOscselIrc /*!< Selects 48 MHz IRC Oscillator */ +#endif +} mcg_oscsel_select_t; + +/*! @brief MCG OSC monitor mode */ +typedef enum _mcg_osc_monitor_mode +{ + kMcgOscMonitorInt, /*!< Generate interrupt when clock lost. */ + kMcgOscMonitorReset /*!< Generate reset when clock lost. */ +} mcg_osc_monitor_mode_t; + +/*! @brief MCG PLLCS select */ +typedef enum _mcg_pll_clk_select +{ + kMcgPllClkSelPll0, /*!< PLL0 output clock is selected */ +#if FSL_FEATURE_MCG_HAS_EXTERNAL_PLL + kMcgPllClkSelExtPll, /* External PLL clock is selected */ +#else + kMcgPllClkSelPll1, /* PLL1 output clock is selected */ +#endif +} mcg_pll_clk_select_t; + +/*! @brief MCG auto trim machine error code. */ +typedef enum _mcg_atm_error +{ + kMcgAtmErrorNone, /*!< No error. */ + kMcgAtmErrorBusClockRange, /*!< Bus clock frequency is not in 8MHz to 16 MHz. */ + kMcgAtmErrorDesireFreqRange, /*!< Desired frequency is out of range. */ + kMcgAtmErrorIrcUsed, /*!< IRC clock is used to generate system clock. */ + kMcgAtmErrorTrimValueInvalid, /*!< The auto trim compare value ACT is invalid. */ + kMcgAtmErrorHardwareFail /*!< ATC[ATMF] fail flag asserts. */ +} mcg_atm_error_t; + +/*! @brief MCG status. */ +typedef enum _mcg_status +{ + kStatus_MCG_Success = 0U, /*!< Success. */ + kStatus_MCG_Fail = 1U, /*!< Execution failed. */ +} mcg_status_t; + +extern uint32_t g_xtal0ClkFreq; /* EXTAL0 clock */ +#if FSL_FEATURE_MCG_HAS_OSC1 +extern uint32_t g_xtal1ClkFreq; /* EXTAL1 clock */ +#endif +#if FSL_FEATURE_MCG_HAS_EXTERNAL_PLL +extern uint32_t g_extPllClkFreq; /* External PLL clock */ +#endif +extern uint32_t g_xtalRtcClkFreq; /* EXTAL RTC clock */ + +extern uint32_t g_fastInternalRefClkFreq; /* Fast IRC clock */ +extern uint32_t g_slowInternalRefClkFreq; /* Slow IRC clock */ + +#if FSL_FEATURE_MCG_HAS_IRC_48M +#define CPU_INTERNAL_IRC_48M 48000000U +#endif + +#if defined(MCG_BWR_C6_CME) +#define MCG_BWR_C6_CME0 MCG_BWR_C6_CME +#endif + +#if defined(MCG_BRD_C6_CME) +#define MCG_BRD_C6_CME0 MCG_BRD_C6_CME +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! @name MCG out clock access API*/ +/*@{*/ + +/*! + * @brief Tests the external clock frequency. + * + * This function tests the external clock frequency, including OSC, RTC and IRC48M. + * If the OSC is not initialized, this function returns 0. + * + * @param base Base address for current MCG instance. + * @param oscselVal External OSC selection. + * @return MCG external reference clock frequency. + */ +uint32_t CLOCK_HAL_TestOscFreq(MCG_Type * base, mcg_oscsel_select_t oscselVal); + +/*! + * @brief Tests the FLL external reference frequency based on the input parameters. + * + * This function calculates the MCG FLL external reference clock value in + * frequency(Hertz) based on the input parameters. + * + * @param base Base address for current MCG instance. + * @param extFreq External OSC frequency. + * @param frdivVal FLL external reference divider value (FRDIV). + * @param range0 OSC0 frequency range selection. + * @param oscsel External OSC selection. + * @return MCG FLL external reference clock frequency. + */ +uint32_t CLOCK_HAL_TestFllExternalRefFreq(MCG_Type * base, + uint32_t extFreq, + uint8_t frdivVal, + osc_range_t range0, + mcg_oscsel_select_t oscsel); +/*! + * @brief Gets the current MCG FLL clock. + * + * This function returns the FLL reference clock frequency based on the + * current MCG configurations and settings. FLL should be properly configured + * in order to get the valid value. + * + * @param base Base address for current MCG instance. + * @return Frequency value in Hertz of FLL reference clock. + */ +uint32_t CLOCK_HAL_GetFllRefClk(MCG_Type * base); + +/*! + * @brief Calculates the FLL frequency based on the input parameters. + * + * This function calculates the FLL frequency based on input parameters. + * + * @param base Base address for current MCG instance. + * @param fllRef FLL reference clock frequency. + * @param dmx32 DCO max 32K setting. + * @param drs DCO range seletion. + * @return Frequency value in Hertz of the mcgfllclk. + */ +uint32_t CLOCK_HAL_TestFllFreq(MCG_Type * base, + uint32_t fllRef, + mcg_dmx32_select_t dmx32, + mcg_dco_range_select_t drs); + +/*! + * @brief Gets the current MCG FLL clock. + * + * This function returns the mcgfllclk value in frequency(Hertz) based on the + * current MCG configurations and settings. FLL should be properly configured + * get the valid value. + * + * @param base Base address for current MCG instance. + * @return Frequency value in Hertz of the mcgpllclk. + */ +uint32_t CLOCK_HAL_GetFllClk(MCG_Type * base); + +#if FSL_FEATURE_MCG_HAS_PLL +/*! + * @brief Calculates the PLL PRDIV and VDIV. + * + * This function calculates the proper PRDIV and VDIV to generate desired PLL + * output frequency with input reference clock frequency. It returns the closest + * frequency PLL could generate, the corresponding PRDIV/VDIV are returned from + * parameters. If desire frequency is not valid, this function returns 0. + * + * @param refFreq PLL reference frequency. + * @param desireFreq Desired PLL output frequency. + * @param prdiv PRDIV value to generate desired PLL frequency. + * @param vdiv VDIV value to generate desired PLL frequency. + * @return Closest frequency PLL could generate. + */ +uint32_t CLOCK_HAL_CalculatePllDiv(uint32_t refFreq, + uint32_t desireFreq, + uint8_t *prdiv, + uint8_t *vdiv); + +/*! + * @brief Gets the current MCG PLL/PLL0 clock. + * + * This function returns the mcgpllclk/mcgpll0 value in frequency(Hertz) based + * on the current MCG configurations and settings. PLL/PLL0 should be properly + * configured in order to get the valid value. + * + * @param base Base address for current MCG instance. + * @return Frequency value in Hertz of the mcgpllclk or the mcgpll0clk. + */ +uint32_t CLOCK_HAL_GetPll0Clk(MCG_Type * base); +#endif + +#if FSL_FEATURE_MCG_HAS_PLL1 +/*! + * @brief Gets the current MCG PLL1 clock. + * + * This function returns the mcgpll1clk value in frequency (Hertz) based + * on the current MCG configurations and settings. PLL1 should be properly configured + * in order to get the valid value. + * + * @param base Base address for current MCG instance. + * @return Frequency value in Hertz of mcgpll1clk. + */ +uint32_t CLOCK_HAL_GetPll1Clk(MCG_Type * base); +#endif + +#if FSL_FEATURE_MCG_HAS_EXTERNAL_PLL +/*! + * @brief Gets the current external PLL clock. + * + * This function returns the extpllclk value in frequency (Hertz). The external PLL + * is configured outside of the MCG module. + * + * @param base Base address for current MCG instance. + * @return value Frequency value in Hertz of mcgpll1clk. + */ +uint32_t CLOCK_HAL_GetExtPllClk(MCG_Type * base); +#endif + +/*! + * @brief Gets the current MCG internal reference clock(MCGIRCLK). + * + * This function returns the MCGIRCLK value in frequency (Hertz) based + * on the current MCG configurations and settings. It does not check if the + * MCGIRCLK is enabled or not, just calculate and return the value. + * + * @param base Base address for current MCG instance. + * @return Frequency value in Hertz of the MCGIRCLK. + */ +uint32_t CLOCK_HAL_GetInternalRefClk(MCG_Type * base); + +/*! + * @brief Gets the current MCG fixed frequency clock(MCGFFCLK). + * + * This function get the MCGFFCLK, it is only valid when its frequency is not + * more than MCGOUTCLK/8. If MCGFFCLK is invalid, this function returns 0. + * + * @param base Base address for current MCG instance. + * @return Frequency value in Hertz of MCGFFCLK. + */ +uint32_t CLOCK_HAL_GetFixedFreqClk(MCG_Type * base); + +/*! + * @brief Gets the current MCG out clock. + * + * This function returns the mcgoutclk value in frequency (Hertz) based on the + * current MCG configurations and settings. The configuration should be + * properly done in order to get the valid value. + * + * @param base Base address for current MCG instance. + * @return Frequency value in Hertz of mcgoutclk. + */ +uint32_t CLOCK_HAL_GetOutClk(MCG_Type * base); + +/*@}*/ + +/*! @name MCG control register access API*/ +/*@{*/ + +/*! + * @brief Sets the Clock Source Select + * + * This function selects the clock source for the MCGOUTCLK. + * + * @param base Base address for current MCG instance. + * @param select Clock source selection + * - 00: Output of FLL or PLLCS is selected(depends on PLLS control bit) + * - 01: Internal reference clock is selected. + * - 10: External reference clock is selected. + * - 11: Reserved. + */ +static inline void CLOCK_HAL_SetClkOutSrc(MCG_Type * base, mcg_clkout_src_t select) +{ + MCG_BWR_C1_CLKS(base, select); +} + +/*! + * @brief Gets the Clock Mode Status. + * + * This function gets the Clock Mode Status. These bits indicate the current clock mode. + * The CLKST bits do not update immediately after a write to the CLKS bits due to + * internal synchronization between clock domains. + * + * @param base Base address for current MCG instance. + * @return Clock Mode Status + * - 00: Output of the FLL is selected (reset default). + * - 01: Internal reference clock is selected. + * - 10: External reference clock is selected. + * - 11: Output of the PLL is selected. + */ +static inline mcg_clkout_stat_t CLOCK_HAL_GetClkOutStat(MCG_Type * base) +{ + return (mcg_clkout_stat_t)MCG_BRD_S_CLKST(base); +} + +/*! + * @brief Sets the Low Power Select. + * + * This function controls whether the FLL (or PLL) is disabled in the BLPI and the + * BLPE modes. In the FBE or the PBE modes, setting this bit to 1 transitions the MCG + * into the BLPE mode. In the FBI mode, setting this bit to 1 transitions the MCG into + * the BLPI mode. In any other MCG mode, the LP bit has no effect. + * + * @param base Base address for current MCG instance. + * @param enable Enable low power or not: + * - true: FLL (or PLL) is not disabled in bypass modes + * - false: FLL (or PLL) is disabled in bypass modes (lower power) + */ +static inline void CLOCK_HAL_SetLowPowerModeCmd(MCG_Type * base, bool enable) +{ + MCG_BWR_C2_LP(base, enable); +} + +#if FSL_FEATURE_MCG_USE_OSCSEL +/*! + * @brief Sets the MCG OSC Clock Select Setting. + * + * This function selects the MCG external reference clock. + * + * @param base Base address for current MCG instance. + * @param setting MCG OSC Clock Select Setting + * - 0: Selects System Oscillator (OSCCLK). + * - 1: Selects 32 kHz RTC Oscillator. + */ +static inline void CLOCK_HAL_SetOscselMode(MCG_Type * base, mcg_oscsel_select_t setting) +{ + MCG_WR_C7_OSCSEL(base, setting); +} +#endif + +/*@}*/ + +/*! @name MCG FLL API */ +/*@{*/ + +/*! + * @brief Gets the FLL source status. + * + * This function gets the Internal Reference Status. This bit indicates the current + * source for the FLL reference clock. The IREFST bit does not update immediately + * after a write to the IREFS bit due to internal synchronization between the clock + * domains. + * + * @param base Base address for current MCG instance. + * @return Internal Reference Status + * - 0: Source of FLL reference clock is the external reference clock. + * - 1: Source of FLL reference clock is the internal reference clock. + */ +static inline mcg_fll_src_t CLOCK_HAL_GetFllSrc(MCG_Type * base) +{ + return (mcg_fll_src_t)MCG_BRD_S_IREFST(base); +} + +/*! + * @brief Sets the FLL Filter Preserve Enable Setting. + * + * This function sets the FLL Filter Preserve Enable. This bit prevents the + * FLL filter values from resetting allowing the FLL output frequency to remain the + * same during the clock mode changes where the FLL/DCO output is still valid. + * (Note: This requires that the FLL reference frequency remain the same as + * the value prior to the new clock mode switch. Otherwise, the FLL filter and the frequency + * values change.) + * + * @param base Base address for current MCG instance. + * @param enable FLL Filter Preserve Enable Setting + * - true: FLL filter and FLL frequency retain their previous values + * during new clock mode change + * - false: FLL filter and FLL frequency will reset on changes to correct + * clock mode + */ +static inline void CLOCK_HAL_SetFllFilterPreserveCmd(MCG_Type * base, bool enable) +{ + MCG_BWR_SC_FLTPRSRV(base, enable); +} + +/*! + * @brief Calculates the proper FRDIV setting. + * + * This function calculates the proper FRDIV setting according to the FLL + * reference clock. FLL reference clock frequency after FRDIV must be in the + * range of 31.25 kHz to 39.0625 kHz. + * + * @param range0 RANGE0 setting. + * @param oscsel OSCSEL setting. + * @param inputFreq The reference clock frequency before FRDIV. + * @param frdiv FRDIV result. + * @retval kStatus_MCG_Success Proper FRDIV is got. + * @retval kStatus_MCG_Fail Could not get proper FRDIV. + */ +mcg_status_t CLOCK_HAL_GetAvailableFrdiv(osc_range_t range0, + mcg_oscsel_select_t oscsel, + uint32_t inputFreq, + uint8_t *frdiv); + +/*@}*/ + +/*! @name MCG internal reference clock APIs */ +/*@{*/ + +/*! + * @brief Sets the internal reference clock enable or not. + * + * This function enables/disables the internal reference clock to use as the MCGIRCLK. + * + * @param base Base address for current MCG instance. + * @param enable Enable or disable internal reference clock. + * - true: MCGIRCLK active + * - false: MCGIRCLK inactive + */ +static inline void CLOCK_HAL_SetInternalRefClkEnableCmd(MCG_Type * base, bool enable) +{ + MCG_BWR_C1_IRCLKEN(base, enable); +} + +/*! + * @brief Sets the internal reference clock enable or nor in stop mode. + * + * This function controls whether or not the internal reference clock remains + * enabled when the MCG enters Stop mode. + * + * @param base Base address for current MCG instance. + * @param enable Enable or disable the internal reference clock stop setting. + * - true: Internal reference clock is enabled in Stop mode if IRCLKEN is set + * or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. + * - false: Internal reference clock is disabled in Stop mode + */ +static inline void CLOCK_HAL_SetInternalRefClkEnableInStopCmd(MCG_Type * base, bool enable) +{ + MCG_BWR_C1_IREFSTEN(base, enable); +} + +/*! + * @brief Sets the Internal Reference Clock Select. + * + * This function selects between the fast or slow internal reference clock source. + * + * @param base Base address for current MCG instance. + * @param select Internal reference clock source. + * - 0: Slow internal reference clock selected. + * - 1: Fast internal reference clock selected. + */ +static inline void CLOCK_HAL_SetInternalRefClkMode(MCG_Type * base, + mcg_irc_mode_t mode) +{ + MCG_BWR_C2_IRCS(base, mode); +} + +/*! + * @brief Gets the Internal Reference Clock Status. + * + * This function gets the Internal Reference Clock Status. The IRCST bit indicates the + * current source for the internal reference clock select clock (IRCSCLK). The IRCST bit + * does not update immediately after a write to the IRCS bit due to the internal + * synchronization between clock domains. The IRCST bit is only updated if the + * internal reference clock is enabled, either by the MCG being in a mode that uses the + * IRC or by setting the C1[IRCLKEN] bit. + * + * @param base Base address for current MCG instance. + * @return Internal Reference Clock Status + * - 0: Source of internal reference clock is the slow clock (32 kHz IRC). + * - 1: Source of internal reference clock is the fast clock (2 MHz IRC). + */ +static inline mcg_irc_mode_t CLOCK_HAL_GetInternalRefClkMode(MCG_Type * base) +{ + return (mcg_irc_mode_t)MCG_BRD_S_IRCST(base); +} + +/*! + * @brief Updates the Fast Clock Internal Reference Divider Setting. + * + * This function sets FCRDIV to a new value. FCRDIV cannot be + * changed when fast internal reference is enabled. + * If it is enabled, disable it , then set FCRDIV, and finally re enable + * it. + * + * @param base Base address for current MCG instance. + * @param fcrdiv Fast Clock Internal Reference Divider Setting + */ +void CLOCK_HAL_UpdateFastClkInternalRefDiv(MCG_Type * base, uint8_t fcrdiv); + +/*@}*/ + +/*! @name MCG PLL APIs */ +/*@{*/ + +#if FSL_FEATURE_MCG_HAS_PLL +/*! + * @brief Sets the PLL Clock Enable Setting. + * + * This function enables/disables the PLL0 independent of the PLLS and enables the PLL0 + * clock to use as the MCGPLL0CLK and the MCGPLL0CLK2X. (PRDIV0 needs to be programmed to + * the correct divider to generate a PLL1 reference clock in a valid reference range + * prior to setting the PLLCLKEN0 bit). Setting PLLCLKEN0 enables the external + * oscillator selected by REFSEL if not already enabled. Whenever the PLL0 is being + * enabled with the PLLCLKEN0 bit, and the external oscillator is being used + * as the reference clock, the OSCINIT 0 bit should be checked to make sure it is set. + * + * @param base Base address for current MCG instance. + * @param enable PLL Clock Enable Setting + * - true: MCGPLL0CLK and MCGPLL0CLK2X are active + * - false: MCGPLL0CLK and MCGPLL0CLK2X are inactive + */ +static inline void CLOCK_HAL_SetPll0EnableCmd(MCG_Type * base, bool enable) +{ + MCG_BWR_C5_PLLCLKEN0(base, enable); +} + +/*! + * @brief Sets the PLL0 enable or not in STOP mode. + * + * This function enables/disables the PLL0 Clock during a Normal Stop (In Low + * Power Stop mode, the PLL0 clock gets disabled even if PLLSTEN0=1). In all other + * power modes, the PLLSTEN0 bit has no affect and does not enable the PLL0 Clock + * to run if it is written to 1. + * + * @param base Base address for current MCG instance. + * @param enable PLL0 Stop Enable Setting + * - true: MCGPLL0CLK and MCGPLL0CLK2X are enabled if system is in + * Normal Stop mode. + * - false: MCGPLL0CLK and MCGPLL0CLK2X are disabled in any of the + * Stop modes. + */ +static inline void CLOCK_HAL_SetPll0EnableInStopCmd(MCG_Type * base, bool enable) +{ + MCG_BWR_C5_PLLSTEN0(base, enable); +} + +/*! + * @brief Gets the Loss of the Lock Status. + * + * This function gets the Loss of Lock Status. This bit is a sticky bit indicating + * the lock status for the PLL. LOLS 0 is set if after acquiring lock, the PLL + * output frequency has fallen outside the lock exit frequency tolerance. + * + * @param base Base address for current MCG instance. + * @return True if PLL0 has lost lock since LOLS 0 was last cleared. + */ +static inline bool CLOCK_HAL_IsPll0LostLock(MCG_Type * base) +{ + return (bool)MCG_BRD_S_LOLS0(base); +} + +/*! + * @brief Clears the PLL0 lost lock status. + * + * This function clears the Loss of Lock Status. + * + * @param base Base address for current MCG instance. + */ +static inline void CLOCK_HAL_ClearPll0LostLock(MCG_Type * base) +{ + MCG_BWR_S_LOLS0(base, 1U); +} + +/*! + * @brief Sets the loss of lock interrupt enable setting. + * + * This function determines whether an interrupt request is made following a loss + * of lock indication. This bit only has an effect when LOLS 0 is set. + * + * @param base Base address for current MCG instance. + * @param enable Loss of Lock Interrupt Enable Setting + * - true: Generate an interrupt request on loss of lock. + * - false: No interrupt request is generated on loss of lock. + */ +static inline void CLOCK_HAL_SetPll0LostLockIntCmd(MCG_Type * base, bool enable) +{ + MCG_BWR_C6_LOLIE0(base, enable); +} + +#if FSL_FEATURE_MCG_HAS_LOLRE +/*! + * @brief Sets the PLL Loss of Lock Reset Enable Setting. + * + * This function determines whether an interrupt or a reset request is made + * following a PLL loss of lock. + * + * @param base Base address for current MCG instance. + * @param enable PLL Loss of Lock Reset Enable Setting + * - true: Generate a reset request on a PLL loss of lock indication. + * - false: Interrupt request is generated on a PLL loss of lock + * indication. The PLL loss of lock interrupt enable bit + * must also be set to generate the interrupt request. + */ +static inline void CLOCK_HAL_SetPllLostLockResetCmd(MCG_Type * base, bool enable) +{ + MCG_BWR_C8_LOLRE(base, enable); +} +#endif /* FSL_FEATURE_MCG_HAS_LOLRE */ + +/*! + * @brief Gets the Lock Status. + * + * This function gets the Lock Status. This bit indicates whether the PLL0 has + * acquired the lock. Lock detection is disabled when not operating in either the PBE or the + * PEE mode unless PLLCLKEN0=1 and the MCG is not configured in the BLPI or the BLPE mode. + * While the PLL0 clock is locking to the desired frequency, MCGPLL0CLK and + * MCGPLL0CLK2X are gated off until the LOCK0 bit gets asserted. If the lock + * status bit is set, changing the value of the PRDIV0[2:0] bits in the C5 register + * or the VDIV0[4:0] bits in the C6 register causes the lock status bit to clear + * and stay cleared until the PLL0 has reacquired the lock. The loss of the PLL0 reference + * clock also causes the LOCK0 bit to clear until the PLL0 has an entry into the LLS, + * VLPS, or a regular Stop with PLLSTEN0=0 also causes the lock status bit to clear + * and stay cleared until the stop mode is exited and the PLL0 has reacquired the lock. + * Any time the PLL0 is enabled and the LOCK0 bit is cleared, the MCGPLL0CLK and + * MCGPLL0CLK2X are gated off until the LOCK0 bit is reasserted. + * + * @param base Base address for current MCG instance. + * @return True if PLL0 is locked. + */ +static inline bool CLOCK_HAL_IsPll0Locked(MCG_Type * base) +{ + return (bool)MCG_BRD_S_LOCK0(base); +} + +/*! + * @brief Selects the PLL output or FLL output as the source of the MCGOUT. + * + * This function selects the PLL output or FLL output as the source of the + * MCGOUT. When this is set, use the CLOCK_HAL_IsPllSelected to check the status + * update. + * + * @param base Base address for current MCG instance. + * @param select True to select PLL, false to select FLL. + */ +static inline void CLOCK_HAL_SetPllSelectCmd(MCG_Type * base, bool select) +{ + MCG_BWR_C6_PLLS(base, select); +} + +/*! + * @brief Gets the PLL Select Status. + * + * This function gets the PLL Select Status. This bit indicates the clock source + * selected by PLLS . The PLLST bit does not update immediately after a write to + * the PLLS bit due to the internal synchronization between the clock domains. + * + * @param base Base address for current MCG instance. + * @return True if PLL output is selected to MCGOUT, false if FLL output is selected. + */ +static inline bool CLOCK_HAL_IsPllSelected(MCG_Type * base) +{ + return (bool)MCG_BRD_S_PLLST(base); +} + +/*! + * @brief Enables the PLL0 not in PLL mode. + * + * This function enables the PLL0 when MCG is not in the PLL mode, for example, + * when the MCG is in FEI mode. This function only sets up the PLL dividers and makes + * sure the PLL is locked. Ensure the PLL reference clock is enabled + * before calling this function. The function CLOCK_HAL_CalculatePllDiv can help to + * get the proper PLL divider values. + * + * @param base Base address for current MCG instance. + * @param prdiv PLL reference divider. + * @param vdiv PLL VCO divider. + * @param enbleInStop PLL enable or not in STOP mode. + */ +void CLOCK_HAL_EnablePll0InFllMode(MCG_Type * base, + uint8_t prdiv, + uint8_t vdiv, + bool enableInStop); +#endif + +#if FSL_FEATURE_MCG_HAS_PLL1 +/*! + * @brief Sets the PLL1 Clock Enable Setting. + * + * This function enables/disables the PLL1 independent of PLLS and enables the + * PLL clocks for use as MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X. (PRDIV1 needs + * to be programmed to the correct divider to generate a PLL1 reference clock in a + * valid reference range prior to setting the PLLCLKEN1 bit.) Setting PLLCLKEN1 + * enables the PLL1 selected external oscillator if not already enabled. + * Whenever the PLL1 is enabled with the PLLCLKEN1 bit, and the + * external oscillator is used as the reference clock, the OSCINIT1 bit should + * be checked to make sure it is set. + * + * @param base Base address for current MCG instance. + * @param enable PLL1 Clock Enable Setting + * - true: MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are active unless + * MCG is in a bypass mode with LP=1 (BLPI or BLPE). + * - false: MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are inactive. + */ +static inline void CLOCK_HAL_SetPll1EnableCmd(MCG_Type * base, bool enable) +{ + MCG_BWR_C11_PLLCLKEN1(base, enable); +} + +/*! + * @brief Sets the PLL1 enable or not in STOP mode. + * + * This function enables/disables the PLL1 Clock during the Normal Stop (In Low + * Power Stop modes, the PLL1 clock gets disabled even if PLLSTEN1=1. In all other + * power modes, PLLSTEN1 bit has no affect and does not enable the PLL1 Clock to + * run if it is written to 1. + * + * @param base Base address for current MCG instance. + * @param enable PLL1 Stop Enable Setting + * - true: PLL1 and its clocks (MCGPLL1CLK, MCGPLL1CLK2X, and + * MCGDDRCLK2X) are enabled if system is in Normal Stop mode. + * - false: PLL1 clocks (MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X) + * are disabled in any of the Stop modes. + */ +static inline void CLOCK_HAL_SetPll1EnableInStopCmd(MCG_Type * base, bool enable) +{ + MCG_BWR_C11_PLLSTEN1(base, enable); +} + +/*! + * @brief Sets the PLL1 Loss of Lock Interrupt Enable Setting. + * + * This function determines whether an interrupt request is made following a + * loss of lock indication for PLL1. This bit only has an affect when LOLS1 is set. + * + * @param base Base address for current MCG instance. + * @param enable PLL1 Loss of Lock Interrupt Enable Setting + * - true: Generate an interrupt request on loss of lock on PLL1. + * - false: No interrupt request is generated on loss of lock on PLL1. + */ +static inline void CLOCK_HAL_SetPll1LostLockIntCmd(MCG_Type * base, bool enable) +{ + MCG_BWR_C12_LOLIE1(base, enable); +} + +/*! + * @brief Gets the Loss of the Lock2 Status. + * + * This function gets the Loss of the Lock2 Status. This bit indicates + * the lock status for the PLL1. LOLS1 is set if after acquiring lock, the PLL1 + * output frequency has fallen outside the lock exit frequency tolerance, D unl. + * LOLIE1 determines whether an interrupt request is made when LOLS1 is set. This + * bit is cleared by reset or by writing a logic 1 to it when set. Writing a logic 0 + * to this bit has no effect. + * + * @param base Base address for current MCG instance. + * @return True if PLL1 has lost lock since LOLS 1 was last cleared. + */ +static inline bool CLOCK_HAL_IsPll1LostLock(MCG_Type * base) +{ + return (bool)MCG_BRD_S2_LOLS1(base); +} + +/*! + * @brief Clears the PLL1 lost lock status. + * + * This function clears the Loss of Lock Status. + * + * @param base Base address for current MCG instance. + */ +static inline void CLOCK_HAL_ClearPll1LostLock(MCG_Type * base) +{ + MCG_BWR_S2_LOLS1(base, 1U); +} + +/*! + * @brief Gets the Lock1 Status. + * + * This function gets the Lock1 Status. This bit indicates whether PLL1 has + * acquired the lock. PLL1 Lock detection is disabled when not operating in either + * PBE or PEE mode unless the PLLCLKEN1=1 and the the MCG is not configured in the BLPI or the + * BLPE mode. While the PLL1 clock is locking to the desired frequency, MCGPLL1CLK, + * MCGPLL1CLK2X, and MCGDDRCLK2X are gated off until the LOCK1 bit gets + * asserted. If the lock status bit is set, changing the value of the PRDIV1[2:0] + * bits in the C8 register or the VDIV2[4:0] bits in the C9 register causes the + * lock status bit to clear and stay cleared until the PLL1 has reacquired lock. + * Loss of PLL1 reference clock also causes the LOCK1 bit to clear until the PLL1 + * has reacquired the lock. Entry into the LLS, VLPS, or a regular Stop with the PLLSTEN1=0 also + * causes the lock status bit to clear and stay cleared until the Stop mode is exited + * and the PLL1 has reacquired the lock. Any time the PLL1 is enabled and the LOCK1 bit + * is cleared, the MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are gated off + * until the LOCK1 bit is asserted again. + * + * @param base Base address for current MCG instance. + * @return True if PLL1 is locked. + */ +static inline bool CLOCK_HAL_IsPll1Locked(MCG_Type * base) +{ + return (bool)MCG_BRD_S2_LOCK1(base); +} +#endif /* FSL_FEATURE_MCG_HAS_PLL1 */ + +#if (FSL_FEATURE_MCG_HAS_PLL1 || FSL_FEATURE_MCG_HAS_EXTERNAL_PLL) +/*! + * @brief Sets the PLL Clock Select Setting. + * + * This function controls whether the PLL0 or PLL1/ExtPLL output is selected as the + * MCG source when CLKS are programmed in PLL Engaged External (PEE) mode + * (CLKS[1:0]=00 and IREFS=0 and PLLS=1). + * + * @param base Base address for current MCG instance. + * @param setting PLL Clock Select Setting + * - 0: PLL0 output clock is selected. + * - 1: PLL1/ExtPLL output clock is selected. + */ +static inline void CLOCK_HAL_SetPllClkSelMode(MCG_Type * base, mcg_pll_clk_select_t setting) +{ + MCG_BWR_C11_PLLCS(base, setting); +} + +/*! + * @brief Gets the PLL Clock Select Status. + * + * This function gets the PLL Clock Select Status. The PLLCST indicates the PLL + * clock selected by PLLCS. The PLLCST bit is not updated immediately after a + * write to the PLLCS bit due internal synchronization between clock domains. + * + * @param base Base address for current MCG instance. + * @return PLL Clock Select Status + * - 0: Source of PLLCS is PLL0 clock. + * - 1: Source of PLLCS is PLL1/ExtPLL clock. + */ +static inline mcg_pll_clk_select_t CLOCK_HAL_GetPllClkSelMode(MCG_Type * base) +{ + return (mcg_pll_clk_select_t)MCG_BRD_S2_PLLCST(base); +} +#endif /* FSL_FEATURE_MCG_HAS_PLL1 || FSL_FEATURE_MCG_HAS_EXTERNAL_PLL */ + +#if FSL_FEATURE_MCG_HAS_PLL1 +/*! + * @brief Enables the PLL1 not in PLL mode. + * + * This function enables the PLL1 when MCG is not in PLL modes, for example, + * when MCG is in FEI mode. This function only sets up the PLL dividers and makes + * sure PLL is locked. Ensure the PLL reference clock is enabled + * before this function. The function CLOCK_HAL_CalculatePllDiv helps to + * get the proper PLL divider values. + * + * @param base Base address for current MCG instance. + * @param prdiv PLL reference divider. + * @param vdiv PLL VCO divider. + * @param enbleInStop PLL enable or not in STOP mode. + */ +void CLOCK_HAL_EnablePll1InFllMode(MCG_Type * base, + uint8_t prdiv, + uint8_t vdiv, + bool enableInStop); + +#if FSL_FEATURE_MCG_USE_PLLREFSEL +/*! + * @brief Sets the PLL0 External Reference Select Setting. + * + * This function selects the PLL0 external reference clock source. + * + * @param base Base address for current MCG instance. + * @param setting PLL0 External Reference Select Setting + * - 0: Selects OSC0 clock source as its external reference clock + * - 1: Selects OSC1 clock source as its external reference clock + */ +static inline void CLOCK_HAL_SetPll0RefMode(MCG_Type * base, + mcg_pll_ref_mode_t setting) +{ + BW_MCG_C5_PLLREFSEL0(base, setting); +} + +/*! + * @brief Sets the PLL1 External Reference Select Setting. + * + * This function selects the PLL1 external reference clock source. + * + * @param base Base address for current MCG instance. + * @param setting PLL1 External Reference Select Setting + * - 0: Selects OSC0 clock source as its external reference clock. + * - 1: Selects OSC1 clock source as its external reference clock. + */ +static inline void CLOCK_HAL_SetPll1RefMode(MCG_Type * base, + mcg_pll_ref_mode_t setting) +{ + BW_MCG_C11_PLLREFSEL1(base, setting); +} +#endif /* FSL_FEATURE_MCG_USE_PLLREFSEL */ + +#endif /* FSL_FEATURE_MCG_HAS_PLL1 */ + +/*@}*/ + +/*! @name MCG OSC APIs */ +/*@{*/ + +/*! + * @brief Sets the OSC0 work mode. + * + * This function sets the OSC0 work mode, include frequency range select, high gain + * oscillator select, and external reference select. + * + * @param base Base address for current MCG instance. + * @param range Frequency range select. + * @param hgo High gain oscillator select. + * @param erefs External reference select. + */ +void CLOCK_HAL_SetOsc0Mode(MCG_Type * base, + osc_range_t range, + osc_gain_t hgo, + osc_src_t erefs); + +/*! + * @brief Gets the OSC Initialization Status. + * + * This function gets the OSC Initialization Status. This bit, which resets to 0, is set + * to 1 after the initialization cycles of the crystal oscillator clock have completed. + * After being set, the bit is cleared to 0 if the OSC is subsequently disabled. See the + * OSC module's detailed description for more information. + * + * @param base Base address for current MCG instance. + * @return True if OSC0 is stable. + */ +static inline bool CLOCK_HAL_IsOsc0Stable(MCG_Type * base) +{ + return (bool)MCG_BRD_S_OSCINIT0(base); +} + +/*! + * @brief Enables the OSC0 external clock monitor. + * + * This function enables the loss of clock monitoring circuit for the OSC0 + * external reference mux select. The monitor mode determines whether an + * interrupt or a reset request is generated following a loss of the OSC0 indication. + * External clock monitor should only be enabled when the MCG is in an operational + * mode that uses the external clock (FEE, FBE, PEE, PBE, or BLPE). Whenever the + * monitor is enabled, the value of the RANGE0 bits in the C2 register + * should not be changed. External clock monitor should be disabled before the MCG + * enters any Stop mode. Otherwise, a reset request may occur while in Stop mode. + * External clock monitor should also be disabled before entering VLPR or VLPW + * power modes if the MCG is in BLPE mode. + * + * @param base Base address for current MCG instance. + * @param mode Generate interrupt or reset when OSC loss detected. + */ +void CLOCK_HAL_EnableOsc0Monitor(MCG_Type * base, mcg_osc_monitor_mode_t mode); + +/*! + * @brief Disables the OSC0 external clock monitor. + * + * This function disables the loss of clock monitoring circuit for the OSC0 + * external reference mux select. + * + * @param base Base address for current MCG instance. + */ +static inline void CLOCK_HAL_DisableOsc0Monitor(MCG_Type * base) +{ + MCG_BWR_C6_CME0(base, 0U); +} + +/*! + * @brief Checks the OSC0 external clock monitor is enabled or not. + * + * This function checks whether the loss of clock monitoring circuit for the OSC0 + * external reference mux select is enabled or not. + * + * @param base Base address for current MCG instance. + * @return True if monitor is enabled. + */ +static inline bool CLOCK_HAL_IsOsc0MonitorEnabled(MCG_Type * base) +{ + return (bool)MCG_BRD_C6_CME0(base); +} + +/*! + * @brief Gets the OSC0 Loss of Clock Status. + * + * This function gets the OSC0 Loss of Clock Status. The LOCS0 indicates when a loss of + * OSC0 reference clock has occurred. The LOCS0 bit only has an effect when CME0 is set. + * + * @param base Base address for current MCG instance. + * @return True if loss of OSC0 has occurred. + */ +static inline bool CLOCK_HAL_IsOsc0LostLock(MCG_Type * base) +{ + return (bool)MCG_BRD_SC_LOCS0(base); +} + +/*! + * @brief Clears the OSC0 Loss of Clock Status. + * + * This function clears the OSC0 Loss of Clock Status. + * + * @param base Base address for current MCG instance. + */ +static inline void CLOCK_HAL_ClearOsc0LostLock(MCG_Type * base) +{ + MCG_BWR_SC_LOCS0(base, 1U); +} + +#if FSL_FEATURE_MCG_HAS_RTC_32K +/*! + * @brief Enables the RTC OSC external clock monitor. + * + * This function enables the loss of the clock monitoring circuit for the + * output of the RTC external reference clock. The LOCRE1 bit determines whether an + * interrupt or a reset request is generated following a loss of the RTC clock indication. + * The monitor should only be enabled when the MCG is in an operational mode + * that uses the external clock (FEE, FBE, PEE, PBE, or BLPE). Monitor must be disabled + * before the MCG enters any Stop mode. Otherwise, a reset request may occur + * while in Stop mode. The monitor should also be disabled before entering VLPR or + * VLPW power modes if the MCG is in BLPE mode. + * + * @param base Base address for current MCG instance. + * @param mode Generate interrupt or reset when RTC OSC loss detected. + */ +void CLOCK_HAL_EnableRtcOscMonitor(MCG_Type * base, mcg_osc_monitor_mode_t mode); + +/*! + * @brief Disables the RTC OSC external clock monitor. + * + * This function disables the loss of clock monitoring circuit for the RTC OSC + * external reference mux select. + * + * @param base Base address for current MCG instance. + */ +static inline void CLOCK_HAL_DisableRTCOscMonitor(MCG_Type * base) +{ + MCG_BWR_C8_CME1(base, 0U); +} + +/*! + * @brief Checks the OSC RTC external clock monitor is enabled or not. + * + * This function checks whether the loss of clock monitoring circuit for the OSC + * RTC external reference mux select is enabled or not. + * + * @param base Base address for current MCG instance. + * @return True if monitor is enabled. + */ +static inline bool CLOCK_HAL_IsRtcOscMonitorEnabled(MCG_Type * base) +{ + return (bool)MCG_BRD_C8_CME1(base); +} + +/*! + * @brief Gets the RTC Loss of Clock Status. + * + * This function gets the RTC Loss of Clock Status. This bit indicates when a loss + * of clock has occurred. This bit is cleared by writing a logic 1 to it when set. + * + * @param base Base address for current MCG instance. + * @return True if loss of RTC has occurred + */ +static inline bool CLOCK_HAL_IsRtcOscLostLock(MCG_Type * base) +{ + return (bool)MCG_BRD_C8_LOCS1(base); +} + +/*! + * @brief Clears the RTC Loss of Clock Status. + * + * This function clears the RTC Loss of Clock Status. + * + * @param base Base address for current MCG instance. + */ +static inline void CLOCK_HAL_ClearRtcOscLostLock(MCG_Type * base) +{ + MCG_BWR_C8_LOCS1(base, 1U); +} +#endif /* FSL_FEATURE_MCG_HAS_RTC_32K */ + +#if FSL_FEATURE_MCG_HAS_OSC1 +/*! + * @brief Sets the OSC0 work mode. + * + * This function sets the OSC0 work mode, includes the frequency range select, high gain + * oscillator select and external reference select. + * + * @param base Base address for current MCG instance. + * @param range Frequency range select. + * @param hgo High gain oscillator select. + * @param erefs External reference select. + */ +void CLOCK_HAL_SetOsc1Mode(MCG_Type * base, + osc_range_t range, + osc_gain_t hgo, + osc_src_t erefs); + +/*! + * @brief Gets the OSC1 Initialization Status. + * + * This function gets the OSC1 Initialization Status. This bit is set after the + * initialization cycles of the 2nd crystal oscillator clock have completed. See + * the Oscillator block guide for more details. + * + * @param base Base address for current MCG instance. + * @return True is OSC1 is stable. + */ +static inline bool CLOCK_HAL_IsOsc1Stable(MCG_Type * base) +{ + return (bool)MCG_BRD_S2_OSCINIT1(base); +} + +/*! + * @brief Enables the OSC1 external clock monitor. + * + * This function enables the loss of the clock monitor for the OSC1 external + * reference clock. The monitor mode determines whether a reset or interrupt + * request is generated following a loss of OSC1 external reference clock. + * The monitor should only be enabled when the MCG is in an operational mode + * that uses the external clock (PEE or PBE). Whenever the monitor is enabled, + * the value of the RANGE1 bits in the C10 register should not be changed. + * The monitor should be disabled before the MCG enters any Stop mode. + * Otherwise, a reset request may occur while in stop mode. + * + * @param base Base address for current MCG instance. + * @param mode Generate interrupt or reset when OSC loss detected. + */ +void CLOCK_HAL_EnableOsc1Monitor(MCG_Type * base, mcg_osc_monitor_mode_t mode); + +/*! + * @brief Disables the OSC1 external clock monitor. + * + * This function disables the loss of clock monitoring circuit for the OSC1 + * external reference mux select. + * + * @param base Base address for current MCG instance. + */ +static inline void CLOCK_HAL_DisableOsc1Monitor(MCG_Type * base) +{ + MCG_BWR_C12_CME2(base, 0U); +} + +/*! + * @brief Checks the OSC1 external clock monitor is enabled or not. + * + * This function checks whether the loss of clock monitoring circuit for the OSC1 + * external reference mux select is enabled or not. + * + * @param base Base address for current MCG instance. + * @return True if monitor is enabled. + */ +static inline bool CLOCK_HAL_IsOsc1MonitorEnabled(MCG_Type * base) +{ + return (bool)MCG_BRD_C12_CME2(base); +} + + +/*! + * @brief Gets the OSC1 Loss of Clock Status. + * + * This function gets the OSC1 Loss of Clock Status. This bit indicates when a loss + * of the OSC1 external reference clock has occurred. + * + * @param base Base address for current MCG instance. + * @return True if loss of OSC1 external reference clock has occurred. + */ +static inline bool CLOCK_HAL_IsOsc1LostLock(MCG_Type * base) +{ + return (bool)MCG_BRD_S2_LOCS2(base); +} + +/*! + * @brief Clears the OSC1 Loss of Clock Status. + * + * This function clears the OSC1 Loss of Clock Status. + * + * @param base Base address for current MCG instance. + */ +static inline void CLOCK_HAL_ClearOsc1LostLock(MCG_Type * base) +{ + MCG_BWR_S2_LOCS2(base, 1U); +} +#endif + +#if FSL_FEATURE_MCG_HAS_EXTERNAL_PLL +/*! + * @brief Enables the External PLL Clock monitor. + * + * This function enables the loss of the clock monitor for the External PLL + * clock. The monitor mode determines whether a reset or interrupt + * request is generated following a loss of EXT_PLL clock. + * The monitor should only be enabled when the MCG is in an operational mode + * that uses the EXT_PLL clock as CLKS source (PEE or PBE). + * + * @param base Base address for current MCG instance. + * @param mode Generate interrupt or reset when OSC loss detected. + */ +void CLOCK_HAL_EnableExtPllMonitor(MCG_Type * base, mcg_osc_monitor_mode_t mode); + +/*! + * @brief Disables the External PLL clock monitor. + * + * This function disables the loss of clock monitoring circuit for the External PLL + * external reference mux select. + * + * @param base Base address for current MCG instance. + */ +static inline void CLOCK_HAL_DisableExtPllMonitor(MCG_Type * base) +{ + MCG_BWR_C9_PLL_CME(base, 0U); +} + +/*! + * @brief Checks the External PLL clock monitor is enabled or not. + * + * This function checks whether the loss of clock monitoring circuit for the External PLL + * clock is enabled or not. + * + * @param base Base address for current MCG instance. + * @return True if monitor is enabled. + */ +static inline bool CLOCK_HAL_IsExtPllMonitorEnabled(MCG_Type * base) +{ + return (bool)MCG_BRD_C9_PLL_CME(base); +} + + +/*! + * @brief Gets the External PLL Loss of Clock Status. + * + * This function gets the External PLL Loss of Clock Status. This bit indicates when a loss + * of the External PLL clock has occurred. + * + * @param base Base address for current MCG instance. + * @return True if loss of External PLL clock has occurred. + */ +static inline bool CLOCK_HAL_IsExtPllLostLock(MCG_Type * base) +{ + return (bool)MCG_BRD_C9_EXT_PLL_LOCS(base); +} + +/*! + * @brief Clears the External PLL Loss of Clock Status. + * + * This function clears the External PLL Loss of Clock Status. + * + * @param base Base address for current MCG instance. + */ +static inline void CLOCK_HAL_ClearExtPllLostLock(MCG_Type * base) +{ + MCG_BWR_C9_EXT_PLL_LOCS(base, 1U); +} +#endif +/*@}*/ + +/*! @name MCG Auto Trim Machine (ATM) */ +/*@{*/ + +/*! + * @brief Auto trims the internal reference clock. + * + * This function trims the internal reference clock using external clock. If + * successful, it returns the kMcgAtmErrorNone and the frequency after trimming is received + * in the parameter actualFreq. If an error occurs, the error code is returned. + * + * @param base Base address for current MCG instance. + * @param extFreq External clock frequency, should be bus clock. + * @param desireFreq Frequency want to trim to. + * @param actualFreq Actual frequency after trim. + * @param atms Trim fast or slow internal reference clock. + * @return Return kMcgAtmErrorNone if success, otherwise return error code. + */ +mcg_atm_error_t CLOCK_HAL_TrimInternalRefClk(MCG_Type* base, + uint32_t extFreq, + uint32_t desireFreq, + uint32_t* actualFreq, + mcg_atm_select_t atms); + +/*! + * @brief Gets the Automatic Trim machine Fail Flag. + * + * This function gets the Automatic Trim machine Fail Flag. This bit asserts when the + * Automatic Trim Machine is + * enabled (ATME=1) and a write to the C1, C3, C4, and SC registers is detected or the MCG + * enters into a Stop mode. Writing to ATMF clears the flag. + * + * @param base Base address for current MCG instance. + * @return True if ATM failed. + */ +static inline bool CLOCK_HAL_IsAutoTrimMachineFailed(MCG_Type * base) +{ + return (bool)MCG_BRD_SC_ATMF(base); +} + +/*! + * @brief Clears the Automatic Trim machine Fail Flag. + * + * This function clears the Automatic Trim machine Fail Flag. + * + * @param base Base address for current MCG instance. + */ +static inline void CLOCK_HAL_ClearAutoTrimMachineFailed(MCG_Type * base) +{ + MCG_BWR_SC_ATMF(base, 1U); +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif +#endif /* __FSL_MCG_HAL_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_mcg_hal_modes.h b/KSDK_1.2.0/platform/hal/inc/fsl_mcg_hal_modes.h new file mode 100755 index 0000000..7a6a0e2 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_mcg_hal_modes.h @@ -0,0 +1,258 @@ +/* + * Copyright (c) 2013, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#if !defined(__FSL_MCG_HAL_MODES_H__) +#define __FSL_MCG_HAL_MODES_H__ + +#include <stdint.h> +#include <stdbool.h> +#include <assert.h> +#include "fsl_mcg_hal.h" +#if FSL_FEATURE_SOC_MCG_COUNT + +//! @addtogroup mcg_hal +//! @{ + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// + +/*! @brief MCG mode definitions */ +typedef enum _mcg_modes { + kMcgModeFEI = 0x01 << 0U, /*!< FEI - FLL Engaged Internal */ + kMcgModeFBI = 0x01 << 1U, /*!< FBI - FLL Bypassed Internal */ + kMcgModeBLPI = 0x01 << 2U, /*!< BLPI - Bypassed Low Power Internal */ + kMcgModeFEE = 0x01 << 3U, /*!< FEE - FLL Engaged External */ + kMcgModeFBE = 0x01 << 4U, /*!< FBE - FLL Bypassed External */ + kMcgModeBLPE = 0x01 << 5U, /*!< BLPE - Bypassed Low Power External */ + kMcgModePBE = 0x01 << 6U, /*!< PBE - PLL Bypassed Enternal */ + kMcgModePEE = 0x01 << 7U, /*!< PEE - PLL Engaged External */ + kMcgModeSTOP = 0x01 << 8U, /*!< STOP - Stop */ + kMcgModeError = 0x01 << 9U /*!< Unknown mode */ +} mcg_modes_t; + +/*! @brief MCG mode transition API error code definitions */ +typedef enum McgModeError { + + kMcgModeErrNone = 0x00U, /*!< No error. */ + kMcgModeErrModeUnreachable = 0x01U, /*!< Target mode is unreachable. */ + + /* Oscillator error codes */ + kMcgModeErrOscFreqRange = 0x21U, /*!< OSC frequency is invalid. */ + + /* IRC and FLL error codes */ + kMcgModeErrIrcSlowRange = 0x31U, /*!< slow IRC is outside allowed range */ + kMcgModeErrIrcFastRange = 0x32U, /*!< fast IRC is outside allowed range */ + kMcgModeErrFllRefRange = 0x33U, /*!< FLL reference frequency is outsice allowed range */ + kMcgModeErrFllFrdivRange = 0x34U, /*!< FRDIV outside allowed range */ + kMcgModeErrFllDrsRange = 0x35U, /*!< DRS is out of range */ + kMcgModeErrFllDmx32Range = 0x36U, /*!< DMX32 setting not allowed. */ + + /* PLL error codes */ + kMcgModeErrPllPrdivRange = 0x41U, /*!< PRDIV outside allowed range */ + kMcgModeErrPllVdivRange = 0x42U, /*!< VDIV outside allowed range */ + kMcgModeErrPllRefClkRange = 0x43U, /*!< PLL reference clock frequency, out of range */ + kMcgModeErrPllLockBit = 0x44U, /*!< LOCK or LOCK2 bit did not set */ + kMcgModeErrPllOutClkRange = 0x45U, /*!< PLL output frequency is outside allowed range. */ + kMcgModeErrMax = 0x1000U +} mcg_mode_error_t; + +//////////////////////////////////////////////////////////////////////////////// +// API +//////////////////////////////////////////////////////////////////////////////// + +#if defined(__cplusplus) +extern "C" { +#endif // __cplusplus + +/*! + * @brief Gets the current MCG mode. + * + * This function checks the MCG registers and determine current MCG mode. + * + * @param base Base address for current MCG instance. + * @return Current MCG mode or error code mcg_modes_t + */ +mcg_modes_t CLOCK_HAL_GetMcgMode(MCG_Type * base); + +/*! + * @brief Set MCG to FEI mode. + * + * This function sets MCG to FEI mode. + * + * @param base Base address for current MCG instance. + * @param drs The DCO range selection. + * @param fllStableDelay Delay function to make sure FLL is stable. + * @param outClkFreq MCGCLKOUT frequency in new mode. + * @return Error code + */ +mcg_mode_error_t CLOCK_HAL_SetFeiMode(MCG_Type * base, + mcg_dco_range_select_t drs, + void (* fllStableDelay)(void), + uint32_t *outClkFreq); + +/*! + * @brief Set MCG to FEE mode. + * + * This function sets MCG to FEE mode. + * + * @param base Base address for current MCG instance. + * @param oscselval OSCSEL in FEE mode. + * @param frdivVal FRDIV in FEE mode. + * @param dmx32 DMX32 in FEE mode. + * @param drs The DCO range selection. + * @param fllStableDelay Delay function to make sure FLL is stable. + * @param outClkFreq MCGCLKOUT frequency in new mode. + * @return Error code + */ +mcg_mode_error_t CLOCK_HAL_SetFeeMode(MCG_Type * base, + mcg_oscsel_select_t oscselVal, + uint8_t frdivVal, + mcg_dmx32_select_t dmx32, + mcg_dco_range_select_t drs, + void (* fllStableDelay)(void), + uint32_t *outClkFreq); + +/*! + * @brief Set MCG to FBI mode. + * + * This function sets MCG to FBI mode. + * + * @param base Base address for current MCG instance. + * @param drs The DCO range selection. + * @param ircselect The internal reference clock to select. + * @param fllStableDelay Delay function to make sure FLL is stable. + * @param outClkFreq MCGCLKOUT frequency in new mode. + * @return Error code + */ +mcg_mode_error_t CLOCK_HAL_SetFbiMode(MCG_Type * base, + mcg_dco_range_select_t drs, + mcg_irc_mode_t ircSelect, + uint8_t fcrdivVal, + void (* fllStableDelay)(void), + uint32_t *outClkFreq); + +/*! + * @brief Set MCG to FBE mode. + * + * This function sets MCG to FBE mode. + * + * @param base Base address for current MCG instance. + * @param oscselval OSCSEL in FEE mode. + * @param frdivVal FRDIV in FEE mode. + * @param dmx32 DMX32 in FEE mode. + * @param drs The DCO range selection. + * @param fllStableDelay Delay function to make sure FLL is stable. + * @param outClkFreq MCGCLKOUT frequency in new mode. + * @return Error code + */ +mcg_mode_error_t CLOCK_HAL_SetFbeMode(MCG_Type * base, + mcg_oscsel_select_t oscselVal, + uint8_t frdivVal, + mcg_dmx32_select_t dmx32, + mcg_dco_range_select_t drs, + void (* fllStableDelay)(void), + uint32_t *outClkFreq); + +/*! + * @brief Set MCG to BLPI mode. + * + * This function sets MCG to BLPI mode. + * + * @param base Base address for current MCG instance. + * @param ircselect The internal reference clock to select. + * @param outClkFreq MCGCLKOUT frequency in new mode. + * @return Error code + */ +mcg_mode_error_t CLOCK_HAL_SetBlpiMode(MCG_Type * base, + uint8_t fcrdivVal, + mcg_irc_mode_t ircSelect, + uint32_t *outClkFreq); + +/*! + * @brief Set MCG to BLPE mode. + * + * This function sets MCG to BLPE mode. + * + * @param base Base address for current MCG instance. + * @param oscselval OSCSEL in FEE mode. + * @param outClkFreq MCGCLKOUT frequency in new mode. + * @return Error code + */ +mcg_mode_error_t CLOCK_HAL_SetBlpeMode(MCG_Type * base, + mcg_oscsel_select_t oscselVal, + uint32_t *outClkFreq); + +/*! + * @brief Set MCG to PBE mode. + * + * This function sets MCG to PBE mode. + * + * @param base Base address for current MCG instance. + * @param oscselval OSCSEL in FBE mode. + * @param pllcsselect PLLCS in PBE mode. + * @param prdivval PRDIV in PBE mode. + * @param vdivVal VDIV in PBE mode. + * @param outClkFreq MCGCLKOUT frequency in new mode. + * @return Error code + */ +mcg_mode_error_t CLOCK_HAL_SetPbeMode(MCG_Type * base, + mcg_oscsel_select_t oscselVal, + mcg_pll_clk_select_t pllcsSelect, + uint8_t prdivVal, + uint8_t vdivVal, + uint32_t *outClkFreq); + +/*! + * @brief Set MCG to PBE mode. + * + * This function sets MCG to PBE mode. + * + * @param base Base address for current MCG instance. + * @param outClkFreq MCGCLKOUT frequency in new mode. + * @return Error code + * @note This function only change CLKS to use PLL/FLL output. If the + * PRDIV/VDIV are different from PBE mode, please setup these + * settings in PBE mode and wait for stable then switch to PEE mode. + */ +mcg_mode_error_t CLOCK_HAL_SetPeeMode(MCG_Type * base, + uint32_t *outClkFreq); + + +#if defined(__cplusplus) +} +#endif // __cplusplus + +//! @} + +#endif +#endif // __FSL_MCG_HAL_MODES_H__ +//////////////////////////////////////////////////////////////////////////////// +// EOF +//////////////////////////////////////////////////////////////////////////////// diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_mcglite_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_mcglite_hal.h new file mode 100755 index 0000000..44cf7f1 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_mcglite_hal.h @@ -0,0 +1,488 @@ +/* +* Copyright (c) 2014-2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#if !defined(__FSL_MCGLITE_HAL_H__) +#define __FSL_MCGLITE_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> +#include <assert.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_MCGLITE_COUNT + +/*! @addtogroup mcglite_hal*/ +/*! @{*/ + +/*! @file fsl_mcglite_hal.h */ + +/******************************************************************************* +* Definitions +******************************************************************************/ +extern uint32_t g_xtalRtcClkFreq; /* EXTAL RTC clock */ +extern uint32_t g_xtal0ClkFreq; /* EXTAL0 clock */ + +/*! @brief MCG_Lite constant definitions. */ +enum _mcglite_constant +{ + kMcgliteConst0 = 0U, + kMcgliteConst2M = 2000000U, + kMcgliteConst8M = 8000000U, + kMcgliteConst48M = 48000000U, +}; + +/*! @brief MCG_Lite clock source selection. */ +typedef enum _mcglite_mcgoutclk_source +{ + kMcgliteClkSrcHirc, /*!< MCGOUTCLK source is HIRC */ + kMcgliteClkSrcLirc, /*!< MCGOUTCLK source is LIRC */ + kMcgliteClkSrcExt, /*!< MCGOUTCLK source is external clock source */ + kMcgliteClkSrcReserved +} mcglite_mcgoutclk_source_t; + +/*! @brief MCG_Lite LIRC select. */ +typedef enum _mcglite_lirc_select +{ + kMcgliteLircSel2M, /*!< slow internal reference(LIRC) 2MHz clock selected */ + kMcgliteLircSel8M, /*!< slow internal reference(LIRC) 8MHz clock selected */ +} mcglite_lirc_select_t; + +/*! @brief MCG_Lite divider factor selection for clock source*/ +typedef enum _mcglite_lirc_div +{ + kMcgliteLircDivBy1 = 0U, /*!< divider is 1 */ + kMcgliteLircDivBy2 , /*!< divider is 2 */ + kMcgliteLircDivBy4 , /*!< divider is 4 */ + kMcgliteLircDivBy8 , /*!< divider is 8 */ + kMcgliteLircDivBy16, /*!< divider is 16 */ + kMcgliteLircDivBy32, /*!< divider is 32 */ + kMcgliteLircDivBy64, /*!< divider is 64 */ + kMcgliteLircDivBy128 /*!< divider is 128 */ +} mcglite_lirc_div_t; + +/*! @brief MCG_Lite external clock Select */ +typedef enum _osc_src +{ + kOscSrcExt, /*!< Selects external input clock */ + kOscSrcOsc /*!< Selects Oscillator */ +} osc_src_t; + +/*! @brief MCG frequency range select */ +typedef enum _osc_range +{ + kOscRangeLow, /*!< Low frequency range selected for the crystal OSC */ + kOscRangeHigh, /*!< High frequency range selected for the crystal OSC */ + kOscRangeVeryHigh, /*!< Very High frequency range selected for the crystal OSC */ + kOscRangeVeryHigh1 /*!< Very High frequency range selected for the crystal OSC */ +} osc_range_t; + +/*! @brief MCG high gain oscillator select */ +typedef enum _osc_gain +{ + kOscGainLow, /*!< Configure crystal oscillator for low-power operation */ + kOscGainHigh /*!< Configure crystal oscillator for high-gain operation */ +} osc_gain_t; + +/******************************************************************************* +* API +******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! @name MCG_Lite output clock access API*/ +/*@{*/ + +/*! +* @brief Gets the current MCGPCLK frequency. +* +* This function returns the MCGPCLK frequency (Hertz) based on +* the current MCG_Lite configurations and settings. The configuration should be +* properly done in order to get the valid value. +* +* @param base MCG_Lite register base address. +* +* @return Frequency value in Hertz of MCGPCLK. +*/ +uint32_t CLOCK_HAL_GetPeripheralClk(MCG_Type * base); + +/*! +* @brief Gets the current MCG_Lite low internal reference clock(2MHz or 8MHz) +* +* This function returns the MCG_Lite LIRC frequency (Hertz) based +* on the current MCG_Lite configurations and settings. Please make sure LIRC +* has been properly configured to get the valid value. +* +* @param base MCG_Lite register base address. +* +* @return Frequency value in Hertz of the MCG_Lite LIRC. +*/ +uint32_t CLOCK_HAL_GetLircClk(MCG_Type * base); + +/*! +* @brief Gets the current MCG_Lite LIRC_DIV1_CLK frequency. +* +* This function returns the MCG_Lite LIRC_DIV1_CLK frequency (Hertz) based +* on the current MCG_Lite configurations and settings. Please make sure LIRC +* has been properly configured to get the valid value. +* +* @param base MCG_Lite register base address. +* +* @return Frequency value in Hertz of the MCG_Lite LIRC_DIV1_CLK. +*/ +uint32_t CLOCK_HAL_GetLircDiv1Clk(MCG_Type * base); + +/*! +* @brief Gets the current MCGIRCLK frequency. +* +* This function returns the MCGIRCLK frequency (Hertz) based +* on the current MCG_Lite configurations and settings. Please make sure LIRC +* has been properly configured to get the valid value. +* +* @param base MCG_Lite register base address. +* +* @return Frequency value in Hertz of MCGIRCLK. +*/ +uint32_t CLOCK_HAL_GetInternalRefClk(MCG_Type * base); + +/*! +* @brief Gets the current MCGOUTCLK frequency. +* +* This function returns the MCGOUTCLK frequency (Hertz) based on +* the current MCG_Lite configurations and settings. The configuration should be +* properly done in order to get the valid value. +* +* @param base MCG_Lite register base address. +* +* @return Frequency value in Hertz of MCGOUTCLK. +*/ +uint32_t CLOCK_HAL_GetOutClk(MCG_Type * base); + +/*@}*/ + +/*! @name MCG_Lite control register access API*/ +/*@{*/ + +/*! +* @brief Sets the Low Internal Reference Select. +* +* This function sets the LIRC to work at 2MHz or 8MHz. +* +* @param base MCG_Lite register base address. +* +* @param select 2MHz or 8MHz. +*/ +static inline void CLOCK_HAL_SetLircSelMode(MCG_Type * base, mcglite_lirc_select_t select) +{ + MCG_BWR_C2_IRCS(base, select); +} + +/*! +* @brief Sets the low internal reference divider 1. +* +* This function sets the low internal reference divider 1, the register FCRDIV. +* +* @param base MCG_Lite register base address. +* +* @param setting LIRC divider 1 setting value. +*/ +static inline void CLOCK_HAL_SetLircRefDiv(MCG_Type * base, mcglite_lirc_div_t setting) +{ + MCG_BWR_SC_FCRDIV(base, setting); +} + +/*! +* @brief Sets the low internal reference divider 2. +* +* This function sets the low internal reference divider 2. +* +* @param base MCG_Lite register base address. +* +* @param setting LIRC divider 2 setting value. +*/ +static inline void CLOCK_HAL_SetLircDiv2(MCG_Type * base, mcglite_lirc_div_t setting) +{ + MCG_BWR_MC_LIRC_DIV2(base, setting); +} + +/*! +* @brief Enables the Low Internal Reference Clock setting +* +* This function enables/disables the low internal reference clock. +* +* @param base MCG_Lite register base address. +* +* @param enable Enable or disable internal reference clock. +* - true: MCG_Lite Low IRCLK active +* - false: MCG_Lite Low IRCLK inactive +*/ +static inline void CLOCK_HAL_SetLircCmd(MCG_Type * base, bool enable) +{ + MCG_BWR_C1_IRCLKEN(base, enable); +} + +/*! +* @brief Sets the Low Internal Reference Clock disabled or not in STOP mode. +* +* This function controls whether or not the low internal reference clock remains +* enabled when the MCG_Lite enters STOP mode. +* +* @param base MCG_Lite register base address. +* +* @param enable Enable or disable low internal reference clock stop setting. +* - true: Internal reference clock is enabled in stop mode if IRCLKEN is set +before entering STOP mode. +* - false: Low internal reference clock is disabled in STOP mode +*/ +static inline void CLOCK_HAL_SetLircStopCmd(MCG_Type * base, bool enable) +{ + MCG_BWR_C1_IREFSTEN(base, enable); +} + +/*! +* @brief Enable or disable the High Internal Reference Clock setting. +* +* This function enables/disables the internal reference clock for use as MCGPCLK. +* +* @param base MCG_Lite register base address. +* +* @param enable Enable or disable HIRC. +* - true: MCG_Lite HIRC active +* - false: MCG_Lite HIRC inactive +*/ +static inline void CLOCK_HAL_SetHircCmd(MCG_Type * base, bool enable) +{ + MCG_BWR_MC_HIRCEN(base, enable); +} + +/*! +* @brief Sets the External Reference Select. +* +* This function selects the source for the external reference clock. +* Refer to the Oscillator (OSC) for more details. +* +* @param base MCG_Lite register base address. +* +* @param select External Reference Select. +* - 0: External input clock requested +* - 1: Crystal requested +*/ +static inline void CLOCK_HAL_SetExtRefSelMode0(MCG_Type * base, osc_src_t select) +{ + MCG_BWR_C2_EREFS0(base, select); +} + +/*! +* @brief Gets the Clock Mode Status. +* +* This function gets the Clock Mode Status. These bits indicate the current clock mode. +* The CLKST bits do not update immediately after a write to the CLKS bits due to +* internal synchronization between clock domains. +* +* @param base MCG_Lite register base address. +* +* @return status Clock Mode Status +* - 00: HIRC clock is select. +* - 01: LIRC(low Internal reference clock) is selected. +* - 10: External reference clock is selected. +* - 11: Reserved. +*/ +static inline mcglite_mcgoutclk_source_t CLOCK_HAL_GetClkSrcStat(MCG_Type * base) +{ + return (mcglite_mcgoutclk_source_t)MCG_BRD_S_CLKST(base); +} + +/*! +* @brief Gets the OSC Initialization Status. +* +* This function gets the OSC Initialization Status OSCINIT0. This bit, +* which resets to 0, is set to 1 after the initialization cycles of +* the crystal oscillator clock have completed. After being set, the bit +* is cleared to 0 if the OSC is subsequently disabled. See +* the OSC module's detailed description for more information. +* +* @param base MCG_Lite register base address. +* +* @return OSC initialization status +*/ +static inline bool CLOCK_HAL_IsOscStable(MCG_Type * base) +{ + return (bool)MCG_BRD_S_OSCINIT0(base); +} + +#if FSL_FEATURE_MCGLITE_HAS_RANGE0 +/*! + * @brief Sets the Frequency Range0 Select Setting. + * + * This function selects the frequency range for the OSC crystal oscillator + * or an external clock source. See the Oscillator chapter for more details and + * the device data sheet for the frequency ranges used. + * + * @param base MCG_Lite register base address. + * @param setting Frequency Range0 Select Setting + * - 00: Low frequency range selected for the crystal oscillator. + * - 01: High frequency range selected for the crystal oscillator. + * - 1X: Very high frequency range selected for the crystal oscillator. + */ +static inline void CLOCK_HAL_SetRange0Mode(MCG_Type * base, osc_range_t setting) +{ + MCG_BWR_C2_RANGE0(base, setting); +} +#endif + +#if FSL_FEATURE_MCGLITE_HAS_HGO0 +/*! + * @brief Sets the High Gain Oscillator0 Select Setting. + * + * This function controls the OSC0 crystal oscillator mode of operation. + * See the Oscillator chapter for more details. + * + * @param base MCG_Lite register base address. + * @param setting High Gain Oscillator0 Select Setting + * - 0: Configure crystal oscillator for low-power operation. + * - 1: Configure crystal oscillator for high-gain operation. + */ +static inline void CLOCK_HAL_SetHighGainOsc0Mode(MCG_Type * base, + osc_gain_t setting) +{ + MCG_BWR_C2_HGO0(base, setting); +} +#endif + +#if FSL_FEATURE_MCGLITE_HAS_HCTRIM +/*! + * @brief Gets the High-frequency IRC coarse trim value. + * + * This function gets the High-frequency IRC coarse trim value. + * + * @param base MCG_Lite register base address. + */ +static inline uint8_t CLOCK_HAL_GetHircCoarseTrim(MCG_Type * base) +{ + return MCG_BRD_HCTRIM_COARSE_TRIM(base); +} +#endif + +#if FSL_FEATURE_MCGLITE_HAS_HTTRIM +/*! + * @brief Gets the High-frequency IRC tempco trim value. + * + * This function gets the High-frequency IRC tempco trim value. + * + * @param base MCG_Lite register base address. + */ +static inline uint8_t CLOCK_HAL_GetHircTempcoTrim(MCG_Type * base) +{ + return MCG_BRD_HTTRIM_TEMPCO_TRIM(base); +} +#endif + +#if FSL_FEATURE_MCGLITE_HAS_HFTRIM +/*! + * @brief Gets the High-frequency IRC fine trim value. + * + * This function gets the High-frequency IRC fine trim value. + * + * @param base MCG_Lite register base address. + */ +static inline uint8_t CLOCK_HAL_GetHircFineTrim(MCG_Type * base) +{ + return MCG_BRD_HFTRIM_FINE_TRIM(base); +} +#endif + +#if FSL_FEATURE_MCGLITE_HAS_LTRIMRNG +/*! + * @brief Gets the LIRC 8M TRIM RANGE value. + * + * This function gets the LIRC 8M RANGE value. + * + * @param base MCG_Lite register base address. + */ +static inline uint8_t CLOCK_HAL_GetLirc8MTrimRange(MCG_Type * base) +{ + return MCG_BRD_LTRIMRNG_FTRIMRNG(base); +} + +/*! + * @brief Gets the LIRC 2M TRIM RANGE value. + * + * This function gets the LIRC 2M RANGE value. + * + * @param base MCG_Lite register base address. + */ +static inline uint8_t CLOCK_HAL_GetLirc2MTrimRange(MCG_Type * base) +{ + return MCG_BRD_LTRIMRNG_STRIMRNG(base); +} +#endif + +#if FSL_FEATURE_MCGLITE_HAS_LFTRIM +/*! + * @brief Gets the LIRC 8M trim value. + * + * This function gets the LIRC 8M trim value. + * + * @param base MCG_Lite register base address. + */ +static inline uint8_t CLOCK_HAL_GetLirc8MTrim(MCG_Type * base) +{ + return MCG_BRD_LFTRIM_LIRC_FTRIM(base); +} +#endif + +#if FSL_FEATURE_MCGLITE_HAS_LSTRIM +/*! + * @brief Gets the LIRC 2M trim value. + * + * This function gets the LIRC 2M trim value. + * + * @param base MCG_Lite register base address. + */ +static inline uint8_t CLOCK_HAL_GetLirc2MTrim(MCG_Type * base) +{ + return MCG_BRD_LSTRIM_LIRC_STRIM(base); +} +#endif + + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif +#endif /* __FSL_MCGLITE_HAL_H__*/ +/******************************************************************************* +* EOF +******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_mcglite_hal_modes.h b/KSDK_1.2.0/platform/hal/inc/fsl_mcglite_hal_modes.h new file mode 100755 index 0000000..5cb48db --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_mcglite_hal_modes.h @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2014-2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#if !defined(__FSL_MCGLITE_HAL_MODES_H__) +#define __FSL_MCGLITE_HAL_MODES_H__ + +#include <stdint.h> +#include <stdbool.h> +#include "fsl_mcglite_hal.h" +#if FSL_FEATURE_SOC_MCGLITE_COUNT + +/*! @addtogroup mcglite_hal*/ +/*! @{*/ + +/*! @file fsl_mcg_lite_hal_modes.h */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief MCG_Lite clock mode definitions */ +typedef enum _mcglite_mode +{ + kMcgliteModeHirc48M, /*!< clock mode is HIRC 48M*/ + kMcgliteModeLirc8M, /*!< clock mode is LIRC 8M */ + kMcgliteModeLirc2M, /*!< clock mode is LIRC 2M */ + kMcgliteModeExt, /*!< clock mode is EXT */ + kMcgliteModeStop, /*!< clock mode is STOP */ + kMcgliteModeError /*!< Unknown mode */ +} mcglite_mode_t; + +/*! @brief MCG_Lite mode transition API error code definitions */ +typedef enum McgliteModeErrorCode { + /* MCG_Lite mode error codes */ + kMcgliteModeErrNone = 0x00, /*!< - No error */ + kMcgliteModeErrExt = 0x01, /*!< - External clock source not available. */ +} mcglite_mode_error_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! @name MCG_Lite clock mode API */ +/*@{*/ + +/*! + * @brief Gets the current MCG_Lite clock mode. + * + * This is an internal function that checks the MCG registers and determine + * the current MCG_lite mode. + * + * @param base MCG_Lite register base address. + * + * @return Current MCG_Lite mode or error code. + */ +mcglite_mode_t CLOCK_HAL_GetMode(MCG_Type * base); + +/*! + * @brief Sets the MCG_Lite to HIRC mode. + * + * This is an internal function that changes MCG_Lite + * to HRIC mode. + * + * @param base MCG_Lite register base address. + * @param outclkfreq MCGOUTCLK frequency in new mode. + * + * @return Error code. + */ +mcglite_mode_error_t CLOCK_HAL_SetHircMode(MCG_Type * base, uint32_t *outClkFreq); + +/*! + * @brief Sets the MCG_Lite to LIRC mode. + * + * This is an internal function that changes MCG_Lite + * to LIRC mode. + * + * @param base MCG_Lite register base address. + * @param lirc Set to LIRC2M or LIRC8M. + * @param div1 The FCRDIV setting. + * @param outclkfreq MCGOUTCLK frequency in new mode. + * + * @return Error code. + */ +mcglite_mode_error_t CLOCK_HAL_SetLircMode(MCG_Type * base, + mcglite_lirc_select_t lirc, + mcglite_lirc_div_t div1, + uint32_t *outClkFreq); + +/*! + * @brief Sets the MCG_Lite to EXT mode. + * + * This is an internal function that changes MCG_Lite + * to EXT mode. Before this function, please make sure + * the OSC or external clock source is ready. + * + * @param base MCG_Lite register base address. + * @param outclkfreq MCGOUTCLK frequency in new mode. + * + * @return Error code. + */ +mcglite_mode_error_t CLOCK_HAL_SetExtMode(MCG_Type * base, uint32_t *outClkFreq); + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif +#endif /* __FSL_MCGLITE_HAL_MODES_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_mmdvsq_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_mmdvsq_hal.h new file mode 100755 index 0000000..978ba56 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_mmdvsq_hal.h @@ -0,0 +1,471 @@ +/* + * Copyright (c) 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#if !defined(__FSL_MMDVSQ_HAL_H__) +#define __FSL_MMDVSQ_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> +#include <assert.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_MMDVSQ_COUNT + +/*! @addtogroup mmdvsq_hal*/ +/*! @{*/ + +/*! @file fsl_mmdvsq_hal.h */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief MMDVSQ execution status */ +typedef enum _mmdvsq_execution_status +{ + kMmdvsqIdleSquareRoot = 0x01, /* MMDVSQ is idle, last calculation was a square root */ + kMmdvsqIdleDivide = 0x02, /* MMDVSQ is idle, last calculation was a divide */ + kMmdvsqBusySquareRoot = 0x05, /* MMDVSQ is busy processing a square root calculation */ + kMmdvsqBusyDivide = 0x06 /* MMDVSQ is busy processing a divide calculation */ +} mmdvsq_execution_status_t; + +/*! @brief MMDVSQ divide operation select */ +typedef enum _mmdvsq_divide_opertion_select +{ + kMmdvsqSignedDivideGetQuotient, /*Select signed divide operation, return the quotient */ + kMmdvsqUnsignedDivideGetQuotient, /* Select unsigned divide operation, return the quotient */ + kMmdvsqSignedDivideGetRemainder, /* Select signed divide operation, return the remainder */ + kMmdvsqUnsignedDivideGetRemainder /* Select unsigned divide operation, return the remainder */ +} mmdvsq_divide_operation_select_t; + +/*! @brief MMDVSQ divide fast start select */ +typedef enum _mmdvsq_divide_fast_start_select +{ + kMmdvsqDivideFastStart, /* Divide operation is initiated by a write to the DSOR register */ + kMmdvsqDivideNormalStart /* Divide operation is initiated by a write to CSR[SRT] = 1, normal start instead fast start*/ +} mmdvsq_divide_fast_start_select_t; + +/*! @brief MMDVSQ divide by zero setting*/ +typedef enum _mmdvsq_divide_by_zero_select +{ + kMmdvsqDivideByZeroDis, /* disable divide by zero detect */ + kMmdvsqDivideByZeroEn /* enable divide by zero detect */ +} mmdvsq_divide_by_zero_select_t; + +/*! @brief MMDVSQ divide by zero status*/ +typedef enum _mmdvsq_divide_by_zero_status +{ + kMmdvsqNonZeroDivisor, /*Divisor is not zero*/ + kMmdvsqZeroDivisor /*Divisor is zero */ +} mmdvsq_divide_by_zero_status_t; + +/*! @brief MMDVSQ unsigned or signed divide calculation select */ +typedef enum _mmdvsq_unsigned_divide_select +{ + kMmdvsqSignedDivide, /*Select signed divide operation*/ + kMmdvsqUnsignedDivide /* Select unsigned divide operation */ +} mmdvsq_unsined_divide_select_t; + + +/*! @brief MMDVSQ remainder or quotient result select */ +typedef enum _mmdvsq_remainder_calculation_select{ + kMmdvsqDivideReturnQuotient, /*Return quotient in RES register*/ + kMmdvsqDivideReturnRemainder /* Return remainder in RES register */ +} mmdvsq_remainder_calculation_select_t; + +/*! @brief MCG mode transition API error code definitions */ +typedef enum _mmdvsq_error_code_t{ + /* MMDVSQ error codes */ + kMmdvsqErrNotReady = 0x01, /* - MMDVSQ is busy */ + kMmdvsqErrDivideTimeOut = 0x02, /* - MMDVSQ is busy in divide operation */ + kMmdvsqErrSqrtTimeOut = 0x03, /* - MMDVSQ is busy in square root operation */ + kMmdvsqErrDivideByZero = 0x04 /* - MMDVSQ is in divide operation, and the divisor is zer0 */ +} mmdvsq_error_code_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! @name MMDVSQ operations access API*/ +/*@{*/ + +/*! + * @brief perform the current MMDVSQ unsigned divide operation and get remainder + * + * This function performs the MMDVSQ unsigned divide operation and get remainder. + * It is in block mode. For non-block mode, other HAL routines can be used. + * + * @param base Base address for current MMDVSQ instance. + * @param dividend -Dividend value + * @param divisor -Divisor value + * + * @return Unsigned divide calculation result in the MMDVSQ_RES register. + */ +uint32_t MMDVSQ_HAL_DivUR(MMDVSQ_Type * base, uint32_t dividend, uint32_t divisor); + +/*! + * @brief perform the current MMDVSQ unsigned divide operation and get quotient + * + * This function performs the MMDVSQ unsigned divide operation and get quotient. + * It is in block mode. For non-block mode, other HAL routines can be used. + * + * @param base Base address for current MMDVSQ instance. + * @param dividend -Dividend value + * @param divisor -Divisor value + * + * @return Unsigned divide calculation result in the MMDVSQ_RES register. + */ +uint32_t MMDVSQ_HAL_DivUQ(MMDVSQ_Type * base, uint32_t dividend, uint32_t divisor); + + +/*! + * @brief perform the current MMDVSQ signed divide operation and get remainder + * + * This function performs the MMDVSQ signed divide operation and get remainder. + * It is in block mode. For non-block mode, other HAL routines can be used. + * + * @param base Base address for current MMDVSQ instance. + * @param dividend -Dividend value + * @param divisor -Divisor value + * + * @return Signed divide calculation result in the MMDVSQ_RES register. + */ +uint32_t MMDVSQ_HAL_DivSR(MMDVSQ_Type * base, uint32_t dividend, uint32_t divisor); + +/*! + * @brief perform the current MMDVSQ signed divide operation and get quotient + * + * This function performs the MMDVSQ signed divide operation and get quotient. + * It is in block mode. For non-block mode, other HAL routines can be used. + * + * @param base Base address for current MMDVSQ instance. + * @param dividend -Dividend value + * @param divisor -Divisor value + * + * @return Signed divide calculation result in the MMDVSQ_RES register. + */ +uint32_t MMDVSQ_HAL_DivSQ(MMDVSQ_Type * base, uint32_t dividend, uint32_t divisor); + +/*! + * @brief set the current MMDVSQ square root operation + * + * This function performs the MMDVSQ square root operation and return the sqrt result of given radicantvalue + * It is in block mode. For non-block mode, other HAL routines can be used. + * + * @param base Base address for current MMDVSQ instance. + * @param radicand - Radicand value + * + * @return Square root calculation result in the MMDVSQ_RES register. + */ +uint16_t MMDVSQ_HAL_Sqrt(MMDVSQ_Type * base, uint32_t radicand); + +/*@}*/ + +/*! @name MMDVSQ control register access API*/ +/*@{*/ + +/*! + * @brief Get the current MMDVSQ execution status + * + * This function checks the current MMDVSQ execution status + * + * @param base Base address for current MMDVSQ instance. + * + * @return Current MMDVSQ execution status + */ +static inline mmdvsq_execution_status_t MMDVSQ_HAL_GetExecutionStatus(MMDVSQ_Type * base) +{ + return (mmdvsq_execution_status_t)(MMDVSQ_RD_CSR(base)>>MMDVSQ_CSR_SQRT_SHIFT); +} + +/*! + * @brief Get the current MMDVSQ BUSY status + * + * This function checks the current MMDVSQ BUSY status + * + * @param base Base address for current MMDVSQ instance. + * + * @return MMDVSQ is busy or idle + */ +static inline bool MMDVSQ_HAL_GetBusyStatus(MMDVSQ_Type * base) +{ + return MMDVSQ_BRD_CSR_BUSY(base); +} + +/*! + * @brief set the current MMDVSQ divide fast start + * + * This function sets the MMDVSQ divide fast start. + * + * @param base Base address for current MMDVSQ instance. + * @param enable Enable or disable divide fast start mode. + * - true: ensable divide fast start. + * - false: disable divide fast start, use normal start. + * + */ +static inline void MMDVSQ_HAL_SetDivideFastStart(MMDVSQ_Type * base, bool enable) +{ + MMDVSQ_BWR_CSR_DFS(base, enable ? 0 : 1); +} + +/*! + * @brief get the current MMDVSQ divide fast start setting + * + * This function gets the MMDVSQ divide fast start setting + * + * @param base Base address for current MMDVSQ instance. + * + * @return MMDVSQ divide start is fast start or normal start + * -true : enable fast start mode. + * -false : disable fast start, divide works normal start mode. + */ +static inline bool MMDVSQ_HAL_GetDivideFastStart(MMDVSQ_Type * base) +{ + return (!MMDVSQ_BRD_CSR_DFS(base)); +} + +/*! + * @brief set the current MMDVSQ divide by zero detection + * + * This function sets the MMDVSQ divide by zero detection + * + * @param base Base address for current MMDVSQ instance. + + * @param enable Enable or disable divide by zero detect. + * - true: Enable divide by zero detect. + * - false: Disable divide by zero detect. + * + */ +static inline void MMDVSQ_HAL_SetDivdeByZero(MMDVSQ_Type * base, bool enable ) +{ + MMDVSQ_BWR_CSR_DZE(base, enable ? 1 : 0); +} + +/*! + * @brief get the current MMDVSQ divide by zero setting + * + * This function gets the MMDVSQ divide by zero setting + * + * @param base Base address for current MMDVSQ instance. + * + * @return MMDVSQ divide is non-zero divisor or zero divisor + * - true: Enable divide by zero detect. + * - false: Disable divide by zero detect. + */ +static inline bool MMDVSQ_HAL_GetDivdeByZeroSetting(MMDVSQ_Type * base) +{ + + return MMDVSQ_BRD_CSR_DZE(base); +} + +/*! + * @brief get the current MMDVSQ divide by zero status + * + * This function gets the MMDVSQ divide by zero status + * + * @param base Base address for current MMDVSQ instance. + * + * @return MMDVSQ divide is non-zero divisor or zero divisor + * - true: zero divisor. + * - false: non-zero divisor. + */ +static inline bool MMDVSQ_HAL_GetDivdeByZeroStatus(MMDVSQ_Type * base) +{ + + return MMDVSQ_BRD_CSR_DZ(base); +} + +/*! + * @brief set the current MMDVSQ divide remainder calculation + * + * This function sets the MMDVSQ divide remainder calculation + * + * @param base Base address for current MMDVSQ instance. + * @param enable Return quotient or remainder in the MMDVSQ_RES register. + * - true: Return remainder in MMQVSQ_RES. + * - false: Return quotient in MMQVSQ_RES. + * + */ +static inline void MMDVSQ_HAL_SetRemainderCalculation(MMDVSQ_Type * base, bool enable) +{ + MMDVSQ_BWR_CSR_REM(base, enable ? 1 : 0); +} + +/*! + * @brief get the current MMDVSQ divide remainder calculation + * + * This function gets the MMDVSQ divide remainder calculation + * + * @param base Base address for current MMDVSQ instance. + * + * @return MMDVSQ divide remainder calculation is quotient or remainder + * - true: return remainder in RES register. + * - false: return quotient in RES register. + */ +static inline bool MMDVSQ_HAL_GetRemainderCalculation(MMDVSQ_Type * base) +{ + return MMDVSQ_BRD_CSR_REM(base); +} + +/*! + * @brief set the current MMDVSQ unsigned divide calculation + * + * This function sets the MMDVSQ unsigned divide calculation + * + * @param base Base address for current MMDVSQ instance. + * + * @param enable Enable or disable unsigned divide calculation. + * - true: Enable unsigned divide calculation. + * - false: Disable unsigned divide calculation. + + * + */ +static inline void MMDVSQ_HAL_SetUnsignedCalculation(MMDVSQ_Type * base, bool enable) +{ + MMDVSQ_BWR_CSR_USGN(base, enable ? 1 : 0); +} + +/*! + * @brief get the current MMDVSQ unsigned divide calculation + * + * This function gets the MMDVSQ unsigned divide calculation + * + * @param base Base address for current MMDVSQ instance. + * + * @return MMDVSQ divide is unsigned divide operation + * - true: perform an unsigned divide. + * - false: perform a signed divide + */ +static inline bool MMDVSQ_HAL_GetUnsignedCalculation(MMDVSQ_Type * base) +{ + return MMDVSQ_BRD_CSR_USGN(base); +} + +/*! + * @brief get the current MMDVSQ operation result + * + * This function gets the MMDVSQ operation result + * + * @param base Base address for current MMDVSQ instance. + * + * @return MMDVSQ operation result + */ +static inline uint32_t MMDVSQ_HAL_GetResult(MMDVSQ_Type * base) +{ + return MMDVSQ_RD_RES(base); +} + +/*! + * @brief set the current MMDVSQ dividend value + * + * This function sets the MMDVSQ dividend value + * + * @param base Base address for current MMDVSQ instance. + * +* @param dividend Dividend value for divide calculations. + */ +static inline void MMDVSQ_HAL_SetDividend(MMDVSQ_Type * base, uint32_t dividend) +{ + MMDVSQ_WR_DEND( base, dividend); +} + +/*! + * @brief get the current MMDVSQ dividend value + * + * This function gets the MMDVSQ dividend value + * + * @param base Base address for current MMDVSQ instance. + * + * @return MMDVSQ dividend value + */ +static inline uint32_t MMDVSQ_HAL_GetDividend(MMDVSQ_Type * base) +{ + return MMDVSQ_RD_DEND(base); +} + +/*! + * @brief set the current MMDVSQ divisor value + * + * This function sets the MMDVSQ divisor value + * + * @param base Base address for current MMDVSQ instance. + * +* @param divisor Divisor value for divide calculations.. + */ +static inline void MMDVSQ_HAL_SetDivisor(MMDVSQ_Type * base, uint32_t divisor) +{ + MMDVSQ_WR_DSOR(base, divisor); +} + +/*! + * @brief get the current MMDVSQ divisor value + * + * This function gets the MMDVSQ divisor value + * + * @param base Base address for current MMDVSQ instance. + * + * @return MMDVSQ divisor value + */ +static inline uint32_t MMDVSQ_HAL_GetDivisor(MMDVSQ_Type * base) +{ + return MMDVSQ_RD_DSOR(base); +} + +/*! + * @brief set the current MMDVSQ radicand value + * + * This function sets the MMDVSQ radicand value +* + * @param base Base address for current MMDVSQ instance. + * + * @param radicand Radicand value of Sqrt. + * + */ +static inline void MMDVSQ_HAL_SetRadicand(MMDVSQ_Type * base, uint32_t radicand) +{ + MMDVSQ_WR_RCND(base, radicand); +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif +#endif /* __FSL_MMDVSQ_HAL_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_mpu_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_mpu_hal.h new file mode 100755 index 0000000..2e73dd3 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_mpu_hal.h @@ -0,0 +1,461 @@ + /* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_MPU_HAL_H__ +#define __FSL_MPU_HAL_H__ + +#define FSL_FEATURE_MPU_SLAVEPORT 5U +#define FSL_FEATURE_MPU_MASTER 8U + +#include <assert.h> +#include <stdint.h> +#include <stdbool.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_MPU_COUNT + +/*! + * @addtogroup mpu_hal + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/* Macro should be in MK64F12.h */ +#define MPU_WORD_LOW_MASTER_SHIFT(n) (n*6) +#define MPU_WORD_LOW_MASTER_MASK(n) (0x1Fu<<MPU_WORD_LOW_MASTER_SHIFT(n)) +#define MPU_WORD_LOW_MASTER_WIDTH 5 +#define MPU_WORD_LOW_MASTER(n, x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_LOW_MASTER_SHIFT(n)))&MPU_WORD_LOW_MASTER_MASK(n)) + +#define MPU_LOW_MASTER_PE_SHIFT(n) (n*6+5) +#define MPU_LOW_MASTER_PE_MASK(n) (0x1u << MPU_LOW_MASTER_PE_SHIFT(n)) +#define MPU_WORD_MASTER_PE_WIDTH 1 +#define MPU_WORD_MASTER_PE(n, x) (((uint32_t)(((uint32_t)(x))<<MPU_LOW_MASTER_PE_SHIFT(n)))&MPU_LOW_MASTER_PE_MASK(n)) + +#define MPU_WORD_HIGH_MASTER_SHIFT(n) (n*2+23) +#define MPU_WORD_HIGH_MASTER_MASK(n) (0x03u << MPU_WORD_HIGH_MASTER_SHIFT(n)) +#define MPU_WORD_HIGH_MASTER_WIDTH 2 +#define MPU_WORD_HIGH_MASTER(n, x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_HIGH_MASTER_SHIFT(n)))&MPU_WORD_HIGH_MASTER_MASK(n)) + +/* Macro should be in MK64F12_extension.h */ +#define MPU_WR_WORD_LOW_MASTER(base, index, index2, n, value) (MPU_WR_WORD(base, index, index2, (MPU_RD_WORD(base, index, index2) & ~MPU_WORD_LOW_MASTER_MASK(n)) | MPU_WORD_LOW_MASTER(n, value))) +#define MPU_WR_WORD_PE(base, index, index2, n, value) (MPU_WR_WORD(base, index, index2, (MPU_RD_WORD(base, index, index2) & ~MPU_LOW_MASTER_PE_MASK(n)) | MPU_WORD_MASTER_PE(n, value))) +#define MPU_WR_WORD_HIGH_MASTER(base, index, index2, n, value) (MPU_WR_WORD(base, index, index2, (MPU_RD_WORD(base, index, index2) & ~MPU_WORD_HIGH_MASTER_MASK(n)) | MPU_WORD_HIGH_MASTER(n, value))) + +#define MPU_WR_WORD_RGDAAC_LOW_MASTER(base, index, n, value) (MPU_WR_RGDAAC(base, index, (MPU_RD_RGDAAC(base, index) & ~MPU_WORD_LOW_MASTER_MASK(n)) | MPU_WORD_LOW_MASTER(n, value))) +#define MPU_WR_WORD_RGDAAC_PE(base, index, n, value) (MPU_WR_RGDAAC(base, index, (MPU_RD_RGDAAC(base, index) & ~MPU_LOW_MASTER_PE_MASK(n)) | MPU_WORD_MASTER_PE(n, value))) +#define MPU_WR_WORD_RGDAAC_HIGH_MASTER(base, index, n, value) (MPU_WR_RGDAAC(base, index, (MPU_RD_RGDAAC(base, index) & ~MPU_WORD_HIGH_MASTER_MASK(n)) | MPU_WORD_HIGH_MASTER(n, value))) + +/*! @brief MPU region number region0~region11. */ +typedef enum _mpu_region_num{ +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 0U + kMPURegionNum00 = 0U, /*!< MPU region number 0*/ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 1U + kMPURegionNum01 = 1U, /*!< MPU region number 1*/ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 2U + kMPURegionNum02 = 2U, /*!< MPU region number 2*/ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 3U + kMPURegionNum03 = 3U, /*!< MPU region number 3*/ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 4U + kMPURegionNum04 = 4U, /*!< MPU region number 4*/ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 5U + kMPURegionNum05 = 5U, /*!< MPU region number 5*/ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 6U + kMPURegionNum06 = 6U, /*!< MPU region number 6*/ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 7U + kMPURegionNum07 = 7U, /*!< MPU region number 7*/ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 8U + kMPURegionNum08 = 8U, /*!< MPU region number 8*/ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 9U + kMPURegionNum09 = 9U, /*!< MPU region number 9*/ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 10U + kMPURegionNum10 = 10U, /*!< MPU region number 10*/ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 11U + kMPURegionNum11 = 11U, /*!< MPU region number 11*/ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 12U + kMPURegionNum12 = 12U, /*!< MPU region number 12*/ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 13U + kMPURegionNum13 = 13U, /*!< MPU region number 13*/ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 14U + kMPURegionNum14 = 14U, /*!< MPU region number 14*/ +#endif +#if FSL_FEATURE_MPU_DESCRIPTOR_COUNT > 15U + kMPURegionNum15 = 15U, /*!< MPU region number 15*/ +#endif +}mpu_region_num_t; + +/*! @brief Descripts the number of MPU regions. */ +typedef enum _mpu_region_total_num +{ + kMPU8Regions = 0x0U, /*!< MPU supports 8 regions */ + kMPU12Regions = 0x1U, /*!< MPU supports 12 regions */ + kMPU16Regions = 0x2U /*!< MPU supports 16 regions */ +}mpu_region_total_num_t; + +/*! @brief MPU hardware basic information. */ +typedef struct _mpu_hardware_info +{ + uint8_t kMPUHardwareRevisionLevel; /*!< Specifies the MPU's hardware and definition reversion level */ + uint8_t kMPUSupportSlavePortsNum; /*!< Specifies the number of slave ports connnected to MPU */ + mpu_region_total_num_t kMPUSupportRegionsNum; /*!< Indicates the number of region descriptors implemented */ +}mpu_hardware_info_t; + +/*! @brief MPU access error. */ +typedef enum _mpu_err_access_type{ + kMPUErrTypeRead = 0U, /*!< MPU error type---read */ + kMPUErrTypeWrite = 1U /*!< MPU error type---write */ +}mpu_err_access_type_t; + +/*! @brief MPU access error attributes.*/ +typedef enum _mpu_err_attributes{ + kMPUInstructionAccessInUserMode = 0U, /*!< access instruction error in user mode */ + kMPUDataAccessInUserMode = 1U, /*!< access data error in user mode */ + kMPUInstructionAccessInSupervisorMode = 2U, /*!< access instruction error in supervisor mode */ + kMPUDataAccessInSupervisorMode = 3U /*!< access data error in supervisor mode */ +}mpu_err_attributes_t; + +/*! @brief access MPU in which mode. */ +typedef enum _mpu_access_mode{ + kMPUAccessInUserMode = 0U, /*!< access data or instruction in user mode*/ + kMPUAccessInSupervisorMode = 1U /*!< access data or instruction in supervisor mode*/ +}mpu_access_mode_t; + +/*! @brief MPU master number. */ +typedef enum _mpu_master{ +#if FSL_FEATURE_MPU_MASTER > 1U + kMPUMaster0 = 0U, /*!< MPU master core */ +#endif +#if FSL_FEATURE_MPU_MASTER > 2U + kMPUMaster1 = 1U, /*!< MPU master defined in SOC */ +#endif +#if FSL_FEATURE_MPU_MASTER > 3U + kMPUMaster2 = 2U, /*!< MPU master defined in SOC */ +#endif +#if FSL_FEATURE_MPU_MASTER > 4U + kMPUMaster3 = 3U, /*!< MPU master defined in SOC */ +#endif +#if FSL_FEATURE_MPU_MASTER > 5U + kMPUMaster4 = 4U, /*!< MPU master defined in SOC */ +#endif +#if FSL_FEATURE_MPU_MASTER > 6U + kMPUMaster5 = 5U, /*!< MPU master defined in SOC */ +#endif +#if FSL_FEATURE_MPU_MASTER > 7U + kMPUMaster6 = 6U, /*!< MPU master defined in SOC */ +#endif +#if FSL_FEATURE_MPU_MASTER > 8U + kMPUMaster7 = 7U /*!< MPU master defined in SOC */ +#endif +}mpu_master_t; + +/*! @brief MPU error access control detail. */ +typedef enum _mpu_err_access_ctr{ + kMPUNoRegionHit = 0U, /*!< no region hit error */ + kMPUNoneOverlappRegion = 1U, /*!< access single region error */ + kMPUOverlappRegion = 2U /*!< access overlapping region error */ +}mpu_err_access_ctr_t; + +/*! @brief Descripts MPU detail error access info. */ +typedef struct _mpu_access_err_info +{ + mpu_master_t master; /*!< Access error master */ + mpu_err_attributes_t attributes; /*!< Access error attribues */ + mpu_err_access_type_t accessType; /*!< Access error type */ + mpu_err_access_ctr_t accessCtr; /*!< Access error control */ + uint32_t addr; /*!< Access error address */ + uint8_t slavePort; /*!< Access error slave port */ +#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER + uint8_t processorIdentification; /*!< Access error processor identification */ +#endif +}mpu_access_err_info_t; + +/*! @brief MPU access rights in supervisor mode for master0~master3. */ +typedef enum _mpu_supervisor_access_rights{ + kMPUSupervisorReadWriteExecute = 0U, /*!< Read write and execute operations are allowed in supervisor mode */ + kMPUSupervisorReadExecute = 1U, /*!< Read and execute operations are allowed in supervisor mode */ + kMPUSupervisorReadWrite = 2U, /*!< Read write operations are allowed in supervisor mode */ + kMPUSupervisorEqualToUsermode = 3U /*!< Access permission equal to user mode */ +}mpu_supervisor_access_rights_t; + +/*! @brief MPU access rights in user mode for master0~master3. */ +typedef enum _mpu_user_access_rights{ + kMPUUserNoAccessRights = 0U, /*!< no access allowed in user mode */ + kMPUUserExecute = 1U, /*!< execute operation is allowed in user mode */ + kMPUUserWrite = 2U, /*!< Write operation is allowed in user mode */ + kMPUUserWriteExecute = 3U, /*!< Write and execute operations are allowed in user mode */ + kMPUUserRead = 4U, /*!< Read is allowed in user mode */ + kMPUUserReadExecute = 5U, /*!< Read and execute operations are allowed in user mode */ + kMPUUserReadWrite = 6U, /*!< Read and write operations are allowed in user mode */ + kMPUUserReadWriteExecute = 7U /*!< Read write and execute operations are allowed in user mode */ +}mpu_user_access_rights_t; + +/*! @brief MPU access rights for low master0~master3. */ +typedef struct _mpu_low_masters_access_rights +{ + mpu_supervisor_access_rights_t superAccessRights; /*!< master access rights in supervisor mode */ + mpu_user_access_rights_t userAccessRights; /*!< master access rights in user mode */ +#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER + bool processIdentifierEnable; /*!< Enables or disables process identifier */ +#endif +}mpu_low_masters_access_rights_t; + +/*! @brief MPU access rights mode for high master4~master7. */ +typedef struct _mpu_high_masters_access_rights +{ + bool kMPUWriteEnable; /*!< Enables or disables write permission */ + bool kMPUReadEnable; /*!< Enables or disables read permission */ +}mpu_high_masters_access_rights_t; + +/*! + * @brief Data v for MPU region initialize + * + * This structure is used when calling the MPU_DRV_Init function. + * + */ +typedef struct MpuRegionConfig{ + mpu_region_num_t regionNum; /*!< MPU region number */ + uint32_t startAddr; /*!< Memory region start address */ + uint32_t endAddr; /*!< Memory region end address */ + mpu_low_masters_access_rights_t accessRights1[4]; /*!< Low masters access permission */ + mpu_high_masters_access_rights_t accessRights2[4]; /*!< Low masters access permission */ + bool regionEnable; /*!< Enables or disables region */ +}mpu_region_config_t; + +/*! @brief MPU status return codes.*/ +typedef enum _MPU_status { + kStatus_MPU_Success = 0x0U, /*!< MPU Succeed. */ + kStatus_MPU_Fail = 0x1U, /*!< MPU failed. */ + kStatus_MPU_NotInitlialized = 0x2U, /*!< MPU is not initialized yet. */ + kStatus_MPU_NullArgument = 0x3U, /*!< Argument is NULL. */ + } mpu_status_t; + +/******************************************************************************* + ** Variables + *******************************************************************************/ + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name MPU HAL. + * @{ + */ + +/*! + * @brief Enables the MPU module operation. + * + * @param base Base address of MPU peripheral instance. + */ +static inline void MPU_HAL_Enable(MPU_Type * base) +{ + MPU_BWR_CESR_VLD(base, 1U); +} + +/*! + * @brief Disables the MPU module operation. + * + * @param base Base address of MPU peripheral instance. + */ +static inline void MPU_HAL_Disable(MPU_Type * base) +{ + MPU_BWR_CESR_VLD(base, 0U); +} + +/*! + * @brief Checks whether the MPU module is enabled + * + * @param base Base address of MPU peripheral instance. + * @return State of the module + * @retval true MPU module is enabled. + * @retval false MPU module is disabled. + */ +static inline bool MPU_HAL_IsEnable(MPU_Type * base) +{ + return MPU_BRD_CESR_VLD(base); +} + +/*! + * @brief Gets MPU basic hardware info. + * + * @param base Base address of MPU peripheral instance. + * @param infoPtr The pointer to the hardware information structure see #mpu_hardware_info_t. + */ +void MPU_HAL_GetHardwareInfo(MPU_Type *base, mpu_hardware_info_t *infoPtr); + +/*! + * @brief Gets MPU derail error access info. + * + * @param base Base address of MPU peripheral instance. + * @param errInfoArrayPtr The pointer to array of structure mpu_access_err_info_t. + */ +void MPU_HAL_GetDetailErrorAccessInfo(MPU_Type *base, mpu_access_err_info_t *errInfoArrayPtr); + +/*! + * @brief Sets region start and end address. + * + * @param base Base address of MPU peripheral instance.. + * @param regionNum MPU region number. + * @param startAddr Region start address. + * @param endAddr Region end address. + */ +void MPU_HAL_SetRegionAddr(MPU_Type * base, mpu_region_num_t regionNum, uint32_t startAddr, uint32_t endAddr); + +/*! + * @brief Configures low master0~3 access permission for a specific region. + * + * @param base Base address of MPU peripheral instance. + * @param regionNum MPU region number. + * @param masterNum MPU master number. + * @param accessRightsPtr The pointer of master access rights see #mpu_low_masters_access_rights_t. + */ +void MPU_HAL_SetLowMasterAccessRights(MPU_Type * base, mpu_region_num_t regionNum, mpu_master_t masterNum, const mpu_low_masters_access_rights_t *accessRightsPtr); + +/*! + * @brief Sets high master access permission for a specific region. + * + * @param base Base address of MPU peripheral instance. + * @param regionNum MPU region number. + * @param masterNum MPU master number. + * @param accessRightsPtr The pointer of master access rights see #mpu_low_masters_access_rights_t. + */ +void MPU_HAL_SetHighMasterAccessRights(MPU_Type * base, mpu_region_num_t regionNum, mpu_master_t masterNum, const mpu_high_masters_access_rights_t *accessRightsPtr); + +/*! + * @brief Sets the region valid value. + * When a region changed not by alternating registers should set the valid again. + * + * @param base Base address of MPU peripheral instance. + * @param regionNum MPU region number. + * @param enable Enables or disables region. + */ +static inline void MPU_HAL_SetRegionValidCmd(MPU_Type * base, mpu_region_num_t regionNum, bool enable) +{ + assert(regionNum < FSL_FEATURE_MPU_DESCRIPTOR_COUNT); + MPU_BWR_WORD_VLD(base, regionNum, 3U, enable); +} + +#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER +/*! + * @brief Sets the process identifier mask. + * + * @param base The MPU peripheral base address. + * @param regionNum MPU region number. + * @param processIdentifierMask Process identifier mask value. + */ +static inline void MPU_HAL_SetProcessIdentifierMask(MPU_Type * base, mpu_region_num_t regionNum, uint8_t processIdentifierMask) +{ + assert(regionNum < FSL_FEATURE_MPU_DESCRIPTOR_COUNT); + MPU_BWR_WORD_PIDMASK(base, regionNum, 3U, processIdentifierMask); +} + +/*! + * @brief Sets the process identifier. + * + * @param base The MPU peripheral base address. + * @param regionNum MPU region number. + * @param processIdentifier Process identifier. + */ +static inline void MPU_HAL_SetProcessIdentifier(MPU_Type * base, mpu_region_num_t regionNum, uint8_t processIdentifier) +{ + assert(regionNum < FSL_FEATURE_MPU_DESCRIPTOR_COUNT); + MPU_BWR_WORD_PID(base, regionNum, 3U, processIdentifier); +} +#endif + +/*! + * @brief Configures low master0~3 access permission for a specific region. + * + * @param base Base address of MPU peripheral instance. + * @param regionNum MPU region number. + * @param masterNum MPU master number. + * @param accessRightsPtr The pointer of master access rights see #mpu_low_masters_access_rights_t. + */ +void MPU_HAL_SetLowMasterAccessRightsByAlternateReg(MPU_Type * base, mpu_region_num_t regionNum, mpu_master_t masterNum, const mpu_low_masters_access_rights_t *accessRightsPtr); + +/*! + * @brief Sets high master access permission for a specific region. + * + * @param base Base address of MPU peripheral instance. + * @param regionNum MPU region number. + * @param masterNum MPU master number. + * @param accessRightsPtr The pointer of master access rights see #mpu_low_masters_access_rights_t. + */ +void MPU_HAL_SetHighMasterAccessRightsByAlternateReg(MPU_Type * base, mpu_region_num_t regionNum, mpu_master_t masterNum, const mpu_high_masters_access_rights_t *accessRightsPtr); + + +/*! + * @brief Configures the MPU region. + * + * @param base The MPU peripheral base address. + * @param regionConfigPtr The pointer to the MPU user configure structure, see #mpu_region_config_t. + * + */ +void MPU_HAL_SetRegionConfig(MPU_Type * base, const mpu_region_config_t *regionConfigPtr); + +/*! + * @brief Initializes the MPU module. + * + * @param base The MPU peripheral base address. + */ +void MPU_HAL_Init(MPU_Type * base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif +#endif /* __FSL_MPU_HAL_H__*/ +/******************************************************************************* + * EOF + *******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_osc_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_osc_hal.h new file mode 100755 index 0000000..da0b622 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_osc_hal.h @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#if !defined(__FSL_OSC_HAL_H__) +#define __FSL_OSC_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> +#include <assert.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_OSC_COUNT + +/*! @addtogroup osc_hal*/ +/*! @{*/ + +/*! @file fsl_osc_hal.h */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Oscillator capacitor load configurations.*/ +typedef enum _osc_capacitor_config { + kOscCapacitor2p = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */ + kOscCapacitor4p = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */ + kOscCapacitor8p = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */ + kOscCapacitor16p = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */ +} osc_capacitor_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! @name oscillator control APIs*/ +/*@{*/ + +/*! + * @brief Enables the external reference clock for the oscillator. + * + * This function enables the external reference clock output + * for the oscillator, OSCERCLK. This clock is used + * by many peripherals. It should be enabled at an early system initialization + * stage to ensure the peripherals can select and use it. + * + * @param base Oscillator register base address + * @param enable enable/disable the clock + */ +static inline void OSC_HAL_SetExternalRefClkCmd(OSC_Type * base, bool enable) +{ + OSC_BWR_CR_ERCLKEN(base, enable); +} + +/*! + * @brief Gets the external reference clock enable setting for the oscillator. + * + * This function gets the external reference clock output enable setting + * for the oscillator , OSCERCLK. This clock is used + * by many peripherals. It should be enabled at an early system initialization + * stage to ensure the peripherals could select and use it. + * + * @param base Oscillator register base address + * @return Clock enable/disable setting + */ +static inline bool OSC_HAL_GetExternalRefClkCmd(OSC_Type * base) +{ + return (bool)OSC_BRD_CR_ERCLKEN(base); +} + +/*! + * @brief Enables/disables the external reference clock in stop mode. + * + * This function enables/disables the external reference clock (OSCERCLK) when an + * MCU enters the stop mode. + * + * @param base Oscillator register base address + * @param enable enable/disable setting + */ +static inline void OSC_HAL_SetExternalRefClkInStopModeCmd(OSC_Type * base, bool enable) +{ + OSC_BWR_CR_EREFSTEN(base, enable); +} + +/*! + * @brief Sets the capacitor configuration for the oscillator. + * + * This function sets the specified capacitors configuration for the + * oscillator. This should be done in the early system level initialization function call + * based on the system configuration. + * + * @param base Oscillator register base address + * @param bitMask Bit mask for the capacitor load option. + * + * Example: + @code + // To enable only 2 pF and 8 pF capacitor load, please use like this. + OSC_HAL_SetCapacitor(OSC, kOscCapacitor2p | kOscCapacitor8p); + @endcode + */ +void OSC_HAL_SetCapacitor(OSC_Type * base, uint32_t bitMask); + +#if FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER +/*! + * @brief Sets the external reference clock divider. + * + * This function sets the divider for the external reference clock. + * + * @param base Oscillator register base address + * @param divider Divider settings + */ +static inline void OSC_HAL_SetExternalRefClkDiv(OSC_Type * base, uint32_t divider) +{ + OSC_BWR_DIV_ERPS(base, divider); +} + +/*! + * @brief Gets the external reference clock divider. + * + * This function gets the divider for the external reference clock. + * + * @param base Oscillator register base address + * @return Divider settings + */ +static inline uint32_t OSC_HAL_GetExternalRefClkDiv(OSC_Type * base) +{ + return OSC_BRD_DIV_ERPS(base); +} +#endif + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif +#endif /* __FSL_OSC_HAL_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_pcc_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_pcc_hal.h new file mode 100755 index 0000000..5369226 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_pcc_hal.h @@ -0,0 +1,339 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_PCC_HAL_H__ +#define __FSL_PCC_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> +#include "fsl_device_registers.h" + +/*! + * @addtogroup pcc_hal + * @{ + */ + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/* Peripheral index in PCC0. */ +#define PCC0_INDEX_DMA0 ( 0x0020U >> 2 ) +#define PCC0_INDEX_XRDC0 ( 0x0050U >> 2 ) +#define PCC0_INDEX_SEMA0 ( 0x006CU >> 2 ) +#define PCC0_INDEX_FLASH0 ( 0x0080U >> 2 ) +#define PCC0_INDEX_DMAMUX0 ( 0x0084U >> 2 ) +#define PCC0_INDEX_MU0_A ( 0x008CU >> 2 ) +#define PCC0_INDEX_INTMUX0 ( 0x0090U >> 2 ) +#define PCC0_INDEX_TPM2 ( 0x00B8U >> 2 ) +#define PCC0_INDEX_PIT0 ( 0x00C0U >> 2 ) +#define PCC0_INDEX_LPTMR0 ( 0x00D0U >> 2 ) +#define PCC0_INDEX_RTC0 ( 0x00E0U >> 2 ) +#define PCC0_INDEX_LPSPI2 ( 0x00F8U >> 2 ) +#define PCC0_INDEX_LPI2C2 ( 0x0108U >> 2 ) +#define PCC0_INDEX_LPUART2 ( 0x0118U >> 2 ) +#define PCC0_INDEX_SAI0 ( 0x0130U >> 2 ) +#define PCC0_INDEX_EVMSIM0 ( 0x0138U >> 2 ) +#define PCC0_INDEX_USBFS0 ( 0x0154U >> 2 ) +#define PCC0_INDEX_PORTA ( 0x0168U >> 2 ) +#define PCC0_INDEX_PORTB ( 0x016CU >> 2 ) +#define PCC0_INDEX_PORTC ( 0x0170U >> 2 ) +#define PCC0_INDEX_PORTD ( 0x0174U >> 2 ) +#define PCC0_INDEX_PORTE ( 0x0178U >> 2 ) +#define PCC0_INDEX_TSI0 ( 0x0188U >> 2 ) +#define PCC0_INDEX_ADC0 ( 0x0198U >> 2 ) +#define PCC0_INDEX_DAC0 ( 0x01A8U >> 2 ) +#define PCC0_INDEX_CMP0 ( 0x01B8U >> 2 ) +#define PCC0_INDEX_VREF0 ( 0x01C8U >> 2 ) +#define PCC0_INDEX_ATX0 ( 0x01CCU >> 2 ) +#define PCC0_INDEX_CRC0 ( 0x01E0U >> 2 ) + +/* Peripheral index in PCC1. */ +#define PCC1_INDEX_DMA1 ( 0x0020U >> 2 ) +#define PCC1_INDEX_SEMA1 ( 0x006CU >> 2 ) +#define PCC1_INDEX_DMAMUX1 ( 0x0084U >> 2 ) +#define PCC1_INDEX_MU0_B ( 0x008CU >> 2 ) +#define PCC1_INDEX_INTMUX1 ( 0x0090U >> 2 ) +#define PCC1_INDEX_TRNG0 ( 0x0094U >> 2 ) +#define PCC1_INDEX_TPM0 ( 0x00B0U >> 2 ) +#define PCC1_INDEX_TPM1 ( 0x00B4U >> 2 ) +#define PCC1_INDEX_PIT1 ( 0x00C4U >> 2 ) +#define PCC1_INDEX_LPTMR1 ( 0x00D4U >> 2 ) +#define PCC1_INDEX_LPSPI0 ( 0x00F0U >> 2 ) +#define PCC1_INDEX_LPSPI1 ( 0x00F4U >> 2 ) +#define PCC1_INDEX_LPI2C0 ( 0x0100U >> 2 ) +#define PCC1_INDEX_LPI2C1 ( 0x0104U >> 2 ) +#define PCC1_INDEX_LPUART0 ( 0x0110U >> 2 ) +#define PCC1_INDEX_LPUART1 ( 0x0114U >> 2 ) +#define PCC1_INDEX_FLEXIO0 ( 0x0128U >> 2 ) +#define PCC1_INDEX_BBS0_PORT ( 0x0180U >> 2 ) +#define PCC1_INDEX_CMP1 ( 0x01BCU >> 2 ) + +/*! + * @brief Clock source for peripherals that support various clock selections. + */ +typedef enum _clock_ip_src +{ + kClockIpSrcNone = 0U, /*!< Clock is off or test clock is enabled. */ + kClockIpSrcSysOsc = 1U, /*!< System Oscillator. */ + kClockIpSrcSIrc = 2U, /*!< Slow IRC (max is 8MHz). */ + kClockIpSrcFIrc = 3U, /*!< Fast IRC (max is 48MHz). */ + kClockIpSrcRtcOsc = 4U, /*!< RTC OSC. */ + kClockIpSrcSysFll = 5U, /*!< System FLL DIV3 or DIV2. */ + kClockIpSrcSysPll = 6U, /*!< System PLL DIV3 or DIV2. */ + kClockIpSrcPerPll = 7U, /*!< Perpheral PLL DIV3 or DIV2. */ + kClockIpSrcMax = 8U, /*!< Max value. */ +} clock_ip_src_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Enable clock for some IP module. + * + * This function enable clock for some specific IP module. + * For example, to enable the DMA0 clock, use like this: + * @code + CLOCK_HAL_EnableClock(PCC0_BASE, 8); + * @endcode + * or use macro like this: + * @code + CLOCK_HAL_EnableClock(PCC0_BASE, PCC0_INDEX_DMA0); + * @endcode + * + * @param base Register base address for the PCC instance. + * @param index The control register index for the IP module in PCC. + */ +static inline void CLOCK_HAL_EnableClock(PCC_Type * base, uint8_t index) +{ + /* Make sure this IP is present. */ + assert(PCC_BRD_CLKCFGn_EN(base, index)); + + PCC_BWR_CLKCFGn_CGC(base, index, 1U); +} + +/*! + * @brief Disable clock for some IP module. + * + * This function disable clock for some specific IP module. + * For example, to disable the DMA0 clock, use like this: + * @code + CLOCK_HAL_DisableClock(PCC0_BASE, 8); + * @endcode + * or use macro like this: + * @code + CLOCK_HAL_DisableClock(PCC0_BASE, PCC0_INDEX_DMA0); + * @endcode + * + * @param base Register base address for the PCC instance. + * @param index The control register index for the IP module in PCC. + */ +static inline void CLOCK_HAL_DisableClock(PCC_Type * base, uint8_t index) +{ + /* Make sure this IP is present. */ + assert(PCC_BRD_CLKCFGn_EN(base, index)); + + PCC_BWR_CLKCFGn_CGC(base, index, 0U); +} + +/*! + * @brief Gets the clock gate status on current core for some IP module. + * + * This function gets the clock gate status on current core for some IP module. + * For example, to get the DMA0 clock gate status, use like this: + * @code + CLOCK_HAL_GetGateCmd(PCC0_BASE, 8); + * @endcode + * or use macro like this: + * @code + CLOCK_HAL_GetGateCmd(PCC0_BASE, PCC0_INDEX_DMA0); + * @endcode + * + * @param base Register base address for the PCC instance. + * @param index The control register index for the IP module in PCC. + * @return state true - ungated(Enabled), false - gated (Disabled) + */ +static inline bool CLOCK_HAL_GetGateCmd(PCC_Type * base, uint8_t index) +{ + /* Make sure this IP is present. */ + assert(PCC_BRD_CLKCFGn_EN(base, index)); + + return (bool)PCC_BRD_CLKCFGn_CGC(base, index); +} + +/*! + * @brief Gets the clock gate status on other core for some IP module. + * + * This function gets the clock gate status on other core for some IP module. + * For example, to get the DMA0 clock gate status, use like this: + * @code + CLOCK_HAL_GetGateCmdOnOtherCore(PCC0_BASE, 8); + * @endcode + * or use macro like this: + * @code + CLOCK_HAL_GetGateCmdOnOtherCore(PCC0_BASE, PCC0_INDEX_DMA0); + * @endcode + * + * @param base Register base address for the PCC instance. + * @param index The control register index for the IP module in PCC. + * @return state true - ungated(Enabled), false - gated (Disabled) + */ +static inline bool CLOCK_HAL_GetGateCmdOnOtherCore(PCC_Type * base, uint8_t index) +{ + /* Make sure this IP is present. */ + assert(PCC_BRD_CLKCFGn_EN(base, index)); + + return (bool)PCC_BRD_CLKCFGn_CGC_ALT(base, index); +} + +/*! + * @brief Sets the clock source for some IP module. + * + * This function sets the clock source for some IP module. + * For example, to set the clock source for USBFS0 to OSCCLK, use like this: + * @code + CLOCK_HAL_SetIpSrc(PCC0_BASE, 38, kClockIpSrcSysOsc); + * @endcode + * or use macro like this: + * @code + CLOCK_HAL_SetIpSrc(PCC0_BASE, PCC0_INDEX_USBFS0, kClockIpSrcSysOsc); + * @endcode + * + * @param base Register base address for the PCC instance. + * @param index The control register index for the IP module in PCC. + * @param src The clock source to set. + * + * @note Not all peripherals support various clock sources, please check the + * reference manual for more details. + */ +static inline void CLOCK_HAL_SetIpSrc(PCC_Type * base, + uint8_t index, + clock_ip_src_t src) +{ + /* Make sure this IP is present. */ + assert(PCC_BRD_CLKCFGn_EN(base, index)); + + assert(src < kClockIpSrcMax); + + PCC_BWR_CLKCFGn_PCS(base, index, src); +} + +/*! + * @brief Gets the clock source for some IP module. + * + * This function gets the clock source for some IP module. + * For example, to get the clock source for USBFS0 to OSCCLK, use like this: + * @code + CLOCK_HAL_GetIpSrc(PCC0_BASE, 38); + * @endcode + * or use macro like this: + * @code + CLOCK_HAL_GetIpSrc(PCC0_BASE, PCC0_INDEX_USBFS0); + * @endcode + * + * @param base Register base address for the PCC instance. + * @param index The control register index for the IP module in PCC. + * @return Current clock source for this module. + * + * @note Not all peripherals support various clock sources, please check the + * reference manual for more details. + */ +static inline clock_ip_src_t CLOCK_HAL_GetIpSrc(PCC_Type * base, + uint8_t index) +{ + /* Make sure this IP is present. */ + assert(PCC_BRD_CLKCFGn_EN(base, index)); + + return (clock_ip_src_t)PCC_BRD_CLKCFGn_PCS(base, index); +} + +/*! + * @brief Sets the clock divider for some IP module. + * + * This function sets the clock divider for some IP module. + * + * @param base Register base address for the PCC instance. + * @param index The control register index for the IP module in PCC. + * @param divider Clock divider for this module. + * + * @note Not all peripherals support this feature, please check the + * reference manual for more details. + */ +static inline void CLOCK_HAL_SetIpDiv(PCC_Type * base, + uint8_t index, + uint32_t divider) +{ + /* Make sure this IP is present. */ + assert(PCC_BRD_CLKCFGn_EN(base, index)); + + PCC_BWR_CLKCFGn_PCD(base, index, divider); +} + + +/*! + * @brief Gets the clock divider for some IP module. + * + * This function gets the clock divider for some IP module. + * + * @param base Register base address for the PCC instance. + * @param index The control register index for the IP module in PCC. + * @return Current clock divider for this module. + * + * @note Not all peripherals support this feature, please check the + * reference manual for more details. + */ +static inline uint32_t CLOCK_HAL_GetIpDiv(PCC_Type * base, + uint8_t index) +{ + /* Make sure this IP is present. */ + assert(PCC_BRD_CLKCFGn_EN(base, index)); + + return (uint32_t)PCC_BRD_CLKCFGn_PCD(base, index); +} + +#if defined(__cplusplus) +extern } +#endif + +/*! + * @} + */ + +#endif /* __FSL_PCC_HAL_H__ */ + +/****************************************************************************** + * EOF + *****************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_pdb_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_pdb_hal.h new file mode 100755 index 0000000..ae3a5ce --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_pdb_hal.h @@ -0,0 +1,511 @@ +/* + * Copyright (c) 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_PDB_HAL_H__ +#define __FSL_PDB_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> +#include <assert.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_PDB_COUNT + +/*! + * @addtogroup pdb_hal + * @{ + */ + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/*! + * @brief PDB status return codes. + */ +typedef enum _pdb_status +{ + kStatus_PDB_Success = 0U, /*!< Success. */ + kStatus_PDB_InvalidArgument = 1U, /*!< Invalid argument existed. */ + kStatus_PDB_Failed = 2U /*!< Execution failed. */ +} pdb_status_t; + +/*! + * @brief Defines the type of value load mode for the PDB module. + * + * Some timing related registers, such as the MOD, IDLY, CHnDLYm, INTx and POyDLY, + * buffer the setting values. Only the load operation is triggered. + * The setting value is loaded from a buffer and takes effect. There are + * four loading modes to fit different applications. + */ +typedef enum _pdb_load_value_mode +{ + kPdbLoadValueImmediately = 0U, + /*!< Loaded immediately after load operation. @internal gui name="Immediately" */ + kPdbLoadValueAtModuloCounter = 1U, + /*!< Loaded when counter hits the modulo after load operation. @internal gui name="Modulo counter" */ + kPdbLoadValueAtNextTrigger = 2U, + /*!< Loaded when detecting an input trigger after load operation. @internal gui name="Next trigger" */ + kPdbLoadValueAtModuloCounterOrNextTrigger = 3U + /*!< Loaded when counter hits the modulo or detecting an input trigger after load operation. @internal gui name="Modulo counter/Next trigger" */ +} pdb_load_value_mode_t; + +/*! + * @brief Defines the type of prescaler divider for the PDB counter clock. + */ +typedef enum _pdb_clk_prescaler_div +{ + kPdbClkPreDivBy1 = 0U, /*!< Counting divided by multiplication factor selected by MULT. @internal gui name="1" */ + kPdbClkPreDivBy2 = 1U, /*!< Counting divided by multiplication factor selected by 2 times ofMULT. @internal gui name="2" */ + kPdbClkPreDivBy4 = 2U, /*!< Counting divided by multiplication factor selected by 4 times ofMULT. @internal gui name="4" */ + kPdbClkPreDivBy8 = 3U, /*!< Counting divided by multiplication factor selected by 8 times ofMULT. @internal gui name="8" */ + kPdbClkPreDivBy16 = 4U, /*!< Counting divided by multiplication factor selected by 16 times ofMULT. @internal gui name="16" */ + kPdbClkPreDivBy32 = 5U, /*!< Counting divided by multiplication factor selected by 32 times ofMULT. @internal gui name="32" */ + kPdbClkPreDivBy64 = 6U, /*!< Counting divided by multiplication factor selected by 64 times ofMULT. @internal gui name="64" */ + kPdbClkPreDivBy128 = 7U, /*!< Counting divided by multiplication factor selected by 128 times ofMULT. @internal gui name="128" */ +} pdb_clk_prescaler_div_t; + +/*! + * @brief Defines the type of trigger source mode for the PDB. + * + * Selects the trigger input source for the PDB. The trigger input source can + * be internal or external (EXTRG pin), or the software trigger. + */ +typedef enum _pdb_trigger_src +{ + kPdbTrigger0 = 0U, /*!< Select trigger-In 0. @internal gui name="External trigger" */ + kPdbTrigger1 = 1U, /*!< Select trigger-In 1. @internal gui name="Trigger 1" */ + kPdbTrigger2 = 2U, /*!< Select trigger-In 2. @internal gui name="Trigger 2" */ + kPdbTrigger3 = 3U, /*!< Select trigger-In 3. @internal gui name="Trigger 3" */ + kPdbTrigger4 = 4U, /*!< Select trigger-In 4. @internal gui name="Trigger 4" */ + kPdbTrigger5 = 5U, /*!< Select trigger-In 5. @internal gui name="Trigger 5" */ + kPdbTrigger6 = 6U, /*!< Select trigger-In 6. @internal gui name="Trigger 6" */ + kPdbTrigger7 = 7U, /*!< Select trigger-In 7. @internal gui name="Trigger 7" */ + kPdbTrigger8 = 8U, /*!< Select trigger-In 8. @internal gui name="Trigger 8" */ + kPdbTrigger9 = 9U, /*!< Select trigger-In 8. @internal gui name="Trigger 9" */ + kPdbTrigger10 = 10U, /*!< Select trigger-In 10. @internal gui name="Trigger 10" */ + kPdbTrigger11 = 11U, /*!< Select trigger-In 11. @internal gui name="Trigger 11" */ + kPdbTrigger12 = 12U, /*!< Select trigger-In 12. @internal gui name="Trigger 12" */ + kPdbTrigger13 = 13U, /*!< Select trigger-In 13. @internal gui name="Trigger 13" */ + kPdbTrigger14 = 14U, /*!< Select trigger-In 14. @internal gui name="Trigger 14" */ + kPdbSoftTrigger = 15U, /*!< Select software trigger. @internal gui name="Software trigger" */ +} pdb_trigger_src_t; + +/*! + * @brief Defines the type of the multiplication source mode for PDB. + * + * Selects the multiplication factor of the prescaler divider for the PDB counter clock. + */ +typedef enum _pdb_clk_prescaler_mult_factor +{ + kPdbClkPreMultFactorAs1 = 0U, /*!< Multiplication factor is 1. @internal gui name="1" */ + kPdbClkPreMultFactorAs10 = 1U, /*!< Multiplication factor is 10. @internal gui name="10" */ + kPdbClkPreMultFactorAs20 = 2U, /*!< Multiplication factor is 20. @internal gui name="20" */ + kPdbClkPreMultFactorAs40 = 3U /*!< Multiplication factor is 40. @internal gui name="40" */ +} pdb_clk_prescaler_mult_factor_t; + +/*! + * @brief Defines the type of structure for basic timer in PDB. + * + * @internal gui name="Basic configuration" id="pdbCfg" + */ +typedef struct PdbTimerConfig +{ + pdb_load_value_mode_t loadValueMode; /*!< Select the load mode. @internal gui name="Load mode" id="LoadMode" */ + bool seqErrIntEnable; /*!< Enable PDB Sequence Error Interrupt. @internal gui name="Sequence error interrupt" id="SequenceErrorInterrupt" */ + pdb_clk_prescaler_div_t clkPreDiv; /*!< Select the prescaler divider. @internal gui name="Divider" id="Divider" */ + pdb_clk_prescaler_mult_factor_t clkPreMultFactor; /*!< Select multiplication factor for prescaler. @internal gui name="Multiplier" id="Multiplier" */ + pdb_trigger_src_t triggerInput; /*!< Select the trigger input source. @internal gui name="Trigger" id="Trigger" */ + bool continuousModeEnable; /*!< Enable the continuous mode. @internal gui name="Continuous mode" id="ContinuousMode" */ + bool dmaEnable; /*!< Enable the dma for timer. @internal gui name="DMA" id="DMA" */ + bool intEnable; /*!< Enable the interrupt for timer. @internal gui name="Interrupt" id="Interrupt" */ +} pdb_timer_config_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Resets the PDB registers to a known state. + * + * This function resets the PDB registers to a known state. This state is + * defined in a reference manual and is power on reset value. + * + * @param base Register base address for the module. + */ +void PDB_HAL_Init(PDB_Type * base); + +/*! + * @brief Configure the PDB timer. + * + * This function configure the PDB's basic timer. + * + * @param base Register base address for the module. + * @param configPtr Pointer to configuration structure, see to "pdb_timer_config_t". + * @return Execution status. + */ +pdb_status_t PDB_HAL_ConfigTimer(PDB_Type * base, const pdb_timer_config_t *configPtr); + +/*! + * @brief Triggers the DAC by software if enabled. + * + * If enabled, this function triggers the DAC by using software. + * + * @param base Register base address for the module. + */ +static inline void PDB_HAL_SetSoftTriggerCmd(PDB_Type * base) +{ + PDB_BWR_SC_SWTRIG(base, 1U); +} + +/*! + * @brief Switches on to enable the PDB module. + * + * This function switches on to enable the PDB module. + * + * @param base Register base address for the module. + */ +static inline void PDB_HAL_Enable(PDB_Type * base) +{ + PDB_BWR_SC_PDBEN(base, 1U); +} +/*! + * @brief Switches to disable the PDB module. + * + * This function switches to disable the PDB module. + * + * @param base Register base address for the module. + */ +static inline void PDB_HAL_Disable(PDB_Type * base) +{ + PDB_BWR_SC_PDBEN(base, 0U); +} + +/*! + * @brief Gets the PDB delay interrupt flag. + * + * This function gets the PDB delay interrupt flag. + * + * @param base Register base address for the module. + * @return Flat status, true if the flag is set. + */ +static inline bool PDB_HAL_GetTimerIntFlag(PDB_Type * base) +{ + return (1U == PDB_BRD_SC_PDBIF(base)); +} + +/*! + * @brief Clears the PDB delay interrupt flag. + * + * This function clears PDB delay interrupt flag. + * + * @param base Register base address for the module. + * @return Flat status, true if the flag is set. + */ +static inline void PDB_HAL_ClearTimerIntFlag(PDB_Type * base) +{ + PDB_BWR_SC_PDBIF(base, 0U); +} + +/*! + * @brief Loads the delay registers value for the PDB module. + * + * This function sets the LDOK bit and loads the delay registers value. + * Writing one to this bit updates the internal registers MOD, IDLY, CHnDLYm, + * DACINTx, and POyDLY with the values written to their buffers. The MOD, IDLY, + * CHnDLYm, DACINTx, and POyDLY take effect according to the load mode settings. + * + * After one is written to the LDOK bit, the values in the buffers of above mentioned registers + * are not effective and cannot be written until the values in the + * buffers are loaded into their internal registers. + * The LDOK can be written only when the the PDB is enabled or as alone with it. It is + * automatically cleared either when the values in the buffers are loaded into the + * internal registers or when the PDB is disabled. + * + * @param base Register base address for the module. + */ +static inline void PDB_HAL_SetLoadValuesCmd(PDB_Type * base) +{ + PDB_BWR_SC_LDOK(base, 1U); +} + +/*! + * @brief Sets the modulus value for the PDB module. + * + * This function sets the modulus value for the PDB module. + * When the counter reaches the setting value, it is automatically reset to zero. + * When in continuous mode, the counter begins to increase + * again. + * + * @param base Register base address for the module. + * @param value The setting value of upper limit for PDB counter. + */ +static inline void PDB_HAL_SetTimerModulusValue(PDB_Type * base, uint32_t value) +{ + PDB_BWR_MOD_MOD(base, value); +} + +/*! + * @brief Gets the PDB counter value of PDB timer. + * + * This function gets the PDB counter value of PDB timer. + * + * @param base Register base address for the module. + * @return The current counter value. + */ +static inline uint32_t PDB_HAL_GetTimerValue(PDB_Type * base) +{ + return PDB_BRD_CNT_CNT(base); +} + +/*! + * @brief Sets the interrupt delay milestone of the PDB counter. + * + * This function sets the interrupt delay milestone of the PDB counter. + * If enabled, a PDB interrupt is generated when the counter is equal to the + * setting value. + * + * @param base Register base address for the module. + * @param value The setting value for interrupt delay milestone of PDB counter. + */ +static inline void PDB_HAL_SetValueForTimerInterrupt(PDB_Type * base, uint32_t value) +{ + PDB_BWR_IDLY_IDLY(base, value); +} + +/*! + * @brief Switches to enable the pre-trigger back-to-back mode. + * + * This function switches to enable the pre-trigger back-to-back mode. + * + * @param base Register base address for the module. + * @param chn ADC instance index for trigger. + * @param preChnMask ADC channel group index mask for trigger. + * @param enable Switcher to assert the feature. + */ +void PDB_HAL_SetAdcPreTriggerBackToBackEnable(PDB_Type * base, uint32_t chn, uint32_t preChnMask, bool enable); + +/*! + * @brief Switches to enable the pre-trigger output. + * + * This function switches to enable pre-trigger output. + * + * @param base Register base address for the module. + * @param chn ADC instance index for trigger. + * @param preChnMask ADC channel group index mask for trigger. + * @param enable Switcher to assert the feature. + */ +void PDB_HAL_SetAdcPreTriggerOutputEnable(PDB_Type * base, uint32_t chn, uint32_t preChnMask, bool enable); + +/*! + * @brief Switches to enable the pre-trigger. + * + * This function switches to enable the pre-trigger. + * + * @param base Register base address for the module. + * @param chn ADC instance index for trigger. + * @param preChnMask ADC channel group index mask for trigger. + * @param enable Switcher to assert the feature. + */ +void PDB_HAL_SetAdcPreTriggerEnable(PDB_Type * base, uint32_t chn, uint32_t preChnMask, bool enable); + +/*! + * @brief Gets the flag which indicates whether the PDB counter has reached the pre-trigger delay value. + * + * This function gets the flag which indicates the PDB counter has reached the + * pre-trigger delay value. + * + * @param base Register base address for the module. + * @param chn ADC instance index for trigger. + * @param preChnMask ADC channel group index mask for trigger. + * @return Flag mask. Indicated bit would be 1 if the event is asserted. + */ +static inline uint32_t PDB_HAL_GetAdcPreTriggerFlags(PDB_Type * base, uint32_t chn, uint32_t preChnMask) +{ + assert(chn < PDB_C1_COUNT); + return (preChnMask & PDB_BRD_S_CF(base, chn) ); +} + +/*! + * @brief Clears the flag which indicates that the PDB counter has reached the pre-trigger delay value. + * + * This function clears the flag which indicates that the PDB counter has reached the + * pre-trigger delay value. + * + * @param base Register base address for the module. + * @param chn ADC instance index for trigger. + * @param preChnMask ADC channel group index mask for trigger. + */ +void PDB_HAL_ClearAdcPreTriggerFlags(PDB_Type * base, uint32_t chn, uint32_t preChnMask); + +/*! + * @brief Gets the flag which indicates whether a sequence error is detected. + * + * This function gets the flag which indicates whether a sequence error is detected. + * + * @param base Register base address for the module. + * @param chn ADC instance index for trigger. + * @param preChnMask ADC channel group index mask for trigger. + * @return Flag mask. Indicated bit would be 1 if the event is asserted. + */ +static inline uint32_t PDB_HAL_GetAdcPreTriggerSeqErrFlags(PDB_Type * base, uint32_t chn, uint32_t preChnMask) +{ + assert(chn < PDB_C1_COUNT); + return ( preChnMask & PDB_BRD_S_ERR(base, chn) ); +} + +/*! + * @brief Clears the flag which indicates that a sequence error has been detected. + * + * This function clears the flag which indicates that the sequence error has been detected. + * + * @param base Register base address for the module. + * @param chn ADC instance index for trigger. + * @param preChnMask ADC channel group index mask for trigger. + */ +void PDB_HAL_ClearAdcPreTriggerSeqErrFlags(PDB_Type * base, uint32_t chn, uint32_t preChnMask); + +/*! + * @brief Sets the pre-trigger delay value. + * + * This function sets the pre-trigger delay value. + * + * @param base Register base address for the module. + * @param chn ADC instance index for trigger. + * @param preChn ADC channel group index for trigger. + * @param value Setting value for pre-trigger's delay value. + */ +void PDB_HAL_SetAdcPreTriggerDelayValue(PDB_Type * base, uint32_t chn, uint32_t preChn, uint32_t value); + +/*! + * @brief Switches to enable the DAC external trigger input. + * + * This function switches to enable the DAC external trigger input. + * + * @param base Register base address for the module. + * @param dacChn DAC instance index for trigger. + * @param value Setting value for pre-trigger's delay value. + * @param enable Switcher to assert the feature. + */ +static inline void PDB_HAL_SetDacExtTriggerInputEnable(PDB_Type * base, uint32_t dacChn, bool enable) +{ + assert(dacChn < PDB_INTC_COUNT); + PDB_BWR_INTC_EXT(base, dacChn, (enable ? 1U: 0U) ); +} + +/*! + * @brief Switches to enable the DAC external trigger input. + * + * This function switches to enable the DAC external trigger input. + * + * @param base Register base address for the module. + * @param dacChn DAC instance index for trigger. + * @param enable Switcher to assert the feature. + */ +static inline void PDB_HAL_SetDacIntervalTriggerEnable(PDB_Type * base, uint32_t dacChn, bool enable) +{ + assert(dacChn < PDB_INTC_COUNT); + PDB_BWR_INTC_TOE(base, dacChn, (enable ? 1U: 0U) ); +} + +/*! + * @brief Sets the interval value for the DAC trigger. + * + * This function sets the interval value for the DAC trigger. + * + * @param base Register base address for the module. + * @param dacChn DAC instance index for trigger. + * @param value Setting value for DAC trigger interval. + */ +static inline void PDB_HAL_SetDacIntervalValue(PDB_Type * base, uint32_t dacChn, uint32_t value) +{ + assert(dacChn < PDB_INT_COUNT); + PDB_BWR_INT_INT(base, dacChn, value); +} + +/*! + * @brief Switches to enable the pulse-out trigger. + * + * This function switches to enable the pulse-out trigger. + * + * @param base Register base address for the module. + * @param pulseChnMask Pulse-out channle index mask for trigger. + * @param enable Switcher to assert the feature. + */ +void PDB_HAL_SetCmpPulseOutEnable(PDB_Type * base, uint32_t pulseChnMask, bool enable); + +/*! + * @brief Sets the counter delay value for the pulse-out goes high. + * + * This function sets the counter delay value for the pulse-out goes high. + * + * @param base Register base address for the module. + * @param pulseChn Pulse-out channel index for trigger. + * @param value Setting value for PDB delay . + */ +static inline void PDB_HAL_SetCmpPulseOutDelayForHigh(PDB_Type * base, uint32_t pulseChn, uint32_t value) +{ + assert(pulseChn < PDB_PODLY_COUNT); + PDB_BWR_PODLY_DLY1(base, pulseChn, value); +} + +/*! + * @brief Sets the counter delay value for the pulse-out goes low. + * + * This function sets the counter delay value for the pulse-out goes low. + * + * @param base Register base address for the module. + * @param pulseChn Pulse-out channel index for trigger. + * @param value Setting value for PDB delay . + */ +static inline void PDB_HAL_SetCmpPulseOutDelayForLow(PDB_Type * base, uint32_t pulseChn, uint32_t value) +{ + assert(pulseChn < PDB_PODLY_COUNT); + PDB_BWR_PODLY_DLY2(base, pulseChn, value); +} + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif +#endif /* __FSL_PDB_HAL_H__ */ + +/****************************************************************************** + * EOF + *****************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_pit_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_pit_hal.h new file mode 100755 index 0000000..b601ad0 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_pit_hal.h @@ -0,0 +1,346 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_PIT_HAL_H__ +#define __FSL_PIT_HAL_H__ + +#include <assert.h> +#include <stdint.h> +#include <stdbool.h> +#include "fsl_device_registers.h" + +/*! + * @addtogroup pit_hal + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Error codes for PIT driver. */ +typedef enum _pit_status +{ + kStatus_PIT_Success = 0x00U, + kStatus_PIT_Fail = 0x01U +} pit_status_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Enables the PIT module. + * + * This function enables the PIT timer clock (Note: this function does not un-gate + * the system clock gating control). It should be called before any other timer + * related setup. + * + * @param base Base address for current PIT instance. + */ +static inline void PIT_HAL_Enable(PIT_Type * base) +{ + PIT_BWR_MCR_MDIS(base, 0U); +} + +/*! + * @brief Disables the PIT module. + * + * This function disables all PIT timer clocks(Note: it does not affect the + * SIM clock gating control). + * + * @param base Base address for current PIT instance. + */ +static inline void PIT_HAL_Disable(PIT_Type * base) +{ + PIT_BWR_MCR_MDIS(base, 1U); +} + +/*! + * @brief Configures the timers to continue running or to stop in debug mode. + * + * In debug mode, the timers may or may not be frozen, based on the configuration of + * this function. This is intended to aid software development, allowing the developer + * to halt the processor, investigate the current state of the system (for example, + * the timer values), and continue the operation. + * + * @param base Base address for current PIT instance. + * @param timerRun Timers run or stop in debug mode. + * - true: Timers continue to run in debug mode. + * - false: Timers stop in debug mode. + */ +static inline void PIT_HAL_SetTimerRunInDebugCmd(PIT_Type * base, bool timerRun) +{ + PIT_BWR_MCR_FRZ(base, !timerRun); +} + +#if FSL_FEATURE_PIT_HAS_CHAIN_MODE +/*! + * @brief Enables or disables the timer chain with the previous timer. + * + * When a timer has a chain mode enabled, it only counts after the previous + * timer has expired. If the timer n-1 has counted down to 0, counter n + * decrements the value by one. This allows the developers to chain timers together + * and form a longer timer. The first timer (timer 0) cannot be chained to any + * other timer. + * + * @param base Base address for current PIT instance. + * @param channel Timer channel number which is chained with the previous timer. + * @param enable Enable or disable chain. + * - true: Current timer is chained with the previous timer. + * - false: Timer doesn't chain with other timers. + */ +static inline void PIT_HAL_SetTimerChainCmd(PIT_Type * base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); + PIT_BWR_TCTRL_CHN(base, channel, enable); +} + +#endif /* FSL_FEATURE_PIT_HAS_CHAIN_MODE*/ + +/* @} */ + +/*! + * @name Timer Start and Stop + * @{ + */ + +/*! + * @brief Starts the timer counting. + * + * After calling this function, timers load the start value as specified by the function + * PIT_HAL_SetTimerPeriodByCount(PIT_Type * base, uint32_t channel, uint32_t count), count down to + * 0, and load the respective start value again. Each time a timer reaches 0, + * it generates a trigger pulse and sets the time-out interrupt flag. + * + * @param base Base address for current PIT instance. + * @param channel Timer channel number + */ +static inline void PIT_HAL_StartTimer(PIT_Type * base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); + PIT_BWR_TCTRL_TEN(base, channel, 1U); +} + +/*! + * @brief Stops the timer from counting. + * + * This function stops every timer from counting. Timers reload their periods + * respectively after they call the PIT_HAL_StartTimer the next time. + * + * @param base Base address for current PIT instance. + * @param channel Timer channel number + */ +static inline void PIT_HAL_StopTimer(PIT_Type * base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); + PIT_BWR_TCTRL_TEN(base, channel, 0U); +} + +/*! + * @brief Checks to see whether the current timer is started or not. + * + * @param base Base address for current PIT instance. + * @param channel Timer channel number + * @return Current timer running status + * -true: Current timer is running. + * -false: Current timer has stopped. + */ +static inline bool PIT_HAL_IsTimerRunning(PIT_Type * base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); + return PIT_BRD_TCTRL_TEN(base, channel); +} + +/* @} */ + +/*! + * @name Timer Period + * @{ + */ + +/*! + * @brief Sets the timer period in units of count. + * + * Timers begin counting from the value set by this function. + * The counter period of a running timer can be modified by first stopping + * the timer, setting a new load value, and starting the timer again. If + * timers are not restarted, the new value is loaded after the next trigger + * event. + * + * @param base Base address for current PIT instance. + * @param channel Timer channel number + * @param count Timer period in units of count + */ +static inline void PIT_HAL_SetTimerPeriodByCount(PIT_Type * base, uint32_t channel, uint32_t count) +{ + assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); + PIT_WR_LDVAL(base, channel, count); +} + +/*! + * @brief Returns the current timer period in units of count. + * + * @param base Base address for current PIT instance. + * @param channel Timer channel number + * @return Timer period in units of count + */ +static inline uint32_t PIT_HAL_GetTimerPeriodByCount(PIT_Type * base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); + return PIT_RD_LDVAL(base, channel); +} + +/*! + * @brief Reads the current timer counting value. + * + * This function returns the real-time timer counting value, in a range from 0 to a + * timer period. + * + * @param base Base address for current PIT instance. + * @param channel Timer channel number + * @return Current timer counting value + */ +static inline uint32_t PIT_HAL_ReadTimerCount(PIT_Type * base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); + return PIT_RD_CVAL(base, channel); +} + +#if FSL_FEATURE_PIT_HAS_LIFETIME_TIMER +/*! + * @brief Reads the current lifetime counter value. + * + * The lifetime timer is a 64-bit timer which chains timer 0 and timer 1 together. + * Timer 0 and 1 are chained by calling the PIT_HAL_SetTimerChainCmd + * before using this timer. The period of lifetime timer is equal to the "period of + * timer 0 * period of timer 1". For the 64-bit value, the higher 32-bit has + * the value of timer 1, and the lower 32-bit has the value of timer 0. + * + * @param base Base address for current PIT instance. + * @return Current lifetime timer value + */ +uint64_t PIT_HAL_ReadLifetimeTimerCount(PIT_Type * base); +#endif /*FSL_FEATURE_PIT_HAS_LIFETIME_TIMER*/ + +/* @} */ + +/*! + * @name Interrupt + * @{ + */ + +/*! + * @brief Enables or disables the timer interrupt. + * + * If enabled, an interrupt happens when a timeout event occurs + * (Note: NVIC should be called to enable pit interrupt in system level). + * + * @param base Base address for current PIT instance. + * @param channel Timer channel number + * @param enable Enable or disable interrupt. + * - true: Generate interrupt when timer counts to 0. + * - false: No interrupt is generated. + */ +static inline void PIT_HAL_SetIntCmd(PIT_Type * base, uint32_t channel, bool enable) +{ + assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); + PIT_BWR_TCTRL_TIE(base, channel, enable); +} + +/*! + * @brief Checks whether the timer interrupt is enabled or not. + * + * @param base Base address for current PIT instance. + * @param channel Timer channel number + * @return Status of enabled or disabled interrupt + * - true: Interrupt is enabled. + * - false: Interrupt is disabled. + */ +static inline bool PIT_HAL_GetIntCmd(PIT_Type * base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); + return PIT_BRD_TCTRL_TIE(base, channel); +} + +/*! + * @brief Clears the timer interrupt flag. + * + * This function clears the timer interrupt flag after a timeout event + * occurs. + * + * @param base Base address for current PIT instance. + * @param channel Timer channel number + */ +static inline void PIT_HAL_ClearIntFlag(PIT_Type * base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); + /* Write 1 will clear the flag. */ + PIT_WR_TFLG(base, channel, 1U); +} + +/*! + * @brief Reads the current timer timeout flag. + * + * Every time the timer counts to 0, this flag is set. + * + * @param base Base address for current PIT instance. + * @param channel Timer channel number + * @return Current status of the timeout flag + * - true: Timeout has occurred. + * - false: Timeout has not yet occurred. + */ +static inline bool PIT_HAL_IsIntPending(PIT_Type * base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_PIT_TIMER_COUNT); + return PIT_RD_TFLG(base, channel); +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __FSL_PIT_HAL_H__*/ +/******************************************************************************* +* EOF +*******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_pmc_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_pmc_hal.h new file mode 100755 index 0000000..5e0e036 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_pmc_hal.h @@ -0,0 +1,275 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#if !defined(__FSL_PMC_HAL_H__) +#define __FSL_PMC_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> +#include <assert.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_PMC_COUNT + +/*! @addtogroup pmc_hal*/ +/*! @{*/ + +/*! @file fsl_pmc_hal.h */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Low-Voltage Warning Voltage Select*/ +typedef enum _pmc_low_volt_warn_volt_select { + kPmcLowVoltWarnVoltLowTrip, /*!< Low trip point selected (VLVW = VLVW1)*/ + kPmcLowVoltWarnVoltMid1Trip, /*!< Mid 1 trip point selected (VLVW = VLVW2)*/ + kPmcLowVoltWarnVoltMid2Trip, /*!< Mid 2 trip point selected (VLVW = VLVW3)*/ + kPmcLowVoltWarnVoltHighTrip /*!< High trip point selected (VLVW = VLVW4)*/ +} pmc_low_volt_warn_volt_select_t; + +/*! @brief Low-Voltage Detect Voltage Select*/ +typedef enum _pmc_low_volt_detect_volt_select { + kPmcLowVoltDetectVoltLowTrip, /*!< Low trip point selected (V LVD = V LVDL )*/ + kPmcLowVoltDetectVoltHighTrip /*!< High trip point selected (V LVD = V LVDH )*/ +} pmc_low_volt_detect_volt_select_t; + +#if FSL_FEATURE_PMC_HAS_BGBDS +/*! @brief Bandgap Buffer Drive Select. */ +typedef enum _pmc_bandgap_buffer_drive_select { + kPmcBandgapBufferDriveLow, /*!< Low drive. */ + kPmcBandgapBufferDriveHigh /*!< High drive. */ +} pmc_bandgap_buffer_drive_select_t; +#endif + +/*! @brief Bandgap Buffer configuration. */ +typedef struct _pmc_bandgap_buffer_config +{ + bool enable; /*!< Enable bandgap buffer. */ +#if FSL_FEATURE_PMC_HAS_BGEN + bool enableInLowPower; /*!< Enable bandgap buffer in low power mode. */ +#endif +#if FSL_FEATURE_PMC_HAS_BGBDS + pmc_bandgap_buffer_drive_select_t drive; /*!< Bandgap buffer drive select. */ +#endif +} pmc_bandgap_buffer_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! @name Power Management Controller Control APIs*/ +/*@{*/ + +/*! + * @brief Configure the low voltage detect setting. + * + * This function configures the low voltage detect setting, including the trip + * point voltage setting, enable interrupt or not, enable MCU reset or not. + * + * @param base Base address for current PMC instance. + * @param enableInt Enable interrupt or not when low voltage detect. + * @param enableReset Enable MCU reset or not when low voltage detect. + * @param voltSelect Low voltage detect trip point voltage. + */ +static inline void PMC_HAL_LowVoltDetectConfig(PMC_Type * base, + bool enableInt, + bool enableReset, + pmc_low_volt_detect_volt_select_t voltSelect) +{ + PMC_WR_LVDSC1(base, PMC_LVDSC1_LVDV(voltSelect) | + PMC_LVDSC1_LVDIE(enableInt) | + PMC_LVDSC1_LVDRE(enableReset)); +} + +/*! + * @brief Low-Voltage Detect Acknowledge + * + * This function acknowledges the low voltage detection errors (write 1 to + * clear LVDF). + * + * @param base Base address for current PMC instance. + */ +static inline void PMC_HAL_SetLowVoltDetectAck(PMC_Type * base) +{ + PMC_BWR_LVDSC1_LVDACK(base, 1U); +} + +/*! + * @brief Low-Voltage Detect Flag Read + * + * This function reads the current LVDF status. If it returns 1, a low + * voltage event is detected. + * + * @param base Base address for current PMC instance. + * @return Current low voltage detect flag + * - true: Low-Voltage detected + * - false: Low-Voltage not detected + */ +static inline bool PMC_HAL_GetLowVoltDetectFlag(PMC_Type * base) +{ + return PMC_BRD_LVDSC1_LVDF(base); +} + +/*! + * @brief Configure the low voltage warning setting. + * + * This function configures the low voltage warning setting, including the trip + * point voltage setting and enable interrupt or not. + * + * @param base Base address for current PMC instance. + * @param enableInt Enable interrupt or not when low voltage detect. + * @param voltSelect Low voltage detect trip point voltage. + */ +static inline void PMC_HAL_LowVoltWarnConfig(PMC_Type * base, + bool enableInt, + pmc_low_volt_warn_volt_select_t voltSelect) +{ + PMC_WR_LVDSC2(base, PMC_LVDSC2_LVWV(voltSelect) | + PMC_LVDSC2_LVWIE(enableInt)); +} + +/*! + * @brief Low-Voltage Warning Acknowledge + * + * This function acknowledges the low voltage warning errors (write 1 to + * clear LVWF). + * + * @param base Base address for current PMC instance. + */ +static inline void PMC_HAL_SetLowVoltWarnAck(PMC_Type * base) +{ + PMC_BWR_LVDSC2_LVWACK(base, 1U); +} + +/*! + * @brief Low-Voltage Warning Flag Read + * + * This function polls the current LVWF status. When 1 is returned, it + * indicates a low-voltage warning event. LVWF is set when V Supply transitions + * below the trip point or after reset and V Supply is already below the V LVW. + * + * @param base Base address for current PMC instance. + * @return Current LVWF status + * - true: Low-Voltage Warning Flag is set. + * - false: the Low-Voltage Warning does not happen. + */ +static inline bool PMC_HAL_GetLowVoltWarnFlag(PMC_Type * base) +{ + return PMC_BRD_LVDSC2_LVWF(base); +} + +/*! + * @brief Configures the PMC bandgap. + * + * This function configures the PMC bandgap, including the drive select and + * behavior in low power mode. + * + * @param base Base address for current PMC instance. + * @param config Pointer to the configuration. + */ +static inline void PMC_HAL_BandgapBufferConfig(PMC_Type * base, + pmc_bandgap_buffer_config_t *config) +{ + PMC_WR_REGSC(base, PMC_REGSC_BGBE(config->enable) +#if FSL_FEATURE_PMC_HAS_BGEN + | PMC_REGSC_BGEN(config->enableInLowPower) +#endif +#if FSL_FEATURE_PMC_HAS_BGBDS + | PMC_REGSC_BGBDS(config->drive) +#endif + ); +} + +/*! + * @brief Gets the acknowledge isolation value. + * + * This function reads the Acknowledge Isolation setting that indicates + * whether certain peripherals and the I/O pads are in a latched state as + * a result of having been in the VLLS mode. + * + * @param base Base address for current PMC instance. + * @return ACK isolation + * 0 - Peripherals and I/O pads are in a normal run state. + * 1 - Certain peripherals and I/O pads are in an isolated and + * latched state. + */ +static inline uint8_t PMC_HAL_GetAckIsolation(PMC_Type * base) +{ + return PMC_BRD_REGSC_ACKISO(base); +} + +/*! + * @brief Clears an acknowledge isolation. + * + * This function clears the ACK Isolation flag. Writing one to this setting + * when it is set releases the I/O pads and certain peripherals to their normal + * run mode state. + * + * @param base Base address for current PMC instance. + */ +static inline void PMC_HAL_ClearAckIsolation(PMC_Type * base) +{ + PMC_BWR_REGSC_ACKISO(base, 1U); +} + +/*! + * @brief Gets the Regulator regulation status. + * + * This function returns the regulator to a run regulation status. It provides + * the current status of the internal voltage regulator. + * + * @param base Base address for current PMC instance. + * @return Regulation status + * 0 - Regulator is in a stop regulation or in transition to/from it. + * 1 - Regulator is in a run regulation. + * + */ +static inline uint8_t PMC_HAL_GetRegulatorStatus(PMC_Type * base) +{ + return PMC_BRD_REGSC_REGONS(base); +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif +#endif /* __FSL_PMC_HAL_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_port_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_port_hal.h new file mode 100755 index 0000000..798e7a0 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_port_hal.h @@ -0,0 +1,474 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_PORT_HAL_H__ +#define __FSL_PORT_HAL_H__ + +#include <assert.h> +#include <stdint.h> +#include <stdbool.h> +#include "fsl_device_registers.h" + +/*! + * @addtogroup port_hal + * @{ + */ + +/*! + * @file + * + * The port features such as "digital filter", "pull", etc will be valid when + * it's available in one of the pins. But, that doesn't mean all pins have the + * capabilities to use such features. Please refer related reference manual for + * accuracy pin features. + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Internal resistor pull feature selection*/ +typedef enum _port_pull { + kPortPullDown = 0U, /*!< internal pull-down resistor is enabled. @internal gui name="Down"*/ + kPortPullUp = 1U /*!< internal pull-up resistor is enabled. @internal gui name="Up"*/ +} port_pull_t; + +/*! @brief Slew rate selection*/ +typedef enum _port_slew_rate { + kPortFastSlewRate = 0U, /*!< fast slew rate is configured. @internal gui name="Fast"*/ + kPortSlowSlewRate = 1U /*!< slow slew rate is configured. @internal gui name="Slow" */ +} port_slew_rate_t; + +/*! @brief Configures the drive strength.*/ +typedef enum _port_drive_strength { + kPortLowDriveStrength = 0U, /*!< low drive strength is configured. @internal gui name="Low"*/ + kPortHighDriveStrength = 1U /*!< high drive strength is configured. @internal gui name="High"*/ +} port_drive_strength_t; + +/*! @brief Pin mux selection*/ +typedef enum _port_mux { + kPortPinDisabled = 0U, /*!< corresponding pin is disabled, but is used as an analog pin.*/ + kPortMuxAsGpio = 1U, /*!< corresponding pin is configured as GPIO.*/ + kPortMuxAlt2 = 2U, /*!< chip-specific*/ + kPortMuxAlt3 = 3U, /*!< chip-specific*/ + kPortMuxAlt4 = 4U, /*!< chip-specific*/ + kPortMuxAlt5 = 5U, /*!< chip-specific*/ + kPortMuxAlt6 = 6U, /*!< chip-specific*/ + kPortMuxAlt7 = 7U /*!< chip-specific*/ +} port_mux_t; + +/*! @brief Digital filter clock source selection*/ +#if FSL_FEATURE_PORT_HAS_DIGITAL_FILTER +typedef enum _port_digital_filter_clock_source { + kPortBusClock = 0U, /*!< Digital filters are clocked by the bus clock.*/ + kPortLPOClock = 1U /*!< Digital filters are clocked by the 1 kHz LPO clock.*/ +} port_digital_filter_clock_source_t; +#endif + +/*! @brief Configures the interrupt generation condition.*/ +typedef enum _port_interrupt_config { + kPortIntDisabled = 0x0U, /*!< Interrupt/DMA request is disabled.*/ + #if FSL_FEATURE_PORT_HAS_DMA_REQUEST + kPortDmaRisingEdge = 0x1U, /*!< DMA request on rising edge.*/ + kPortDmaFallingEdge = 0x2U, /*!< DMA request on falling edge.*/ + kPortDmaEitherEdge = 0x3U, /*!< DMA request on either edge.*/ + #endif + kPortIntLogicZero = 0x8U, /*!< Interrupt when logic zero. */ + kPortIntRisingEdge = 0x9U, /*!< Interrupt on rising edge. */ + kPortIntFallingEdge = 0xAU, /*!< Interrupt on falling edge. */ + kPortIntEitherEdge = 0xBU, /*!< Interrupt on either edge. */ + kPortIntLogicOne = 0xCU /*!< Interrupt when logic one. */ +} port_interrupt_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Configuration + * @{ + */ + +#if FSL_FEATURE_PORT_HAS_PULL_SELECTION +/*! + * @brief Selects the internal resistor as pull-down or pull-up. + * + * Pull configuration is valid in all digital pin muxing modes. + * + * @param base port base pointer. + * @param pin port pin number + * @param pullSelect internal resistor pull feature selection + * - kPortPullDown: internal pull-down resistor is enabled. + * - kPortPullUp : internal pull-up resistor is enabled. + */ +static inline void PORT_HAL_SetPullMode(PORT_Type * base, + uint32_t pin, + port_pull_t pullSelect) +{ + assert(pin < 32U); + PORT_BWR_PCR_PS(base, pin, pullSelect); +} +#endif + +#if FSL_FEATURE_PORT_HAS_PULL_ENABLE +/*! + * @brief Enables or disables the internal pull resistor. + * + * @param base port base pointer + * @param pin port pin number + * @param isPullEnabled internal pull resistor enable or disable + * - true : internal pull resistor is enabled. + * - false: internal pull resistor is disabled. + */ +static inline void PORT_HAL_SetPullCmd(PORT_Type * base, + uint32_t pin, + bool isPullEnabled) +{ + assert(pin < 32U); + PORT_BWR_PCR_PE(base, pin, isPullEnabled); +} +#endif + +#if FSL_FEATURE_PORT_HAS_SLEW_RATE +/*! + * @brief Configures the fast/slow slew rate if the pin is used as a digital output. + * + * @param base port base pointer + * @param pin port pin number + * @param rateSelect slew rate selection + * - kPortFastSlewRate: fast slew rate is configured. + * - kPortSlowSlewRate: slow slew rate is configured. + */ +static inline void PORT_HAL_SetSlewRateMode(PORT_Type * base, + uint32_t pin, + port_slew_rate_t rateSelect) +{ + assert(pin < 32U); + PORT_BWR_PCR_SRE(base, pin, rateSelect); +} +#endif + +#if FSL_FEATURE_PORT_HAS_PASSIVE_FILTER +/*! + * @brief Configures the passive filter if the pin is used as a digital input. + * + * If enabled, a low pass filter (10 MHz to 30 MHz bandwidth) is enabled + * on the digital input path. Disable the Passive Input Filter when supporting + * high speed interfaces (> 2 MHz) on the pin. + * + * @param base port base pointer + * @param pin port pin number + * @param isPassiveFilterEnabled passive filter configuration + * - false: passive filter is disabled. + * - true : passive filter is enabled. + */ +static inline void PORT_HAL_SetPassiveFilterCmd(PORT_Type * base, + uint32_t pin, + bool isPassiveFilterEnabled) +{ + assert(pin < 32U); + PORT_BWR_PCR_PFE(base, pin, isPassiveFilterEnabled); +} +#endif + +#if FSL_FEATURE_PORT_HAS_OPEN_DRAIN +/*! + * @brief Enables or disables the open drain. + * + * @param base port base pointer + * @param pin port pin number + * @param isOpenDrainEnabled enable open drain or not + * - false: Open Drain output is disabled on the corresponding pin. + * - true : Open Drain output is disabled on the corresponding pin. + */ +static inline void PORT_HAL_SetOpenDrainCmd(PORT_Type * base, + uint32_t pin, + bool isOpenDrainEnabled) +{ + assert(pin < 32U); + PORT_BWR_PCR_ODE(base, pin, isOpenDrainEnabled); +} +#endif + +#if FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH +/*! + * @brief Configures the drive strength if the pin is used as a digital output. + * + * @param base port base pointer + * @param pin port pin number + * @param driveSelect drive strength selection + * - kLowDriveStrength : low drive strength is configured. + * - kHighDriveStrength: high drive strength is configured. + */ +static inline void PORT_HAL_SetDriveStrengthMode(PORT_Type * base, + uint32_t pin, + port_drive_strength_t driveSelect) +{ + assert(pin < 32U); + PORT_BWR_PCR_DSE(base, pin, driveSelect); +} +#endif + +/*! + * @brief Configures the pin muxing. + * + * @param base port base pointer + * @param pin port pin number + * @param mux pin muxing slot selection + * - kPortPinDisabled: Pin disabled. + * - kPortMuxAsGpio : Set as GPIO. + * - others : chip-specific. + */ +static inline void PORT_HAL_SetMuxMode(PORT_Type * base, + uint32_t pin, + port_mux_t mux) +{ + assert(pin < 32U); + PORT_BWR_PCR_MUX(base, pin, mux); +} + +#if FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK +/*! + * @brief Locks or unlocks the pin control register bits[15:0]. + * + * @param base port base pointer + * @param pin port pin number + * @param isPinLockEnabled lock pin control register or not + * - false: pin control register bit[15:0] are not locked. + * - true : pin control register bit[15:0] are locked, cannot be updated till system reset. + */ +static inline void PORT_HAL_SetPinCtrlLockCmd(PORT_Type * base, + uint32_t pin, + bool isPinLockEnabled) +{ + assert(pin < 32U); + PORT_BWR_PCR_LK(base, pin, isPinLockEnabled); +} +#endif + +#if FSL_FEATURE_PORT_HAS_DIGITAL_FILTER +/*! + * @brief Enables or disables the digital filter in one single port. + * Each bit of the 32-bit register represents one pin. + * + * @param base port base pointer + * @param pin port pin number + * @param isDigitalFilterEnabled digital filter enable/disable + * - false: digital filter is disabled on the corresponding pin. + * - true : digital filter is enabled on the corresponding pin. + */ +static inline void PORT_HAL_SetDigitalFilterCmd(PORT_Type * base, + uint32_t pin, + bool isDigitalFilterEnabled) +{ + assert(pin < 32U); + PORT_SET_DFER(base, (uint32_t)isDigitalFilterEnabled << pin); +} + +/*! + * @brief Configures the clock source for the digital input filters. Changing the filter clock source should + * only be done after disabling all enabled filters. Every pin in one port uses the same + * clock source. + * + * @param base port base pointer + * @param clockSource chose which clock source to use for current port + * - kBusClock: digital filters are clocked by the bus clock. + * - kLPOClock: digital filters are clocked by the 1 kHz LPO clock. + */ +static inline void PORT_HAL_SetDigitalFilterClock(PORT_Type * base, + port_digital_filter_clock_source_t clockSource) +{ + PORT_WR_DFCR(base, clockSource); +} + +/*! + * @brief Configures the maximum size of the glitches (in clock cycles) that the digital filter absorbs + * for enabled digital filters. Glitches that are longer than this register setting + * (in clock cycles) pass through the digital filter, while glitches that are equal + * to or less than this register setting (in clock cycles) are filtered. Changing the + * filter length should only be done after disabling all enabled filters. + * + * @param base port base pointer + * @param width configure digital filter width (should be less than 5 bits). + */ +static inline void PORT_HAL_SetDigitalFilterWidth(PORT_Type * base, uint8_t width) +{ + PORT_WR_DFWR(base, width); +} +#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER*/ + +/*! + * @brief Configures the low half of the pin control register for the same settings. + * This function operates pin 0 -15 of one specific port. + * + * @param base port base pointer + * @param lowPinSelect update corresponding pin control register or not. For a specific bit: + * - 0: corresponding low half of pin control register won't be updated according to configuration. + * - 1: corresponding low half of pin control register will be updated according to configuration. + * @param config value is written to a low half port control register bits[15:0]. + */ +void PORT_HAL_SetLowGlobalPinCtrl(PORT_Type * base, uint16_t lowPinSelect, uint16_t config); + +/*! + * @brief Configures the high half of pin control register for the same settings. + * This function operates pin 16 -31 of one specific port. + * + * @param base port base pointer + * @param highPinSelect update corresponding pin control register or not. For a specific bit: + * - 0: corresponding high half of pin control register won't be updated according to configuration. + * - 1: corresponding high half of pin control register will be updated according to configuration. + * @param config value is written to a high half port control register bits[15:0]. + */ +void PORT_HAL_SetHighGlobalPinCtrl(PORT_Type * base, uint16_t highPinSelect, uint16_t config); + +/*@}*/ + +/*! + * @name Interrupt + * @{ + */ + +/*! + * @brief Configures the port pin interrupt/DMA request. + * + * @param base port base pointer. + * @param pin port pin number + * @param intConfig interrupt configuration + * - kPortIntDisabled : Interrupt/DMA request disabled. + * - kPortDmaRisingEdge : DMA request on rising edge. + * - kPortDmaFallingEdge: DMA request on falling edge. + * - kPortDmaEitherEdge : DMA request on either edge. + * - kPortIntLogicZero : Interrupt when logic zero. + * - kPortIntRisingEdge : Interrupt on rising edge. + * - kPortIntFallingEdge: Interrupt on falling edge. + * - kPortIntEitherEdge : Interrupt on either edge. + * - kPortIntLogicOne : Interrupt when logic one. + */ +static inline void PORT_HAL_SetPinIntMode(PORT_Type * base, + uint32_t pin, + port_interrupt_config_t intConfig) +{ + assert(pin < 32U); + PORT_BWR_PCR_IRQC(base, pin, intConfig); +} + +/*! + * @brief Gets the current port pin interrupt/DMA request configuration. + * + * @param base port base pointer + * @param pin port pin number + * @return interrupt configuration + * - kPortIntDisabled : Interrupt/DMA request disabled. + * - kPortDmaRisingEdge : DMA request on rising edge. + * - kPortDmaFallingEdge: DMA request on falling edge. + * - kPortDmaEitherEdge : DMA request on either edge. + * - kPortIntLogicZero : Interrupt when logic zero. + * - kPortIntRisingEdge : Interrupt on rising edge. + * - kPortIntFallingEdge: Interrupt on falling edge. + * - kPortIntEitherEdge : Interrupt on either edge. + * - kPortIntLogicOne : Interrupt when logic one. + */ +static inline port_interrupt_config_t PORT_HAL_GetPinIntMode(PORT_Type * base, uint32_t pin) +{ + assert(pin < 32U); + return (port_interrupt_config_t)PORT_BRD_PCR_IRQC(base, pin); +} + +/*! + * @brief Reads the individual pin-interrupt status flag. + * + * If a pin is configured to generate the DMA request, the corresponding flag + * is cleared automatically at the completion of the requested DMA transfer. + * Otherwise, the flag remains set until a logic one is written to that flag. + * If configured for a level sensitive interrupt that remains asserted, the flag + * is set again immediately. + * + * @param base port base pointer + * @param pin port pin number + * @return current pin interrupt status flag + * - 0: interrupt is not detected. + * - 1: interrupt is detected. + */ +static inline bool PORT_HAL_IsPinIntPending(PORT_Type * base, uint32_t pin) +{ + assert(pin < 32U); + return PORT_BRD_PCR_ISF(base, pin); +} + +/*! + * @brief Clears the individual pin-interrupt status flag. + * + * @param base port base pointer + * @param pin port pin number + */ +static inline void PORT_HAL_ClearPinIntFlag(PORT_Type * base, uint32_t pin) +{ + assert(pin < 32U); + PORT_BWR_PCR_ISF(base, pin, 1U); +} + +/*! + * @brief Reads the entire port interrupt status flag. + * + * @param base port base pointer + * @return all 32 pin interrupt status flags. For specific bit: + * - 0: interrupt is not detected. + * - 1: interrupt is detected. + */ +static inline uint32_t PORT_HAL_GetPortIntFlag(PORT_Type * base) +{ + return PORT_RD_ISFR(base); +} + +/*! + * @brief Clears the entire port interrupt status flag. + * + * @param base port base pointer + */ +static inline void PORT_HAL_ClearPortIntFlag(PORT_Type * base) +{ + PORT_WR_ISFR(base, ~0U); +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __FSL_PORT_HAL_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_pwm_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_pwm_hal.h new file mode 100755 index 0000000..37ee685 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_pwm_hal.h @@ -0,0 +1,620 @@ +/* + * Copyright (c) 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_PWM_HAL_H__ +#define __FSL_PWM_HAL_H__ + +#include <assert.h> +#include <stdint.h> +#include <stdbool.h> +#include "fsl_device_registers.h" + +#if FSL_FEATURE_SOC_PWM_COUNT + +/*! + * @addtogroup pwm_hal + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief PWM submodules */ +typedef enum _pwm_module +{ + kFlexPwmModule0 = 0U, /*!< Sub-module 0. @internal gui name="PWM Sub-module 0" */ + kFlexPwmModule1, /*!< Sub-module 1. @internal gui name="PWM Sub-module 1" */ + kFlexPwmModule2, /*!< Sub-module 2. @internal gui name="PWM Sub-module 2" */ + kFlexPwmModule3 /*!< Sub-module 3. @internal gui name="PWM Sub-module 3" */ +} pwm_module_t; + +/*! @brief PWM signals from each module */ +typedef enum _pwm_module_signal +{ + kFlexPwmB = 0U, + kFlexPwmA, + kFlexPwmX +} pwm_module_signal_t; + +/*! @brief PWM value registers */ +typedef enum _pwm_val_regs +{ + kFlexPwmVAL0 = 0U, /*!< PWM VAL0 reg. @internal gui name="PWM value register 0" */ + kFlexPwmVAL1, /*!< PWM VAL1 reg. @internal gui name="PWM value register 1" */ + kFlexPwmVAL2, /*!< PWM VAL2 reg. @internal gui name="PWM value register 2" */ + kFlexPwmVAL3, /*!< PWM VAL3 reg. @internal gui name="PWM value register 3" */ + kFlexPwmVAL4, /*!< PWM VAL4 reg. @internal gui name="PWM value register 4" */ + kFlexPwmVAL5 /*!< PWM VAL5 reg. @internal gui name="PWM value register 5" */ +} pwm_val_regs_t; + +/*! @brief PWM status */ +typedef enum _pwm_status { + kStatusPwmSuccess = 0U, /*!< PWM success status.*/ + kStatusPwmError = 1U, /*!< PWM error status.*/ + kStatusPwmInvalidArgument = 2U /*!< PWM invalid argument.*/ +} pwm_status_t; + +/*! @brief PWM clock source selection.*/ +typedef enum _pwm_clock_src +{ + kClkSrcPwmIPBusClk = 0U, /*!< The IPBus clock is used as the clock. @internal gui name="IPBus clock" */ + kClkSrcPwmExtClk, /*!< EXT_CLK is used as the clock. @internal gui name="External clock (EXT_CLK)" */ + kClkSrcPwm0Clk /*!< Clock of Submodule 0 (AUX_CLK) is used as the source clock. @internal gui name="Clock of Submodule 0 clock (AUX_CLK)" */ +} pwm_clock_src_t; + +/*! @brief PWM prescaler factor selection for clock source*/ +typedef enum _pwm_clock_ps +{ + kPwmDividedBy1 = 0U, /*!< PWM clock frequency = fclk/1. @internal gui name="PWM clock divided by 1" */ + kPwmDividedBy2, /*!< PWM clock frequency = fclk/2. @internal gui name="PWM clock divided by 2" */ + kPwmDividedBy4, /*!< PWM clock frequency = fclk/4. @internal gui name="PWM clock divided by 4" */ + kPwmDividedBy8, /*!< PWM clock frequency = fclk/8. @internal gui name="PWM clock divided by 8" */ + kPwmDividedBy16, /*!< PWM clock frequency = fclk/16. @internal gui name="PWM clock divided by 16" */ + kPwmDividedBy32, /*!< PWM clock frequency = fclk/32. @internal gui name="PWM clock divided by 32" */ + kPwmDividedBy64, /*!< PWM clock frequency = fclk/64. @internal gui name="PWM clock divided by 64" */ + kPwmDividedBy128 /*!< PWM clock frequency = fclk/128. @internal gui name="PWM clock divided by 128" */ +} pwm_clock_ps_t; + +/*! @brief Options that can trigger a PWM FORCE_OUT */ +typedef enum _pwm_force_output_trigger +{ + kForceOutputLocalForce = 0U, /*!< The local force signal, CTRL2[FORCE], from this submodule is used to force updates. @internal gui name="The local force signal, CTRL2[FORCE], from this submodule is used to force updates" */ + kForceOutputMasterForce, /*!< The master force signal from submodule 0 is used to force updates. @internal gui name="The master force signal from submodule 0 is used to force updates" */ + kForceOutputLocalReload, /*!< The local reload signal from this submodule is used to force updates without regard to the state of LDOK. @internal gui name="The local reload signal from this submodule is used to force updates without regard to the state of LDOK" */ + kForceOutputMasterReload, /*!< The master reload signal from submodule 0 is used to force updates if LDOK is set. @internal gui name="The master reload signal from submodule 0 is used to force updates if LDOK is set" */ + kForceOutputLocalSync, /*!< The local sync signal from this submodule is used to force updates. @internal gui name="The local sync signal from this submodule is used to force updates" */ + kForceOutputMasterSync, /*!< The master sync signal from submodule0 is used to force updates. @internal gui name="The master sync signal from submodule0 is used to force updates" */ + kForceOutputExternalForce /*!< The external force signal, EXT_FORCE, from outside the PWM module causes updates. @internal gui name="The external force signal, EXT_FORCE, from outside the PWM module causes updates" */ +} pwm_force_output_trigger_t; + +/*! @brief PWM counter initialization options */ +typedef enum _pwm_init_src +{ + kInitSrcLocalSync = 0U, /*!< Local sync (PWM_X) causes initialization. @internal gui name="Local sync (PWM_X) causes initialization"*/ + kInitSrcMasterReload, /*!< Master reload from submodule 0 causes initialization. @internal gui name="Master reload from submodule 0 causes initialization" */ + kInitSrcMasterSync, /*!< Master sync from submodule 0 causes initialization. @internal gui name="Master sync from submodule 0 causes initialization" */ + kInitSrcExtSync /*!< EXT_SYNC causes initialization. @internal gui name="EXT_SYNC causes initialization" */ +} pwm_init_src_t; + +/*! @brief PWM load frequency selection */ +typedef enum _pwm_load_frequency +{ + kPwmLoadEvery1Oportunity = 0U, /*!< Every 1 PWM opportunity. @internal gui name="Every 1 PWM opportunity" */ + kPwmLoadEvery2Oportunity, /*!< Every 2 PWM opportunities. @internal gui name="Every 2 PWM opportunities" */ + kPwmLoadEvery3Oportunity, /*!< Every 3 PWM opportunities. @internal gui name="Every 3 PWM opportunities" */ + kPwmLoadEvery4Oportunity, /*!< Every 4 PWM opportunities. @internal gui name="Every 4 PWM opportunities" */ + kPwmLoadEvery5Oportunity, /*!< Every 5 PWM opportunities. @internal gui name="Every 5 PWM opportunities" */ + kPwmLoadEvery6Oportunity, /*!< Every 6 PWM opportunities. @internal gui name="Every 6 PWM opportunities" */ + kPwmLoadEvery7Oportunity, /*!< Every 7 PWM opportunities. @internal gui name="Every 7 PWM opportunities" */ + kPwmLoadEvery8Oportunity, /*!< Every 8 PWM opportunities. @internal gui name="Every 8 PWM opportunities" */ + kPwmLoadEvery9Oportunity, /*!< Every 9 PWM opportunities. @internal gui name="Every 9 PWM opportunities" */ + kPwmLoadEvery10Oportunity, /*!< Every 10 PWM opportunities. @internal gui name="Every 10 PWM opportunities" */ + kPwmLoadEvery11Oportunity, /*!< Every 11 PWM opportunities. @internal gui name="Every 11 PWM opportunities" */ + kPwmLoadEvery12Oportunity, /*!< Every 12 PWM opportunities. @internal gui name="Every 12 PWM opportunities" */ + kPwmLoadEvery13Oportunity, /*!< Every 13 PWM opportunities. @internal gui name="Every 13 PWM opportunities" */ + kPwmLoadEvery14Oportunity, /*!< Every 14 PWM opportunities. @internal gui name="Every 14 PWM opportunities" */ + kPwmLoadEvery15Oportunity, /*!< Every 15 PWM opportunities. @internal gui name="Every 15 PWM opportunities" */ + kPwmLoadEvery16Oportunity /*!< Every 16 PWM opportunities. @internal gui name="Every 16 PWM opportunities" */ +} pwm_load_frequency_t; + +/*! @brief PWM fault select */ +typedef enum _pwm_fault_input +{ + kFlexPwmFault0 = 0U, /*!< Fault 0 input pin. @internal gui name="Fault pin 0" */ + kFlexPwmFault1, /*!< Fault 1 input pin. @internal gui name="Fault pin 1" */ + kFlexPwmFault2, /*!< Fault 2 input pin. @internal gui name="Fault pin 2" */ + kFlexPwmFault3 /*!< Fault 3 input pin. @internal gui name="Fault pin 3" */ +} pwm_fault_input_t; + +/*! @brief PWM capture edge select */ +typedef enum _pwm_capture_edge +{ + kCaptureDisable = 0U, /*!< Disabled */ + kCaptureFallingEdges, /*!< Capture falling edges */ + kCaptureRisingEdges, /*!< Capture rising edges */ + kCaptureAnyEdges /*!< Capture any edge */ +} pwm_capture_edge_t; + +/*! @brief PWM output options when a FORCE_OUT signal is asserted */ +typedef enum _pwm_force_signal +{ + kFlexPwmUsePwm = 0U, /*!< Generated PWM signal is used by the deadtime logic.*/ + kFlexPwmInvertedPwm, /*!< Inverted PWM signal is used by the deadtime logic.*/ + kFlexPwmSoftwareControl, /*!< Software controlled value is used by the deadtime logic. */ + kFlexPwmUseExternal /*!< PWM_EXTA signal is used by the deadtime logic. */ +} pwm_force_signal_t; + +/*! @brief Optiona available for the PWM A & B pair operation */ +typedef enum _pwm_chnl_pair_operation +{ + kFlexPwmIndependent = 0U, /*!< PWM A & PWM B operation as 2 independent channels. @internal gui name="Independent" */ + kFlexPwmComplementaryPwmA, /*!< PWM A & PWM B are compelementary channels, PWM A generates the signal. @internal gui name="Complementary, PWM A generates the signal" */ + kFlexPwmComplementaryPwmB /*!< PWM A & PWM B are compelementary channels, PWM B generates the signal. @internal gui name="Complementary, PWM B generates the signal" */ +} pwm_chnl_pair_operation_t; + +/*! @brief Options available on how to load the buffered-registers with new values */ +typedef enum _pwm_reg_reload +{ + kFlexPwmReloadImmediate = 0U, /*!< Buffered-registers get loaded with new values as soon as LDOK bit is set. @internal gui name="Reload immediately upon MCTRL[LDOK] being set" */ + kFlexPwmReloadPwmHalfCycle, /*!< Registers loaded on a PWM half cycle. @internal gui name="Reload on a PWM half cycle" */ + kFlexPwmReloadPwmFullCycle, /*!< Registers loaded on a PWM full cycle. @internal gui name="Reload on a PWM full cycle" */ + kFlexPwmReloadPwmHalfAndFullCycle /*!< Registers loaded on a PWM half & full cycle. @internal gui name="Reload on both half and full PWM cycle" */ +} pwm_reg_reload_t; + +/*! @brief Options available on how to re-enable the PWM output when recovering from a fault */ +typedef enum _pwm_fault_recovery_mode +{ + kFlexPwmNoRecovery = 0U, /*!< PWM output will stay inactive. @internal gui name="No Recovery" */ + kFlexPwmRecoverHalfCycle, /*!< PWM output re-enabled at the first half cycle. @internal gui name="Half cycle recovery" */ + kFlexPwmRecoverFullCycle, /*!< PWM output re-enabled at the first full cycle. @internal gui name="Full cycle recovery" */ + kFlexPwmRecoverHalfAndFullCycle /*!< PWM output re-enabled at the first half or full cycle. @internal gui name="Half and Full cycle recovery" */ +} pwm_fault_recovery_mode_t; + +/*! + * @brief Structure is used to hold the parameters to configure a PWM module + * + * @internal gui name="PWM Sub-module configuration" id="pwmModuleCfg" + */ +typedef struct PwmModuleSetup +{ + pwm_init_src_t cntrInitSel; /*!< Option to initialize the counter. @internal gui name="PWM counter initialization" id="pwm_cntrInitSel" */ + pwm_clock_src_t clkSrc; /*!< Clock source for the counter. @internal gui name="PWM clock source" id="pwm_clkSrc" */ + pwm_clock_ps_t prescale; /*!< Pre-scaler to divide down the clock. @internal gui name="PWM clock prescaler" id="pwm_prescale" */ + pwm_chnl_pair_operation_t chnlPairOper; /*!< Channel pair in indepedent or complementary mode. @internal gui name="PWM channel mode" id="pwm_chnlPairOper" */ + pwm_reg_reload_t reloadLogic; /*!< PWM Reload logic setup. @internal gui name="PWM reload logic" id="pwm_reloadLogic" */ + pwm_load_frequency_t reloadFreq; /*!< Specifies when to reload, used when user's choice is not immediate reload. @internal gui name="PWM reload frequency" id="pwm_reloadFreq" */ + pwm_force_output_trigger_t forceTrig; /*!< Specify which signal will trigger a FORCE_OUT. @internal gui name="PWM trigger settings" id="pwm_forceTrig" */ +} pwm_module_setup_t; + + /*! + * @brief Structure is used to hold the parameters to configure a PWM fault + * + * @internal gui name="PWM Fault configuration" id="pwmFaultCfg" + */ +typedef struct PwmFaultSetup +{ + bool automaticClearing; /*!< true: Use automatic fault clearing; false: Manual fault clearing. @internal gui name="Automatic clearing" id="pwm_automaticClearing" */ + bool faultLevel; /*!< true: Logic 1 indicates fault; false: Logic 0 indicates fault. @internal gui name="Fault level" id="pwm_faultLevel" */ + bool useFaultFilter; /*!< true: Use the filtered fault signal; false: Use the direct path from fault input. @internal gui name="Use fault filter" id="pwm_useFaultFilter" */ + pwm_fault_recovery_mode_t recMode; /*!< Specify when to re-enable the PWM output. @internal gui name="Fault recovery mode" id="pwm_recMode" */ +} pwm_fault_setup_t; + +/*! + * @brief Structure is used to hold parameters to configure the capture capability of a signal pin + */ +typedef struct PwmCaptureSetup +{ + bool captureInputSel; /*!< true: Use the edge counter signal as source + false: Use the raw input signal from the pin as source */ + uint8_t edgeCompareVal; /*!< Compare value, used only if edge counter is used as source */ + pwm_capture_edge_t edge0; /*!< Specify which edge causes a capture for input circuitry 0 */ + pwm_capture_edge_t edge1; /*!< Specify which edge causes a capture for input circuitry 1 */ + bool oneShotCapture; /*!< true: Use one-shot capture mode; + false: Use free-running capture mode */ +} pwm_capture_setup_t; + + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initialize the PWM to its reset state. + * + * Set the control registers to their reset state + * + * @param base Base address pointer of eflexPWM module + */ +void PWM_HAL_Init(PWM_Type *base); + +/*! + * @brief Sets up a PWM sub-module. + * + * Flex PWM has 4 sub-modules. This function sets up key features that configure the + * working of each sub-module. This function will setup: + * 1. Clock source and clock prescaler + * 2. Submodules PWM A & PWM B signals operation (independent or complementary) + * 3. Reload logic to use and reload freqeuncy + * 4. Force trigger to use to generate the FORCE_OUT signal. + * + * @param base Base address pointer of eflexPWM module + * @param subModuleNum is a number of the PWM submodule. + * @param setupParams Parameters passed in to setup the submodule + */ +void PWM_HAL_SetupPwmSubModule(PWM_Type *base, pwm_module_t subModuleNum, + pwm_module_setup_t *setupParams); + +/*! + * @brief Sets up the working of the Flex PWM fault protection. + * + * Flex PWM has 4 fault inputs. This function sets up the working of each fault. The function + * will setup: + * 1. Fault automatic clearing function + * 2. Sets up the fault level + * 3. Defines if the fault filter should be used for this fault input + * 4. Recovery mode to be used to re-enable the PWM output + * + * @param base Base address pointer of eflexPWM module + * @param faultNum is a number of the PWM fault to configure. + * @param setupParams Parameters passed in to setup the fault + */ +void PWM_HAL_SetupFaults(PWM_Type *base, pwm_fault_input_t faultNum, + pwm_fault_setup_t *setupParams); + +/*! + * @brief Sets up the Flex PWM capture + * + * Each PWM submodule has 3 pins can be configured to use for capture. This function will + * setup the capture for each pin as follows: + * 1. Whether to use the edge counter or raw input + * 2. Edge capture mode + * 3. One-shot or continuous + * + * @param base Base address pointer of eflexPWM module + * @param subModuleNum is a number of the PWM submodule. + * @param pwmSignal Which signal in the submodule to setup + * @param setupParams Parameters passed in to setup the input pin + */ +void PWM_HAL_SetupCapture(PWM_Type *base, pwm_module_t subModuleNum, + pwm_module_signal_t pwmSignal, pwm_capture_setup_t *setupParams); + +/*! + * @brief Gets PWM capture value. + * + * Read one of the 6 capture value registers + * + * @param base Base address pointer of eflexPWM module + * @param subModuleNum is a number of the PWM submodule. + * @param cmpReg is a number of value compare register to get + * @return PWM value register + */ +uint16_t PWM_HAL_GetCaptureValReg(PWM_Type *base, pwm_module_t subModuleNum, + pwm_val_regs_t cmpReg); + +/*! + * @brief Sets PWM value register. + * + * Sets one of the 6 value registers. + * + * @param base Base address pointer of eflexPWM module + * @param subModuleNum is a number of the PWM submodule. + * @param valReg is the number of the value register to be set + * @param val is a number of value to write + */ +void PWM_HAL_SetValReg (PWM_Type *base, uint8_t subModuleNum, pwm_val_regs_t valReg, + uint16_t val); + +/*! + * @brief Selects the signal to output when a FORCE_OUT signal is asserted + * + * User specifies which pin to configure by supplying the submodule number and whether + * he wishes to modify PWM A or PWM B within that submodule + * + * @param base Base address pointer of eflexPWM module + * @param subModuleNum is a number of the PWM submodule. + * @param pwmSignal specifies which signal to work with in the module + * @param mode signal to output when a FORCE_OUT is triggered + */ +void PWM_HAL_SetupForceSignal(PWM_Type *base, pwm_module_t subModuleNum, + pwm_module_signal_t pwmSignal, pwm_force_signal_t mode); + + +/*! + * @brief Returns PWM peripheral current counter value. + * + * @param base Base address pointer of eflexPWM module + * @param subModuleNum is a number of the PWM submodule. + * @return current PWM counter value + */ +static inline uint16_t PWM_HAL_GetCounter(PWM_Type *base, pwm_module_t subModuleNum) +{ + return PWM_RD_CNT(base, subModuleNum); +} + +/*! + * @brief Sets PWM timer counter initial value. + * + * @param base Base address pointer of eflexPWM module + * @param subModuleNum is a number of the PWM submodule. + * @param val initial value to be set + */ +static inline void PWM_HAL_SetCounterInitVal(PWM_Type *base, pwm_module_t subModuleNum, + uint16_t val) +{ + PWM_WR_INIT(base, subModuleNum, val); +} + +/*! + * @brief Outputs a FORCE signal. + * + * This function will enable/disable the force init logic and assert/de-assert the FORCE signal + * + * @param base Base address pointer of eflexPWM module + * @param subModuleNum is a number of the PWM submodule. + * @param val true to enable, false to disable. + */ +static inline void PWM_HAL_SetForceCmd(PWM_Type *base, pwm_module_t subModuleNum, bool val ) +{ + PWM_BWR_CTRL2_FRCEN(base, subModuleNum, val); + PWM_BWR_CTRL2_FORCE(base, subModuleNum, val); +} + +/*! + * @brief Sets output polarity for PWM_B. + * + * @param base Base address pointer of eflexPWM module + * @param subModuleNum is a number of the PWM submodule. + * @param val true to set inverted output, false to set non inverted output. + */ +static inline void PWM_HAL_SetOutputPolarityPwmBCmd(PWM_Type *base, pwm_module_t subModuleNum, + bool val) +{ + PWM_BWR_OCTRL_POLB(base, subModuleNum, val); +} + +/*! + * @brief Sets output polarity for PWM_A. + * + * @param base Base address pointer of eflexPWM module + * @param subModuleNum is a number of the PWM submodule. + * @param val true to set inverted output, false to set non inverted output. + */ +static inline void PWM_HAL_SetOutputPolarityPwmACmd(PWM_Type *base, pwm_module_t subModuleNum, + bool val) +{ + PWM_BWR_OCTRL_POLA(base, subModuleNum, val); +} + +/*! + * @brief Sets output polarity for PWM_X. + * + * @param base Base address pointer of eflexPWM module + * @param subModuleNum is a number of the PWM submodule. + * @param val true to set inverted output, false to set non inverted output. + */ +static inline void PWM_HAL_SetOutputPolarityPwmXCmd(PWM_Type *base, pwm_module_t subModuleNum, + bool val) +{ + PWM_BWR_OCTRL_POLX(base, subModuleNum, val); +} + +/*! + * @brief Enables or disables if a match with a value register will cause an output trigger. + * + * There are 2 triggers available per PWM submodule. This function allows the user the ability + * to activate a trigger when the counter matches one of the 6 value registers. Enabling + * VAL0, VAL2 or VAL4 will output a trigger on a match on TRIG0. Enabling VAL1, VAL3, VAL5 will + * output a trigger on a match on TRIG1. + * + * @param base Base address pointer of eflexPWM module + * @param subModuleNum is a number of the PWM submodule. + * @param valueReg register that is the cause for the output triger. + * @param val true to trigger enable, false to disable. + */ +static inline void PWM_HAL_SetOutputTriggerCmd(PWM_Type *base, pwm_module_t subModuleNum, + uint8_t valueReg, bool val) +{ + assert(valueReg < 6U); + val ? PWM_SET_TCTRL(base, subModuleNum, 1U << valueReg) : + PWM_CLR_TCTRL(base, subModuleNum, 1U << valueReg); +} + +/*! + * @brief Enables or disables fault input for PWM A. + * + * Enabling the specified fault will cause the PWM A signal to deactivate when the fault occurs. + * User should configure the PWM faults by calling PWM_HAL_SetupFaults() prior to enabling them + * in the submodules. + * + * @param base Base address pointer of eflexPWM module + * @param subModuleNum is a number of the PWM submodule. + * @param fault number, options: 0,1,2,3 . + * @param val true to enable the fault input, false to disable fault input. + */ +static inline void PWM_HAL_SetPwmAFaultInputCmd(PWM_Type *base, pwm_module_t subModuleNum, + pwm_fault_input_t fault, bool val) +{ + val ? PWM_SET_DISMAP(base, subModuleNum, 0, 1U << fault) : + PWM_CLR_DISMAP(base, subModuleNum, 0, 1U << fault); +} + +/*! + * @brief Enables or disables fault input for PWM B. + * + * Enabling the specified fault will cause the PWM B signal to deactivate when the fault occurs. + * User should configure the PWM faults by calling PWM_HAL_SetupFaults() prior to enabling them + * in the submodules. + * + * @param base Base address pointer of eflexPWM module + * @param subModuleNum is a number of the PWM submodule. + * @param fault number, options: 0,1,2,3 . + * @param val true to enable the fault input, false to disable fault input. + */ +static inline void PWM_HAL_SetPwmBFaultInputCmd(PWM_Type *base, pwm_module_t subModuleNum, + pwm_fault_input_t fault, bool val) +{ + val ? PWM_SET_DISMAP(base, subModuleNum, 0, 1U << (fault + PWM_DISMAP_DIS0B_SHIFT)) : + PWM_CLR_DISMAP(base, subModuleNum, 0, 1U << (fault + PWM_DISMAP_DIS0B_SHIFT)); +} + +/*! + * @brief Enables or disables fault input for PWM X. + * + * Enabling the specified fault will cause the PWM X signal to deactivate when the fault occurs. + * User should configure the PWM faults by calling PWM_HAL_SetupFaults() prior to enabling them + * in the submodules. + * + * @param base Base address pointer of eflexPWM module + * @param subModuleNum is a number of the PWM submodule. + * @param fault number, options: 0,1,2,3. + * @param val true to enable the fault input; false to disable the fault input + */ +static inline void PWM_HAL_SetPwmXFaultInputCmd(PWM_Type *base, pwm_module_t subModuleNum, + pwm_fault_input_t fault, bool val) +{ + val ? PWM_SET_DISMAP(base, subModuleNum, 0, 1U << (fault + PWM_DISMAP_DIS0X_SHIFT)) : + PWM_CLR_DISMAP(base, subModuleNum, 0, 1U << (fault + PWM_DISMAP_DIS0X_SHIFT)); +} + +/*! + * @brief Sets PWM_X pin to input or output. + * + * @param base Base address pointer of eflexPWM module + * @param subModuleNum Number of the PWM submodule. + * @param val true to make the pin as output output, false to make the pin as input + */ +static inline void PWM_HAL_SetOutputPwmXCmd(PWM_Type *base, pwm_module_t subModuleNum, + bool val) +{ + val ? PWM_SET_OUTEN(base, 1U << subModuleNum) : + PWM_CLR_OUTEN(base, 1U << subModuleNum); +} + +/*! + * @brief Sets PWM_B pin to input or output. + * + * @param base Base address pointer of eflexPWM module + * @param subModuleNum Number of the PWM submodule. + * @param val true to make the pin as output output, false to make the pin as input + */ +static inline void PWM_HAL_SetOutputPwmBCmd(PWM_Type *base, pwm_module_t subModuleNum, + bool val) +{ + val ? PWM_SET_OUTEN(base, 1U << (subModuleNum + PWM_OUTEN_PWMB_EN_SHIFT)) : + PWM_CLR_OUTEN(base, 1U << (subModuleNum + PWM_OUTEN_PWMB_EN_SHIFT)); +} + +/*! + * @brief Sets PWM_A pin to input or output. + * + * @param base Base address pointer of eflexPWM module + * @param subModuleNum Number of the PWM submodule. + * @param val true to make the pin as output output, false to make the pin as input + */ +static inline void PWM_HAL_SetOutputPwmACmd(PWM_Type *base, pwm_module_t subModuleNum, + bool val) +{ + val ? PWM_SET_OUTEN(base, 1U << (subModuleNum + PWM_OUTEN_PWMA_EN_SHIFT)) : + PWM_CLR_OUTEN(base, 1U << (subModuleNum + PWM_OUTEN_PWMA_EN_SHIFT)); +} + +/*! + * @brief Sets software control output for a pin to high or low. + * + * User specifies which signal to modify by supplying the submodule number and whether + * he wishes to modify PWM A or PWM B within that submodule + * + * @param base Base address pointer of eflexPWM module + * @param subModuleNum is a number of the PWM submodule. + * @param output specifies which signal to work with in the module, 0 is PWM B, 1 is PWM A + * @param val true to supply a logic 1, false to supply a logic 0. + */ +static inline void PWM_HAL_SetSwCtrlOutCmd(PWM_Type *base, pwm_module_t subModuleNum, + pwm_module_signal_t output, bool val) +{ + val ? PWM_SET_SWCOUT(base, (1U << ((subModuleNum * 2) + output))) : + PWM_CLR_SWCOUT(base, (1U << ((subModuleNum * 2) + output))); +} + +/*! + * @brief Sets PWM generator run. + * + * @param base Base address pointer of eflexPWM module + * @param subModules represented by corresponded bits. + * @param val true to run selected subModuleNums, false to stop selected subModuleNums output. + */ +static inline void PWM_HAL_SetPwmRunCmd(PWM_Type *base, uint8_t subModules, bool val) +{ + assert(subModules < 16U); + val ? PWM_SET_MCTRL(base, (unsigned)subModules << PWM_MCTRL_RUN_SHIFT) : + PWM_CLR_MCTRL(base, (unsigned)subModules << PWM_MCTRL_RUN_SHIFT); +} + +/*! + * @brief Sets fault interrupt. + * + * @param base Base address pointer of eflexPWM module + * @param fault represented by corresponded bits. + * @param val true to enable the interrupt request, false to disable. + */ +static inline void PWM_HAL_SetFaultIntCmd(PWM_Type *base, pwm_fault_input_t fault, + bool val) +{ + val ? PWM_SET_FCTRL(base, (1U << fault)) : PWM_CLR_FCTRL(base, (1U << fault)); +} + +/*! + * @brief Clears fault flags. + * + * @param base Base address pointer of eflexPWM module + * @param fault represented by corresponded bits. + */ +static inline void PWM_HAL_ClearFaultFlags(PWM_Type *base, pwm_fault_input_t fault) +{ + PWM_SET_FSTS(base, (1U << fault)); +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_FEATURE_SOC_PWM_COUNT */ + +#endif /* __FSL_PWM_HAL_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_rcm_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_rcm_hal.h new file mode 100755 index 0000000..b0d4d9a --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_rcm_hal.h @@ -0,0 +1,238 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#if !defined(__FSL_RCM_HAL_H__) +#define __FSL_RCM_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> +#include <assert.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_RCM_COUNT + +/*! @addtogroup rcm_hal*/ +/*! @{*/ + +/*! @file fsl_rcm_hal.h */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief System Reset Source Name definitions */ +typedef enum _rcm_source_names { + kRcmSrcAll = 0U, /*!< Parameter could get all reset flags */ + kRcmWakeup = RCM_SRS0_WAKEUP_MASK, /*!< low-leakage wakeup reset */ + kRcmLowVoltDetect = RCM_SRS0_LVD_MASK, /*!< low voltage detect reset */ +#if FSL_FEATURE_RCM_HAS_LOC + kRcmLossOfClk = RCM_SRS0_LOC_MASK, /*!< loss of clock reset */ +#endif +#if FSL_FEATURE_RCM_HAS_LOL + kRcmLossOfLock = RCM_SRS0_LOL_MASK, /*!< loss of lock reset */ +#endif + kRcmWatchDog = RCM_SRS0_WDOG_MASK, /*!< watch dog reset */ + kRcmExternalPin = RCM_SRS0_PIN_MASK, /*!< external pin reset */ + kRcmPowerOn = RCM_SRS0_POR_MASK, /*!< power on reset */ +#if FSL_FEATURE_RCM_HAS_JTAG + kRcmJtag = RCM_SRS1_JTAG_MASK << 8U, /*!< JTAG generated reset */ +#endif + kRcmCoreLockup = RCM_SRS1_LOCKUP_MASK << 8U, /*!< core lockup reset */ + kRcmSoftware = RCM_SRS1_SW_MASK << 8U, /*!< software reset */ + kRcmMdmAp = RCM_SRS1_MDM_AP_MASK << 8U, /*!< MDM-AP system reset. */ +#if FSL_FEATURE_RCM_HAS_EZPORT + kRcmEzport = RCM_SRS1_EZPT_MASK << 8U, /*!< EzPort reset */ +#endif + kRcmStopModeAckErr = RCM_SRS1_SACKERR_MASK << 8U, /*!< stop mode ack error reset */ +} rcm_source_names_t; + +/*! @brief Reset pin filter select in Run and Wait modes */ +typedef enum _rcm_filter_run_wait_modes { + kRcmFilterDisabled, /*!< all filtering disabled */ + kRcmFilterBusClk, /*!< Bus clock filter enabled */ + kRcmFilterLpoClk, /*!< LPO clock filter enabled */ + kRcmFilterReserverd /*!< reserved setting */ +} rcm_filter_run_wait_modes_t; + +#if FSL_FEATURE_RCM_HAS_BOOTROM +/*! @brief Boot from ROM configuration. */ +typedef enum _rcm_boot_rom_config { + kRcmBootFlash, /*!< Boot from flash */ + kRcmBootRomCfg0, /*!< Boot from boot rom due to BOOTCFG0 */ + kRcmBootRomFopt, /*!< Boot from boot rom due to FOPT[7] */ + kRcmBootRomBoth /*!< Boot from boot rom due to both BOOTCFG0 and FOPT[7] */ +} rcm_boot_rom_config_t; +#endif + +/*! @brief Reset pin filter configuration. */ +typedef struct _rcm_reset_pin_filter_config +{ + bool filterInStop; /*!< Reset pin filter select in stop mode. */ + rcm_filter_run_wait_modes_t filterInRunWait; /*!< Reset pin filter in run/wait mode. */ + uint8_t busClockFilterCount; /*!< Reset pin bus clock filter width. */ +} rcm_reset_pin_filter_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! @name Reset Control Module APIs*/ +/*@{*/ + +/*! + * @brief Gets the reset source status. + * + * This function gets the current reset source status for some specified sources. + * + * Example: + @code + uint32_t resetStatus; + + // To get all reset source statuses. + resetStatus = RCM_HAL_GetSrcStatus(RCM, kRcmSrcAll); + + // To test whether MCU is reset by watchdog. + resetStatus = RCM_HAL_GetSrcStatus(RCM, kRcmWatchDog); + + // To test multiple reset source. + resetStatus = RCM_HAL_GetSrcStatus(RCM, kRcmWatchDog | kRcmSoftware); + @endcode + * + * @param base Register base address of RCM + * @param statusMask Bit mask for the reset sources to get. + * @return The reset source status. + */ +uint32_t RCM_HAL_GetSrcStatus(RCM_Type * base, uint32_t statusMask); + +#if FSL_FEATURE_RCM_HAS_SSRS +/*! + * @brief Gets the sticky reset source status. + * + * This function gets the current reset source status that have not been cleared + * by software for some specified sources. + * + * @param base Register base address of RCM + * @param statusMask Bit mask for the reset sources to get. + * @return The reset source status. + */ +uint32_t RCM_HAL_GetStickySrcStatus(RCM_Type * base, uint32_t statusMask); + +/*! + * @brief Clear the sticky reset source status. + * + * This function clears all the sticky system reset flags. + * + * @param base Register base address of RCM + */ +void RCM_HAL_ClearStickySrcStatus(RCM_Type * base); +#endif + +/*! + * @brief Sets the reset pin filter base on configuration. + * + * This function sets the reset pin filter, including filter source, filter + * width and so on. + * + * @param base Register base address of RCM + * @param config Pointer to the configuration structure. + */ +void RCM_HAL_SetResetPinFilterConfig(RCM_Type * base, rcm_reset_pin_filter_config_t *config); + +#if FSL_FEATURE_RCM_HAS_EZPMS +/*! + * @brief Gets the EZP_MS_B pin assert status. + * + * This function gets the easy port mode status (EZP_MS_B) pin assert status. + * + * @param base Register base address of RCM + * @return status true - asserted, false - reasserted + */ +static inline bool RCM_HAL_GetEasyPortModeStatus(RCM_Type * base) +{ + return (bool)RCM_BRD_MR_EZP_MS(base); +} +#endif + +#if FSL_FEATURE_RCM_HAS_BOOTROM +/*! + * @brief Force the boot from ROM. + * + * This function forces boot from ROM during all subsequent system resets. + * + * @param base Register base address of RCM + * @param config Boot configuration. + */ +static inline void RCM_HAL_SetForceBootRomSrc(RCM_Type * base, + rcm_boot_rom_config_t config) +{ + RCM_BWR_FM_FORCEROM(base, config); +} + +/*! + * @brief Get the ROM boot source. + * + * This function gets the ROM boot source during the last chip reset. + * + * @param base Register base address of RCM + * @return The ROM boot source. + */ +static inline rcm_boot_rom_config_t RCM_HAL_GetBootRomSrc(RCM_Type * base) +{ + return (rcm_boot_rom_config_t)RCM_BRD_MR_BOOTROM(base); +} + +/*! + * @brief Clear the ROM boot source flag. + * + * This function clears the ROM boot source flag. + * + * @param base Register base address of RCM + */ +static inline void RCM_HAL_ClearBootRomSrc(RCM_Type * base) +{ + RCM_BWR_MR_BOOTROM(base, kRcmBootRomBoth); +} +#endif + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif +#endif /* __FSL_RCM_HAL_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_rnga_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_rnga_hal.h new file mode 100755 index 0000000..34381fa --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_rnga_hal.h @@ -0,0 +1,351 @@ +/* + * Copyright (c) 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_RNGA_HAL_H__ +#define __FSL_RNGA_HAL_H__ + +#include <assert.h> +#include <stdint.h> +#include <stdbool.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_RNG_COUNT + +/*! + * @addtogroup rnga_hal + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @brief the max cpu clock cycles rnga module used to get a new random data */ +#define MAX_COUNT 4096 + +/*! @brief RNGA working mode */ +typedef enum _rnga_mode +{ + kRNGAModeNormal = 0U, /*!< Normal Mode. */ + kRNGAModeSleep = 1U, /*!< Sleep Mode. */ +} rnga_mode_t; + +/*! @brief Defines the value of output register level */ +typedef enum _rnga_output_reg_level +{ + kRNGAOutputRegLevelNowords = 0U, /*!< output register no words. */ + kRNGAOutputRegLevelOneword = 1U, /*!< output register one word. */ +} rnga_output_reg_level_t; + +/*! + * @brief Status structure for RNGA + * + * This structure holds the return code of RNGA module. + */ + +typedef enum _rnga_status +{ + kStatus_RNGA_Success = 0U, /*!< Success */ + kStatus_RNGA_InvalidArgument = 1U, /*!< Invalid argument */ + kStatus_RNGA_Underflow = 2U, /*!< Underflow */ + kStatus_RNGA_Timeout = 3U, /*!< Timeout */ +} rnga_status_t; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name RNGA HAL. + * @{ + */ + + +/*! + * @brief Initializes the RNGA module. + * + * This function initializes the RNGA to a default state. + * + * @param base, RNGA base address + */ +static inline void RNGA_HAL_Init(RNG_Type * base) +{ + RNG_WR_CR(base, 0); +} + + +/*! + * @brief Enables the RNGA module. + * + * This function enables the RNGA random data generation and loading. + * + * @param base, RNGA base address + */ +static inline void RNGA_HAL_Enable(RNG_Type * base) +{ + RNG_BWR_CR_GO(base, 1); +} + + +/*! + * @brief Disables the RNGA module. + * + * This function disables the RNGA module. + * + * @param base, RNGA base address +*/ +static inline void RNGA_HAL_Disable(RNG_Type * base) +{ + RNG_BWR_CR_GO(base, 0); +} + + +/*! + * @brief Sets the RNGA high assurance. + * + * This function sets the RNGA high assurance(notification of security + * violations. + * + * @param base, RNGA base address + * @param enable, 0 means notification of security violations disabled. + * 1 means notification of security violations enabled. +*/ +static inline void RNGA_HAL_SetHighAssuranceCmd(RNG_Type * base, bool enable) +{ + RNG_BWR_CR_HA(base, enable); +} + + +/*! + * @brief Sets the RNGA interrupt mask. + * + * This function sets the RNGA error interrupt mask. + * + * @param base, RNGA base address + * @param enable, 0 means unmask RNGA interrupt. + * 1 means mask RNGA interrupt. +*/ +static inline void RNGA_HAL_SetIntMaskCmd(RNG_Type * base, bool enable) +{ + RNG_BWR_CR_INTM(base, enable); +} + + +/*! + * @brief Clears the RNGA interrupt. + * + * This function clears the RNGA interrupt. + * + * @param base, RNGA base address + * @param enable, 0 means do not clear the interrupt. + * 1 means clear the interrupt. +*/ +static inline void RNGA_HAL_ClearIntFlag(RNG_Type * base, bool enable) +{ + RNG_BWR_CR_CLRI(base, enable); +} + + +/*! + * @brief Sets the RNGA in sleep mode or normal mode. + * + * This function specifies whether the RNGA is in sleep mode or normal mode. + * + * @param base, RNGA base address + * @param mode, kRNGAModeNormal means set RNGA in normal mode. + * kRNGAModeSleep means set RNGA in sleep mode. +*/ +static inline void RNGA_HAL_SetWorkModeCmd(RNG_Type * base, rnga_mode_t mode) +{ + RNG_BWR_CR_SLP(base, (uint32_t)mode); +} + + +/*! + * @brief Gets the output register size. + * + * This function gets the size of the output register as + * 32-bit random data words it can hold. + * + * @param base, RNGA base address + * @return 1 means one word(this value is fixed). + */ +static inline uint8_t RNGA_HAL_GetOutputRegSize(RNG_Type * base) +{ + return RNG_BRD_SR_OREG_SIZE(base); +} + + +/*! + * @brief Gets the output register level. + * + * This function gets the number of random-data words that are in OR + * [RANDOUT], which indicates if OR is valid. + * + * @param base, RNGA base address + * @return 0 means no words(empty), 1 means one word(valid). + */ +static inline rnga_output_reg_level_t RNGA_HAL_GetOutputRegLevel(RNG_Type * base) +{ + return (rnga_output_reg_level_t)(RNG_BRD_SR_OREG_LVL(base)); +} + + +/*! + * @brief Gets the RNGA working mode. + * + * This function checks whether the RNGA works in sleep mode or normal mode. + * + * @param base, RNGA base address + * @return Kmode_RNGA_Normal means in normal mode + * Kmode_RNGA_Sleep means in sleep mode +*/ +static inline rnga_mode_t RNGA_HAL_GetWorkMode(RNG_Type * base) +{ + return (rnga_mode_t)RNG_BRD_SR_SLP(base); +} + + +/*! + * @brief Gets the RNGA status whether an error interrupt has occurred. + * + * This function gets the RNGA status whether an OR underflow + * condition has occurred since the error interrupt was last cleared or the RNGA was + * reset. + * + * @param base, RNGA base address + * @return 0 means no underflow, 1 means underflow +*/ +static inline bool RNGA_HAL_GetErrorIntCmd(RNG_Type * base) +{ + return (RNG_BRD_SR_ERRI(base)); +} + + +/*! + * @brief Gets the RNGA status whether an output register underflow has occurred. + * + * This function gets the RNGA status whether an OR underflow + * condition has occurred since the register (SR) was last read or the RNGA was + * reset. + * + * @param base, RNGA base address + * @return 0 means no underflow, 1 means underflow +*/ +static inline bool RNGA_HAL_GetOutputRegUnderflowCmd(RNG_Type * base) +{ + return (RNG_BRD_SR_ORU(base)); +} + + +/*! + * @brief Gets the most recent RNGA read status. + * + * This function gets the RNGA status whether the most recent read of + * OR[RANDOUT] causes an OR underflow condition. + * + * @param base, RNGA base address + * @return 0 means no underflow, 1 means underflow +*/ +static inline bool RNGA_HAL_GetLastReadStatusCmd(RNG_Type * base) +{ + return (RNG_BRD_SR_LRS(base)); +} + + +/*! + * @brief Gets the RNGA status whether a security violation has occurred. + * + * This function gets the RNGA status whether a security violation has + * occurred when high assurance is enabled. + * + * @param base, RNGA base address + * @return 0 means no security violation, 1 means security violation +*/ +static inline bool RNGA_HAL_GetSecurityViolationCmd(RNG_Type * base) +{ + return (RNG_BRD_SR_SECV(base)); +} + + +/*! + * @brief Gets a random data from the RNGA. + * + * This function gets a random data from RNGA. + * + * @param base, RNGA base address + * @return random data obtained +*/ +static inline uint32_t RNGA_HAL_ReadRandomData(RNG_Type * base) +{ + return (RNG_RD_OR(base)); +} + + +/*! + * @brief Get random data. + * + * This function is used to get a random data from RNGA + * + * @param base, RNGA base address + * @param data, pointer address used to store random data + * @return one random data + */ +rnga_status_t RNGA_HAL_GetRandomData(RNG_Type * base, uint32_t *data); + + +/*! + * @brief Inputs an entropy value used to seed the RNGA. + * + * This function specifies an entropy value that RNGA uses with + * its ring oscillations to seed its pseudorandom algorithm. + * + * @param base, RNGA base address + * @param data, external entropy value +*/ +static inline void RNGA_HAL_WriteSeed(RNG_Type * base, uint32_t data) +{ + RNG_WR_ER(base, data); +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif +#endif /* __FSL_RNGA_HAL_H__*/ +/******************************************************************************* + * EOF + *******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_rtc_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_rtc_hal.h new file mode 100755 index 0000000..0e926f6 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_rtc_hal.h @@ -0,0 +1,953 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#if !defined(__FSL_RTC_HAL_H__) +#define __FSL_RTC_HAL_H__ + +#include <assert.h> +#include <stdint.h> +#include <stdbool.h> +#include "fsl_device_registers.h" + +#if FSL_FEATURE_SOC_RTC_COUNT + +/*! + * @addtogroup rtc_hal + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Error codes for RTC driver. */ +typedef enum _rtc_status +{ + kStatusRtcSuccess = 0x00U, /*!< RTC success status.*/ + kStatusRtcFail = 0x01U /*!< RTC error status.*/ +} rtc_status_t; + +/*! + * @brief Structure is used to hold the time in a simple "date" format. + */ +typedef struct RtcDatetime +{ + uint16_t year; /*!< Range from 1970 to 2099.*/ + uint16_t month; /*!< Range from 1 to 12.*/ + uint16_t day; /*!< Range from 1 to 31 (depending on month).*/ + uint16_t hour; /*!< Range from 0 to 23.*/ + uint16_t minute; /*!< Range from 0 to 59.*/ + uint8_t second; /*!< Range from 0 to 59.*/ +} rtc_datetime_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name RTC HAL API Functions + * @{ + */ + +/*! + * @brief Initializes the RTC module. + * + * This function enables the RTC oscillator. + * + * @param rtcBase The RTC base address pointer + */ +void RTC_HAL_Enable(RTC_Type *rtcBase); + +/*! + * @brief Disables the RTC module. + * + * This function disables the RTC counter and oscillator. + * + * @param rtcBase The RTC base address pointer + */ +void RTC_HAL_Disable(RTC_Type *rtcBase); + +/*! + * @brief This function will clear all interrupts. + * + * This function initiates a soft-reset of the RTC module if the time invalid flag is set. + * + * @param rtcBase The RTC base address pointer. + */ +void RTC_HAL_Init(RTC_Type *rtcBase); + +/*! + * @brief Converts seconds to date time format data structure. + * + * @param seconds holds the date and time information in seconds + * @param datetime holds the converted information from seconds in date and time format + */ +void RTC_HAL_ConvertSecsToDatetime(const uint32_t * seconds, rtc_datetime_t * datetime); + +/*! + * @brief Checks whether the date time structure elements have the information that is within the range. + * + * @param datetime holds the date and time information that needs to be converted to seconds + * + * @return returns true if the datetime argument has the right format, false otherwise + */ +bool RTC_HAL_IsDatetimeCorrectFormat(const rtc_datetime_t * datetime); + +/*! + * @brief Converts the date time format data structure to seconds. + * + * @param datetime holds the date and time information that needs to be converted to seconds + * @param seconds holds the converted date and time in seconds + */ +void RTC_HAL_ConvertDatetimeToSecs(const rtc_datetime_t * datetime, uint32_t * seconds); + +/*! + * @brief Sets the RTC date and time according to the given time structure. + * + * The function converts the data from the time structure to seconds and writes the seconds + * value to the RTC register. The RTC counter is started after setting the time. + * + * @param rtcBase The RTC base address pointer + * @param datetime [in] Pointer to structure where the date and time + * details to set are stored. + */ +void RTC_HAL_SetDatetime(RTC_Type *rtcBase, const rtc_datetime_t * datetime); + +/*! + * @brief Sets the RTC date and time according to the given time provided in seconds. + * + * The RTC counter is started after setting the time. + * + * @param rtcBase The RTC base address pointer + * @param seconds [in] Time in seconds + */ +void RTC_HAL_SetDatetimeInsecs(RTC_Type *rtcBase, const uint32_t seconds); + +/*! + * @brief Gets the RTC time and stores it in the given time structure. + * + * The function reads the value in seconds from the RTC register. It then converts to the + * time structure which provides the time in date, hour, minutes and seconds. + * + * @param rtcBase The RTC base address pointer + * @param datetime [out] pointer to a structure where the date and time details are + * stored. + */ +void RTC_HAL_GetDatetime(RTC_Type *rtcBase, rtc_datetime_t * datetime); + +/*! + * @brief Gets the RTC time and returns it in seconds. + * + * @param rtcBase The RTC base address pointer + * @param seconds [out] pointer to variable where the RTC time is stored in seconds + */ +void RTC_HAL_GetDatetimeInSecs(RTC_Type *rtcBase, uint32_t * seconds); + +/*! + * @brief Reads the value of the time alarm. + * + * @param rtcBase The RTC base address pointer + * @param date [out] pointer to a variable where the alarm date and time + * details are stored. + */ +void RTC_HAL_GetAlarm(RTC_Type *rtcBase, rtc_datetime_t * date); + +/*! + * @brief Sets the RTC alarm time and enables the alarm interrupt. + * + * The function checks whether the specified alarm time is greater than the present + * time. If not, the function does not set the alarm and returns an error. + * + * @param rtcBase The RTC base address pointer. + * @param date [in] pointer to structure where the alarm date and time + * details will be stored at. + * @return true: success in setting the RTC alarm + * false: error in setting the RTC alarm. + */ +bool RTC_HAL_SetAlarm(RTC_Type *rtcBase, const rtc_datetime_t * date); + +#if FSL_FEATURE_RTC_HAS_MONOTONIC +/*-------------------------------------------------------------------------------------------*/ +/* RTC Monotonic Counter*/ +/*-------------------------------------------------------------------------------------------*/ + +/*! + * @brief Reads the values of the Monotonic Counter High and Monotonic Counter Low and returns + * them as a single value. + * + * @param rtcBase The RTC base address pointer + * @param counter [out] pointer to variable where the value is stored. + */ +void RTC_HAL_GetMonotonicCounter(RTC_Type *rtcBase, uint64_t * counter); + +/*! + * @brief Writes values Monotonic Counter High and Monotonic Counter Low by decomposing + * the given single value. + * + * @param rtcBase The RTC base address pointer + * @param counter [in] pointer to variable where the value is stored. + */ +void RTC_HAL_SetMonotonicCounter(RTC_Type *rtcBase, const uint64_t * counter); + +/*! + * @brief Increments the Monotonic Counter by one. + * + * Increments the Monotonic Counter (registers RTC_MCLR and RTC_MCHR accordingly) by setting + * the monotonic counter enable (MER[MCE]) and then writing to the RTC_MCLR register. A write to the + * monotonic counter low that causes it to overflow also increments the monotonic counter high. + * + * @param rtcBase The RTC base address pointer + * + * @return true: success + * false: error occurred, either time invalid or monotonic overflow flag was found + */ +bool RTC_HAL_IncrementMonotonicCounter(RTC_Type *rtcBase); +#endif +/*! @}*/ + +/*! + * @name RTC register access functions + * @{ + */ + +/*! + * @brief Reads the value of the time seconds counter. + * + * The time counter reads as zero if either the SR[TOF] or the SR[TIF] is set. + * + * @param rtcBase The RTC base address pointer. + * + * @return contents of the seconds register. + */ +static inline uint32_t RTC_HAL_GetSecsReg(RTC_Type *rtcBase) +{ + return RTC_RD_TSR(rtcBase); +} + +/*! + * @brief Writes to the time seconds counter. + * + * When the time counter is enabled, the TSR is read only and increments + * once every second provided the SR[TOF] or SR[TIF] is not set. When the time counter + * is disabled, the TSR can be read or written. Writing to the TSR when the + * time counter is disabled clears the SR[TOF] and/or the SR[TIF]. Writing + * to the TSR register with zero is supported, but not recommended, since the TSR + * reads as zero when either the SR[TIF] or the SR[TOF] is set (indicating the time is + * invalid). + * + * @param rtcBase The RTC base address pointer. + * @param seconds [in] seconds value. + * + */ +static inline void RTC_HAL_SetSecsReg(RTC_Type *rtcBase, const uint32_t seconds) +{ + RTC_WR_TPR_TPR(rtcBase, (uint32_t)0x00000000U); + RTC_WR_TSR(rtcBase, seconds); +} + +/*! + * @brief Sets the time alarm and clears the time alarm flag. + * + * When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR] + * equals the TSR[TSR] and the TSR[TSR] increments. Writing to the TAR + * clears the SR[TAF]. + * + * @param rtcBase The RTC base address pointer. + * @param seconds [in] alarm value in seconds. + */ +static inline void RTC_HAL_SetAlarmReg(RTC_Type *rtcBase, const uint32_t seconds) +{ + RTC_WR_TAR(rtcBase, seconds); +} + +/*! + * @brief Gets the time alarm register contents. + * + * @param rtcBase The RTC base address pointer + * + * @return contents of the alarm register. + */ +static inline uint32_t RTC_HAL_GetAlarmReg(RTC_Type *rtcBase) +{ + return RTC_RD_TAR(rtcBase); +} + + +/*! + * @brief Reads the value of the time prescaler. + * + * The time counter reads as zero when either the SR[TOF] or the SR[TIF] is set. + * + * @param rtcBase The RTC base address pointer + * + * @return contents of the time prescaler register. + */ +static inline uint16_t RTC_HAL_GetPrescaler(RTC_Type *rtcBase) +{ + return RTC_RD_TPR_TPR(rtcBase); +} + +/*! + * @brief Sets the time prescaler. + * + * When the time counter is enabled, the TPR is read only and increments + * every 32.768 kHz clock cycle. When the time counter is disabled, the TPR + * can be read or written. The TSR[TSR] increments when bit 14 of the TPR + * transitions from a logic one to a logic zero. + * + * @param rtcBase The RTC base address pointer + * @param prescale Prescaler value + */ +static inline void RTC_HAL_SetPrescaler(RTC_Type *rtcBase, const uint16_t prescale) +{ + RTC_WR_TPR_TPR(rtcBase, prescale); +} + +/*-------------------------------------------------------------------------------------------*/ +/* RTC Time Compensation*/ +/*-------------------------------------------------------------------------------------------*/ + +/*! + * @brief Reads the time compensation register contents. + * + * @param rtcBase The RTC base address pointer + * + * @return time compensation register contents. + */ +static inline uint32_t RTC_HAL_GetCompensationReg(RTC_Type *rtcBase) +{ + return RTC_RD_TCR(rtcBase); +} + +/*! + * @brief Writes the value to the RTC TCR register. + * + * @param rtcBase The RTC base address pointer + * @param compValue value to be written to the compensation register. + */ +static inline void RTC_HAL_SetCompensationReg(RTC_Type *rtcBase, const uint32_t compValue) +{ + RTC_WR_TCR(rtcBase, compValue); +} + +/*! + * @brief Reads the current value of the compensation interval counter, which is the field CIC in the RTC TCR register. + * + * @param rtcBase The RTC base address pointer. + * + * @return compensation interval value. + */ +static inline uint8_t RTC_HAL_GetCompensationIntervalCounter(RTC_Type *rtcBase) +{ + return RTC_RD_TCR_CIC(rtcBase); +} + +/*! + * @brief Reads the current value used by the compensation logic for the present second interval. + * + * @param rtcBase The RTC base address pointer + * + * @return time compensation value + */ +static inline uint8_t RTC_HAL_GetTimeCompensationValue(RTC_Type *rtcBase) +{ + return RTC_RD_TCR_TCV(rtcBase); +} + +/*! + * @brief Reads the compensation interval register. + + * The value is the configured compensation interval in seconds from 1 to 256 to control + * how frequently the time compensation register should adjust the + * number of 32.768 kHz cycles in each second. The value is one + * less than the number of seconds (for example, zero means a + * configuration for a compensation interval of one second). + * + * @param rtcBase The RTC base address pointer. + * + * @return compensation interval in seconds. + */ +static inline uint8_t RTC_HAL_GetCompensationIntervalRegister(RTC_Type *rtcBase) +{ + return RTC_RD_TCR_CIR(rtcBase); +} + +/*! + * @brief Writes the compensation interval. + * + * This configures the compensation interval in seconds from 1 to 256 to control + * how frequently the TCR should adjust the number of 32.768 kHz + * cycles in each second. The value written should be one less than + * the number of seconds (for example, write zero to configure for + * a compensation interval of one second). This register is double + * buffered and writes do not take affect until the end of the + * current compensation interval. + * + * @param rtcBase The RTC base address pointer. + * @param value the compensation interval value. + */ +static inline void RTC_HAL_SetCompensationIntervalRegister(RTC_Type *rtcBase, const uint8_t value) +{ + RTC_WR_TCR_CIR(rtcBase, value); +} + +/*! + * @brief Reads the time compensation value which is the configured number + * of 32.768 kHz clock cycles in each second. + * + * @param rtcBase The RTC base address pointer + * + * @return time compensation value. + */ +static inline uint8_t RTC_HAL_GetTimeCompensationRegister(RTC_Type *rtcBase) +{ + return RTC_RD_TCR_TCR(rtcBase); +} + +/*! + * @brief Writes to the field Time Compensation Register (TCR) of the RTC Time Compensation Register (RTC_TCR). + * + * Configures the number of 32.768 kHz clock cycles in each second. This register is double + * buffered and writes do not take affect until the end of the + * current compensation interval. + * + * @param rtcBase The RTC base address pointer + * @param compValue value of the time compensation. + */ +static inline void RTC_HAL_SetTimeCompensationRegister(RTC_Type *rtcBase, const uint8_t compValue) +{ + RTC_WR_TCR_TCR(rtcBase, compValue); +} + +/*-------------------------------------------------------------------------------------------*/ +/* RTC Control*/ +/*-------------------------------------------------------------------------------------------*/ + +/*! + * @brief Enables/disables the oscillator configuration for the 2pF load. + * + * @param rtcBase The RTC base address pointer + * @param enable can be true or false + * -true: enables load + * -false: disables load. + */ +static inline void RTC_HAL_SetOsc2pfLoadCmd(RTC_Type *rtcBase, bool enable) +{ + RTC_BWR_CR_SC2P(rtcBase, enable); +} + +/*! + * @brief Reads the oscillator 2pF load configure bit. + * + * @param rtcBase The RTC base address pointer + * + * @return true: 2pF additional load enabled. + * false: 2pF additional load disabled. + */ +static inline bool RTC_HAL_GetOsc2pfLoad(RTC_Type *rtcBase) +{ + return (bool)RTC_BRD_CR_SC2P(rtcBase); +} + +/*! + * @brief Enables/disables the oscillator configuration for the 4pF load. + * + * @param rtcBase The RTC base address pointer + * @param enable can be true or false + * -true: enables load. + * -false: disables load + */ +static inline void RTC_HAL_SetOsc4pfLoadCmd(RTC_Type *rtcBase, bool enable) +{ + RTC_BWR_CR_SC4P(rtcBase, enable); +} + +/*! + * @brief Reads the oscillator 4pF load configure bit. + * + * @param rtcBase The RTC base address pointer + * + * @return true: 4pF additional load enabled. + * false: 4pF additional load disabled. + */ +static inline bool RTC_HAL_GetOsc4pfLoad(RTC_Type *rtcBase) +{ + return (bool)RTC_BRD_CR_SC4P(rtcBase); +} + +/*! + * @brief Enables/disables the oscillator configuration for the 8pF load. + * + * @param rtcBase The RTC base address pointer + * @param enable can be true or false + * -true: enables load. + * -false: disables load. + */ +static inline void RTC_HAL_SetOsc8pfLoadCmd(RTC_Type *rtcBase, bool enable) +{ + RTC_BWR_CR_SC8P(rtcBase, enable); +} + +/*! + * @brief Reads the oscillator 8pF load configure bit. + * + * @param rtcBase The RTC base address pointer + * + * @return true: 8pF additional load enabled. + * false: 8pF additional load disabled. + */ +static inline bool RTC_HAL_GetOsc8pfLoad(RTC_Type *rtcBase) +{ + return (bool)RTC_BRD_CR_SC8P(rtcBase); +} + +/*! + * @brief Enables/disables the oscillator configuration for the 16pF load. + * + * @param rtcBase The RTC base address pointer + * @param enable can be true or false + * -true: enables load. + * -false: disables load. + */ +static inline void RTC_HAL_SetOsc16pfLoadCmd(RTC_Type *rtcBase, bool enable) +{ + RTC_BWR_CR_SC16P(rtcBase, enable); +} + +/*! + * @brief Reads the oscillator 16pF load configure bit. + * + * @param rtcBase The RTC base address pointer + * + * @return true: 16pF additional load enabled. + * false: 16pF additional load disabled. + */ +static inline bool RTC_HAL_GetOsc16pfLoad(RTC_Type *rtcBase) +{ + return (bool)RTC_BRD_CR_SC16P(rtcBase); +} + +/*! + * @brief Enables/disables the 32 kHz clock output to other peripherals. + * + * @param rtcBase The RTC base address pointer + * @param enable can be true or false + * -true: enables clock out. + * -false: disables clock out. + */ +static inline void RTC_HAL_SetClockOutCmd(RTC_Type *rtcBase, bool enable) +{ + RTC_BWR_CR_CLKO(rtcBase, !enable); +} + +/*! + * @brief Reads the RTC_CR CLKO bit. + * + * @param rtcBase The RTC base address pointer + * + * @return true: 32 kHz clock is not output to other peripherals. + * false: 32 kHz clock is output to other peripherals. + */ +static inline bool RTC_HAL_GetClockOutCmd(RTC_Type *rtcBase) +{ + return (bool)RTC_BRD_CR_CLKO(rtcBase); +} + +/*! + * @brief Enables/disables the oscillator. + * + * After enabling, waits for the oscillator startup time before enabling the + * time counter to allow the 32.768 kHz clock time to stabilize. + * + * @param rtcBase The RTC base address pointer + * @param enable can be true or false + * -true: enables oscillator. + * -false: disables oscillator. + */ +static inline void RTC_HAL_SetOscillatorCmd(RTC_Type *rtcBase, bool enable) +{ + RTC_BWR_CR_OSCE(rtcBase, enable); +} + +/*! + * @brief Reads the RTC_CR OSCE bit. + * + * @param rtcBase The RTC base address pointer + * + * @return true: 32.768 kHz oscillator is enabled + * false: 32.768 kHz oscillator is disabled. + */ +static inline bool RTC_HAL_IsOscillatorEnabled(RTC_Type *rtcBase) +{ + return (bool)RTC_BRD_CR_OSCE(rtcBase); +} + +/*! + * @brief Performs a software reset on the RTC module. + * + * This resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR + * registers. The SWR bit is cleared after VBAT POR and by software + * explicitly clearing it. + * Note: access control features (RTC_WAR and RTC_RAR registers) + * are not available in all MCUs. + * + * @param rtcBase The RTC base address pointer + */ +static inline void RTC_HAL_SoftwareReset(RTC_Type *rtcBase) +{ + RTC_BWR_CR_SWR(rtcBase, 1u); +} + +/*! + * @brief Clears the software reset flag. + * + * @param rtcBase The RTC base address pointer + */ +static inline void RTC_HAL_SoftwareResetFlagClear(RTC_Type *rtcBase) +{ + RTC_BWR_CR_SWR(rtcBase, 0u); +} + +/*! + * @brief Reads the RTC_CR SWR bit. + * + * @param rtcBase The RTC base address pointer + * + * @return true: SWR is set. + * false: SWR is cleared. + */ +static inline bool RTC_HAL_ReadSoftwareResetStatus(RTC_Type *rtcBase) +{ + return (bool)RTC_BRD_CR_SWR(rtcBase); +} + +/*-------------------------------------------------------------------------------------------*/ +/* RTC Status*/ +/*-------------------------------------------------------------------------------------------*/ + +/*! + * @brief Reads the time counter status (enabled/disabled). + * + * @param rtcBase The RTC base address pointer + * + * @return -true: time counter is enabled, time seconds register and time + * prescaler register are not writeable, but increment. + * -false: time counter is disabled, time seconds register and + * time prescaler register are writeable, but do not increment. + */ +static inline bool RTC_HAL_IsCounterEnabled(RTC_Type *rtcBase) +{ + return (bool)RTC_BRD_SR_TCE(rtcBase); +} + +/*! + * @brief Changes the time counter status. + * + * @param rtcBase The RTC base address pointer + * @param enable can be true or false + * -true: enables the time counter + * -false: disables the time counter. + */ +static inline void RTC_HAL_EnableCounter(RTC_Type *rtcBase, bool enable) +{ + RTC_BWR_SR_TCE(rtcBase, enable); +} + +#if FSL_FEATURE_RTC_HAS_MONOTONIC +/*! + * @brief Reads the value of the Monotonic Overflow Flag (MOF). + * + * This flag is set when the monotonic counter is enabled and the monotonic + * counter high overflows. The monotonic counter does not increment and + * reads as zero when this bit is set. This bit is cleared by writing the monotonic + * counter high register when the monotonic counter is disabled. + * + * @param rtcBase The RTC base address pointer. + * + * @return -true: monotonic counter overflow has occurred and monotonic + * counter is read as zero. + * -false: No monotonic counter overflow has occurred. + */ +static inline bool RTC_HAL_IsMonotonicCounterOverflow(RTC_Type *rtcBase) +{ + return (bool)RTC_BRD_SR_MOF(rtcBase); +} +#endif + +/*! + * @brief Checks whether the configured time alarm has occurred. + * + * Reads time alarm flag (TAF). This flag is set when the time + * alarm register (TAR) equals the time seconds register (TSR) and + * the TSR increments. This flag is cleared by writing the TAR register. + * + * @param rtcBase The RTC base address pointer. + * + * @return -true: time alarm has occurred. + * -false: no time alarm occurred. + */ +static inline bool RTC_HAL_HasAlarmOccured(RTC_Type *rtcBase) +{ + return (bool)RTC_BRD_SR_TAF(rtcBase); +} + +/*! + * @brief Checks whether the time has been marked as invalid. + * + * Reads the value of RTC Status Register (RTC_SR), field Time + * Invalid Flag (TIF). This flag is set on VBAT POR or software + * reset. The TSR and TPR do not increment and read as zero when + * this bit is set. This flag is cleared by writing the TSR + * register when the time counter is disabled. + * + * @param rtcBase The RTC base address pointer. + * + * @return -true: time is INVALID and time counter is zero. + * -false: time is valid. + */ +static inline bool RTC_HAL_IsTimeInvalid(RTC_Type *rtcBase) +{ + return (bool)RTC_BRD_SR_TIF(rtcBase); +} + +/*-------------------------------------------------------------------------------------------*/ +/* RTC Interrupt Enable*/ +/*-------------------------------------------------------------------------------------------*/ + +/*! + * @brief Checks whether the Time Seconds Interrupt is enabled/disabled. + * + * Reads the value of field Time Seconds Interrupt Enable (TSIE)of the RTC Interrupt Enable Register (RTC_IER). + * The seconds interrupt is an edge-sensitive + * interrupt with a dedicated interrupt vector. It is generated once a second + * and requires no software overhead (there is no corresponding status flag to + * clear). + * + * @param rtcBase The RTC base address pointer + * + * @return -true: Seconds interrupt is enabled. + * -false: Seconds interrupt is disabled. + */ +static inline bool RTC_HAL_IsSecsIntEnabled(RTC_Type *rtcBase) +{ + return (bool)RTC_BRD_IER_TSIE(rtcBase); +} + +/*! + * @brief Enables/disables the Time Seconds Interrupt. + * + * Writes to the field Time Seconds + * Interrupt Enable (TSIE) of the RTC Interrupt Enable Register (RTC_IER). + * Note: The seconds interrupt is an edge-sensitive interrupt with a + * dedicated interrupt vector. It is generated once a second and + * requires no software overhead (there is no corresponding status + * flag to clear). + * + * @param rtcBase The RTC base address pointer + * @param enable can be true or false + * -true: Seconds interrupt is enabled. + * -false: Seconds interrupt is disabled. + */ +static inline void RTC_HAL_SetSecsIntCmd(RTC_Type *rtcBase, bool enable) +{ + RTC_BWR_IER_TSIE(rtcBase, (uint32_t) enable); +} + +/*! + * @brief Checks whether the Time Alarm Interrupt is enabled/disabled. + * + * Reads the field Time Alarm Interrupt Enable (TAIE) value of the RTC Interrupt Enable Register (RTC_IER). + * + * @param rtcBase The RTC base address pointer + * + * @return true: Time alarm flag does generate an interrupt. + * false: Time alarm flag does not generate an interrupt. + */ +static inline bool RTC_HAL_ReadAlarmInt(RTC_Type *rtcBase) +{ + return (bool)RTC_BRD_IER_TAIE(rtcBase); +} + +/*! + * @brief Enables/disables the Time Alarm Interrupt. + * + * Writes to the field Time Alarm + * Interrupt Enable (TAIE) of the RTC Interrupt Enable Register (RTC_IER). + * + * @param rtcBase The RTC base address pointer + * @param enable can be true or false + * -true: Time alarm flag does generate an interrupt. + * -false: Time alarm flag does not generate an interrupt. + */ +static inline void RTC_HAL_SetAlarmIntCmd(RTC_Type *rtcBase, bool enable) +{ + RTC_BWR_IER_TAIE(rtcBase, (uint32_t) enable); +} + +/*! + * @brief Enables/disables the Time Overflow Interrupt. + * + * Writes to the field Time Overflow Interrupt Enable (TOIE) of the RTC Interrupt Enable Register (RTC_IER). + * + * @param rtcBase The RTC base address pointer + * @param enable can be true or false + * -true: Time overflow flag does generate an interrupt. + * -false: Time overflow flag does not generate an interrupt. + */ +static inline void RTC_HAL_SetTimeOverflowIntCmd(RTC_Type *rtcBase, bool enable) +{ + RTC_BWR_IER_TOIE(rtcBase, (uint32_t) enable); +} + +/*! + * @brief Enables/disables the Time Invalid Interrupt. + * + * Writes to the field Time Invalid + * Interrupt Enable (TIIE) of the RTC Interrupt Enable Register (RTC_IER). + * + * @param rtcBase The RTC base address pointer + * @param enable can be true or false + * -true: Time invalid flag does generate an interrupt. + * -false: Time invalid flag does not generate an interrupt. + */ +static inline void RTC_HAL_SetTimeInvalidIntCmd(RTC_Type *rtcBase, bool enable) +{ + RTC_BWR_IER_TIIE(rtcBase, (uint32_t) enable); +} + +#if FSL_FEATURE_RTC_HAS_MONOTONIC + +/*-------------------------------------------------------------------------------------------*/ +/* RTC Monotonic Enable*/ +/*-------------------------------------------------------------------------------------------*/ + +/*! + * @brief Reads the Monotonic Counter Enable bit. + * + * @param rtcBase The RTC base address pointer + * + * @return true: This means writing to the monotonic counter increments the counter by one and + * the value written is ignored. + * false: This means writing to the monotonic counter loads the counter with the + * value written. + */ +static inline bool RTC_HAL_ReadMonotonicEnable(RTC_Type *rtcBase) +{ + /* Reads value of the RTC_MER register, field Monotonic Counter Enable (MCE). */ + return (bool)RTC_BRD_MER_MCE(rtcBase); +} + +/*! + * @brief Changes the state of Monotonic Counter Enable bit. + * + * @param rtcBase The RTC base address pointer + * @param enable value to be written to the MER[MCE] bit + * true: Set the bit to 1 which means writing to the monotonic counter will increment + * the counter by one and the value written will be ignored. + * false: Set the bit to 0 which means writing to the monotonic counter loads the counter + * with the value written. + */ +static inline void RTC_HAL_SetMonotonicEnableCmd(RTC_Type *rtcBase, bool enable) +{ + /* Writes to the RTC_MER registers Monotonic Counter Enable (MCE) bit.*/ + RTC_BWR_MER_MCE(rtcBase, (uint32_t)enable); +} + +/*! + * @brief Reads the values of the Monotonic Counter Low register. + * + * @param rtcBase The RTC base address pointer + * + * @return Monotonic Counter Low value. + */ +static inline uint32_t RTC_HAL_GetMonotonicCounterLow(RTC_Type *rtcBase) +{ + return RTC_RD_MCLR(rtcBase); +} + +/*! + * @brief Reads the values of the Monotonic Counter High register. + * + * @param rtcBase The RTC base address pointer + * + * @return Monotonic Counter High value. + */ +static inline uint32_t RTC_HAL_GetMonotonicCounterHigh(RTC_Type *rtcBase) +{ + return RTC_RD_MCHR(rtcBase); +} + +/*! + * @brief Writes values of the Monotonic Counter Low register. + * + * @param rtcBase The RTC base address pointer + * @param counter [in] Monotonic Counter Low value to be stored. + */ +static inline void RTC_HAL_SetMonotonicCounterLow(RTC_Type *rtcBase, const uint32_t counter) +{ + /* enable writing to the counter*/ + RTC_BWR_MER_MCE(rtcBase, 0U); + RTC_WR_MCLR(rtcBase, counter); +} + +/*! + * @brief Writes values of the Monotonic Counter High register. + * + * @param rtcBase The RTC base address pointer + * @param counter [in] Monotonic Counter High value to be stored. + */ +static inline void RTC_HAL_SetMonotonicCounterHigh(RTC_Type *rtcBase, const uint32_t counter) +{ + /* enable writing to the counter*/ + RTC_BWR_MER_MCE(rtcBase, 0U); + RTC_WR_MCHR(rtcBase, counter); +} + +#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */ + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif + + +/*! @}*/ + +#endif /* FSL_FEATURE_SOC_RTC_COUNT */ + +#endif /* __FSL_RTC_HAL_H__*/ + +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_sai_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_sai_hal.h new file mode 100755 index 0000000..1a2c0c6 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_sai_hal.h @@ -0,0 +1,1038 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FSL_SAI_HAL_H__ +#define __FSL_SAI_HAL_H__ + + +#include <string.h> +#include <stdbool.h> +#include <assert.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_I2S_COUNT + + +/*! + * @addtogroup sai_hal + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Define the bus type of sai */ +typedef enum _sai_protocol +{ + kSaiBusI2SLeft = 0x0u, /*!< Uses I2S left aligned format. @internal gui name="Left aligned" */ + kSaiBusI2SRight = 0x1u,/*!< Uses I2S right aligned format. @internal gui name="Right aligned" */ + kSaiBusI2SType = 0x2u, /*!< Uses I2S format. @internal gui name="I2S format" */ + kSaiBusPCMA = 0x3u, /*!< Uses I2S PCM A format. @internal gui name="PCM A format" */ + kSaiBusPCMB = 0x4u, /*!< Uses I2S PCM B format. @internal gui name="PCM B format" */ + kSaiBusAC97 = 0x5u /*!< Uses I2S AC97 format. @internal gui name="AC97 format" */ + } sai_protocol_t; + +/*! @brief Master or slave mode */ +typedef enum _sai_master_slave +{ + kSaiMaster = 0x0u,/*!< Master mode */ + kSaiSlave = 0x1u/*!< Slave mode */ +} sai_master_slave_t; + +typedef enum _sai_mono_stereo +{ + kSaiMono = 0x0u, /*!< 1 channel in frame. @internal gui name="Mono" */ + kSaiStereo = 0x1u /*!< 2 channels in frame. @internal gui name="Stereo" */ +} sai_mono_stereo_t; + +/*! @brief Synchronous or asynchronous mode */ +typedef enum _sai_sync_mode +{ + kSaiModeAsync = 0x0u,/*!< Asynchronous mode @internal gui name="Asynchronous" */ + kSaiModeSync = 0x1u,/*!< Synchronous mode (with receiver or transmit) @internal gui name="Synchronous" */ + kSaiModeSyncWithOtherTx = 0x2u,/*!< Synchronous with another SAI transmit @internal gui name="Synchronous with another Tx" */ + kSaiModeSyncWithOtherRx = 0x3u/*!< Synchronous with another SAI receiver @internal gui name="Synchronous with another Rx" */ +} sai_sync_mode_t; + +/*! @brief Mater clock source */ +typedef enum _sai_mclk_source +{ + kSaiMclkSourceSysclk = 0x0u,/*!< Master clock from the system clock @internal gui name="System clock" */ + kSaiMclkSourceSelect1 = 0x1u,/*!< Master clock from source 1 @internal gui name="Input clock 1" */ + kSaiMclkSourceSelect2 = 0x2u,/*!< Master clock from source 2 @internal gui name="Input clock 2" */ + kSaiMclkSourceSelect3 = 0x3u/*!< Master clock from source 3 @internal gui name="Input clock 3" */ +} sai_mclk_source_t; + +/*! @brief Bit clock source */ +typedef enum _sai_bclk_source +{ + kSaiBclkSourceBusclk = 0x0u,/*!< Bit clock using bus clock. @internal gui name="Bus clock" */ + kSaiBclkSourceMclkDiv = 0x1u,/*!< Bit clock using master clock divider. @internal gui name="Master clock" */ + kSaiBclkSourceOtherSai0 = 0x2u,/*!< Bit clock from other SAI device. @internal gui name="From SAI0" */ + kSaiBclkSourceOtherSai1 = 0x3u/*!< Bit clock from other SAI device. @internal gui name="From SAI1" */ +} sai_bclk_source_t; + +/*! @brief The SAI state flag. */ +typedef enum _sai_interrupt_request +{ + kSaiIntrequestWordStart = 0x1000u,/*!< Word start flag, means the first word in a frame detected */ + kSaiIntrequestSyncError = 0x800u,/*!< Sync error flag, means the sync error is detected */ + kSaiIntrequestFIFOWarning = 0x200u,/*!< FIFO warning flag, means the FIFO is empty */ + kSaiIntrequestFIFOError = 0x400u,/*!< FIFO error flag */ + kSaiIntrequestFIFORequest = 0x100u,/*!< FIFO request, means reached watermark */ + kSaiIntRequestAll = 0x1F00 /* All interrupt source */ +} sai_interrupt_request_t; + +/*! @brief The DMA request sources */ +typedef enum _sai_dma_request +{ + kSaiDmaReqFIFOWarning = 0x2u,/*!< FIFO warning caused by the DMA request */ + kSaiDmaReqFIFORequest = 0x1u,/*!< FIFO request caused by the DMA request */ + kSaiDmaReqAll = 0x3u /* All dma request source */ +} sai_dma_request_t; + +/*! @brief The SAI state flag */ +typedef enum _sai_state_flag +{ + kSaiStateFlagWordStart = 0x100000u,/*!< Word start flag, means the first word in a frame detected. */ + kSaiStateFlagSyncError = 0x80000u,/*!< Sync error flag, means the sync error is detected */ + kSaiStateFlagFIFOError = 0x40000u,/*!< FIFO error flag */ + kSaiStateFlagFIFORequest = 0x10000u, /*!< FIFO request flag. */ + kSaiStateFlagFIFOWarning = 0x20000u, /*!< FIFO warning flag. */ + kSaiStateFlagSoftReset = 0x1000000u, /*!< Software reset flag */ + kSaiStateFlagAll = 0x11F0000u /*!< All flags. */ +} sai_state_flag_t; + +/*! @brief The reset type */ +typedef enum _sai_reset_type +{ + kSaiResetTypeSoftware = 0x1000000u,/*!< Software reset, reset the logic state */ + kSaiResetTypeFIFO = 0x2000000u,/*!< FIFO reset, reset the FIFO read and write pointer */ + kSaiResetAll = 0x3000000u /*!< All reset. */ +} sai_reset_type_t; + +/* + * @brief The SAI running mode + * The mode includes normal mode, debug mode, and stop mode. + */ +typedef enum _sai_running_mode +{ + kSaiRunModeDebug = 0x0,/*!< In debug mode */ + kSaiRunModeStop = 0x1/*!< In stop mode */ +} sai_run_mode_t; + +#if FSL_FEATURE_SAI_HAS_FIFO_PACKING + +/* + * @brief The SAI packing mode + * The mode includes 8 bit and 16 bit packing. + */ +typedef enum _sai_fifo_packing +{ + kSaiFifoPackingDisabled = 0x0, /*!< Packing disabled. */ + kSaiFifoPacking8bit = 0x2,/*!< 8 bit packing enabled. */ + kSaiFifoPacking16bit = 0x3 /*!< 16bit packing enabled. */ +} sai_fifo_packing_t; +#endif + +/*! @brief SAI clock configuration structure. */ +typedef struct SaiClockSetting +{ + sai_mclk_source_t mclk_src; /*!< Master clock source. */ + sai_bclk_source_t bclk_src; /*!< Bit clock source. */ + uint32_t mclk_src_freq; /*!< Master clock source frequency. */ + uint32_t mclk; /*!< Master clock frequency. */ + uint32_t bclk; /*!< Bit clock frequency. */ + uint32_t bclk_src_freq; /* Bit clock source frequency. */ +} sai_clock_setting_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! +* @name Module control +* @{ +*/ + +/*! + * @brief Initializes the SAI Tx. + * + * The initialization resets the SAI module by setting the SR bit of TCSR register. + * Note that the function writes 0 to every control registers. + * @param base Register base address of SAI module. + */ +void SAI_HAL_TxInit(I2S_Type * base); + +/*! + * @brief Initializes the SAI Rx. + * + * The initialization resets the SAI module by setting the SR bit of RCSR register. + * Note that the function writes 0 to every control registers. + * @param base Register base address of SAI module. + */ +void SAI_HAL_RxInit(I2S_Type * base); + +/*! + * @brief Sets Tx protocol relevant settings. + * + * The bus mode means which protocol SAI uses. It can be I2S left, right and so on. Each protocol + * has a different configuration on bit clock and frame sync. + * @param base Register base address of SAI module. + * @param protocol The protocol selection. It can be I2S left aligned, I2S right aligned, etc. + */ +void SAI_HAL_TxSetProtocol(I2S_Type * base, sai_protocol_t protocol); + +/*! + * @brief Sets Rx protocol relevant settings. + * + * The bus mode means which protocol SAI uses. It can be I2S left, right and so on. Each protocol + * has a different configuration on bit clock and frame sync. + * @param base Register base address of SAI module. + * @param protocol The protocol selection. It can be I2S left aligned, I2S right aligned, etc. + */ +void SAI_HAL_RxSetProtocol(I2S_Type * base, sai_protocol_t protocol); + +/*! + * @brief Sets master or slave mode. + * + * The function determines master or slave mode. Master mode provides its + * own clock and slave mode uses an external clock. + * @param base Register base address of SAI module. + * @param master_slave_mode Mater or slave mode. + */ +void SAI_HAL_TxSetMasterSlave(I2S_Type * base, sai_master_slave_t master_slave_mode); + +/*! + * @brief Sets master or slave mode. + * + * The function determines master or slave mode. Master mode provides its + * own clock and slave mode uses external clock. + * @param base Register base address of SAI module. + * @param master_slave_mode Mater or slave mode. + */ +void SAI_HAL_RxSetMasterSlave(I2S_Type * base, sai_master_slave_t master_slave_mode); + +/*! @}*/ + +/*! +* @name Overall Clock configuration +* @{ +*/ + +/*! + * @brief Setup clock for SAI Tx. + * + * This function can sets the clock settings according to the configure structure. + * In this configuration setting structure, users can set clock source, clock source frequency, + * and frequency of master clock and bit clock. + * If bit clock source is master clock, the master clock frequency should equal to bit clock source + * frequency. If bit clock source is not master clock, then settings about master clock have no + * effect to the setting. + * @param base Register base address of SAI module. + * @param clk_config Pointer to sai clock configuration structure. + */ +void SAI_HAL_TxClockSetup(I2S_Type * base, sai_clock_setting_t *clk_config); + +/*! + * @brief Setup clock for SAI Rx. + * + * This function can sets the clock settings according to the configure structure. + * In this configuration setting structure, users can set clock source, clock source frequency, + * and frequency of master clock and bit clock. + * If bit clock source is master clock, the master clock frequency should equal to bit clock source + * frequency. If bit clock source is not master clock, then settings about master clock have no + * effect to the setting. + * @param base Register base address of SAI module. + * @param clk_config Pointer to sai clock configuration structure. + */ +void SAI_HAL_RxClockSetup(I2S_Type * base, sai_clock_setting_t *clk_config); + +/*! @}*/ + +/*! +* @name Master clock configuration +* @{ +*/ + +/*! + * @brief Sets the master clock source. + * + * The source of the clock is different from socs. + * This function sets the clock source for SAI master clock source. + * Master clock is used to produce the bit clock for the data transfer. + * @param base Register base address of SAI module. + * @param source Mater clock source + */ +static inline void SAI_HAL_SetMclkSrc(I2S_Type * base, sai_mclk_source_t source) +{ + I2S_BWR_MCR_MICS(base,source); +} + +/*! + * @brief Gets the master clock source. + * + * The source of the clock is different from socs. + * This function gets the clock source for SAI master clock source. + * Master clock is used to produce the bit clock for the data transfer. + * @param base Register base address of SAI module. + * @return Mater clock source + */ +static inline uint32_t SAI_HAL_GetMclkSrc(I2S_Type * base) +{ + return I2S_BRD_MCR_MICS(base); +} + +/*! + * @brief Enable or disable MCLK internal. + * + * This function enable or disable internal MCLK. + * @param base Register base address of SAI module. + * @param enable True means enable, false means disable. + */ +static inline void SAI_HAL_SetMclkDividerCmd(I2S_Type * base, bool enable) +{ + I2S_BWR_MCR_MOE(base,enable); +} + +#if FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER +/*! + * @brief Sets the divider of the master clock. + * + * Using the divider to get the master clock frequency wanted from the source. + * mclk = clk_source * fract/divide. The input is the master clock frequency needed and the source clock frequency. + * The master clock is decided by the sample rate and the multi-clock number. + * Notice that mclk should less than src_clk, or it would do hang as the HW refuses to write in this situation. + * @param base Register base address of SAI module. + * @param mclk Master clock frequency needed. + * @param src_clk The source clock frequency. + */ +void SAI_HAL_SetMclkDiv(I2S_Type * base, uint32_t mclk, uint32_t src_clk); +#endif + +/*! @}*/ + +/*! +* @name Bit clock configuration +* @{ +*/ + +/*! + * @brief Sets the bit clock source of Tx. It is generated by the master clock, bus clock and other devices. + * + * The function sets the source of the bit clock. The bit clock can be produced by the master + * clock and from the bus clock or other SAI Tx/Rx. Tx and Rx in the SAI module use the same bit + * clock either from Tx or Rx. + * @param base Register base address of SAI module. + * @param source Bit clock source. + */ +static inline void SAI_HAL_TxSetBclkSrc(I2S_Type * base, sai_bclk_source_t source) +{ + I2S_BWR_TCR2_MSEL(base,source); +} + +/*! + * @brief Sets bit clock source of the Rx. It is generated by the master clock, bus clock and other devices. + * + * The function sets the source of the bit clock. The bit clock can be produced by the master + * clock, and from the bus clock or other SAI Tx/Rx. Tx and Rx in the SAI module use the same bit + * clock either from Tx or Rx. + * @param base Register base address of SAI module. + * @param source Bit clock source. + */ +static inline void SAI_HAL_RxSetBclkSrc(I2S_Type * base, sai_bclk_source_t source) +{ + I2S_BWR_RCR2_MSEL(base,source); +} + +/*! + * @brief Gets the bit clock source of Tx. It is generated by the master clock, bus clock and other devices. + * + * The function gets the source of the bit clock. The bit clock can be produced by the master + * clock and from the bus clock or other SAI Tx/Rx. Tx and Rx in the SAI module use the same bit + * clock either from Tx or Rx. + * @param base Register base address of SAI module. + * @return Bit clock source. + */ +static inline uint32_t SAI_HAL_TxGetBclkSrc(I2S_Type * base) +{ + return I2S_BRD_TCR2_MSEL(base); +} + +/*! + * @brief Gets bit clock source of the Rx. It is generated by the master clock, bus clock and other devices. + * + * The function gets the source of the bit clock. The bit clock can be produced by the master + * clock, and from the bus clock or other SAI Tx/Rx. Tx and Rx in the SAI module use the same bit + * clock either from Tx or Rx. + * @param base Register base address of SAI module. + * @return Bit clock source. + */ +static inline uint32_t SAI_HAL_RxGetBclkSrc(I2S_Type * base) +{ + return I2S_BRD_RCR2_MSEL(base); +} + +/*! + * @brief Sets the Tx bit clock divider value. + * + * bclk = mclk / divider. At the same time, bclk = sample_rate * channel * bits. This means + * how much time is needed to transfer one bit. + * Notice: The function is called while the bit clock source is the master clock. + * @param base Register base address of SAI module. + * @param divider The divide number of bit clock. + */ +static inline void SAI_HAL_TxSetBclkDiv(I2S_Type * base, uint32_t divider) +{ + I2S_BWR_TCR2_DIV(base,divider/2 -1); +} + +/*! + * @brief Sets the Rx bit clock divider value. + * + * bclk = mclk / divider. At the same time, bclk = sample_rate * channel * bits. This means + * how much time is needed to transfer one bit. + * Notice: The function is called while the bit clock source is the master clock. + * @param base Register base address of SAI module. + * @param divider The divide number of bit clock. + */ +static inline void SAI_HAL_RxSetBclkDiv(I2S_Type * base, uint32_t divider) +{ + I2S_BWR_RCR2_DIV(base,divider/2 -1); +} + +/*! + * @brief Enables or disables the Tx bit clock input bit. + * + * @param saiBaseAddr Register base address of SAI module. + * @param enable True means enable, false means disable. + */ +static inline void SAI_HAL_TxSetBclkInputCmd(I2S_Type * base, bool enable) +{ + I2S_BWR_TCR2_BCI(base,enable); +} + +/*! + * @brief Enables or disables the Rx bit clock input bit. + * + * @param saiBaseAddr Register base address of SAI module. + * @param enable True means enable, false means disable. + */ +static inline void SAI_HAL_RxSetBclkInputCmd(I2S_Type * base, bool enable) +{ + I2S_BWR_RCR2_BCI(base,enable); +} +/*! + * @brief Sets the Tx bit clock swap. + * + * This field swaps the bit clock used by the transmitter. When the transmitter is configured in + * asynchronous mode and this bit is set, the transmitter is clocked by the receiver bit clock. + * This allows the transmitter and receiver to share the same bit clock, but the transmitter + * continues to use the transmit frame sync (SAI_TX_SYNC). + * When the transmitter is configured in synchronous mode, the transmitter BCS field and receiver + * BCS field must be set to the same value. When both are set, the transmitter and receiver are both + * clocked by the transmitter bit clock (SAI_TX_BCLK) but use the receiver frame sync (SAI_RX_SYNC). + * @param saiBaseAddr Register base address of SAI module. + * @param enable True means swap bit closk, false means no swap. + */ +static inline void SAI_HAL_TxSetSwapBclkCmd(I2S_Type * base, bool enable) +{ + I2S_BWR_TCR2_BCS(base,enable); +} + +/*! + * @brief Sets the Rx bit clock swap. + * + * This field swaps the bit clock used by the receiver. When the receiver is configured in + * asynchronous mode and this bit is set, the receiver is clocked by the transmitter bit clock + * (SAI_TX_BCLK). This allows the transmitter and receiver to share the same bit clock, but the + * receiver continues to use the receiver frame sync (SAI_RX_SYNC). + * When the receiver is configured in synchronous mode, the transmitter BCS field and receiver BCS + * field must be set to the same value. When both are set, the transmitter and receiver are both + * clocked by the receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync (SAI_TX_SYNC). + * @param saiBaseAddr Register base address of SAI module. + * @param enable True means swap bit closk, false means no swap. + */ +static inline void SAI_HAL_RxSetSwapBclkCmd(I2S_Type * base, bool enable) +{ + I2S_BWR_RCR2_BCS(base, enable); +} +/*! @} */ + +/*! +* @name Mono or stereo configuration +* @{ +*/ + +/*! + * @brief Set Tx audio channel number. Can be mono or stereo. + * + * @param base Register base address of SAI module. + * @param mono_stereo Mono or stereo mode. + */ +void SAI_HAL_TxSetMonoStereo(I2S_Type * base, sai_mono_stereo_t mono_stereo); + +/*! + * @brief Set Rx audio channel number. Can be mono or stereo. + * + * @param base Register base address of SAI module. + * @param mono_stereo Mono or stereo mode. + */ +void SAI_HAL_RxSetMonoStereo(I2S_Type * base, sai_mono_stereo_t mono_stereo); + +/*! @} */ + +/*! +* @name Word configurations +* @{ +*/ + +/*! + * @brief Set Tx word width. + * + * This interface is for i2s and PCM series protocol, it would set the width of first word and other word + * the same. At the same time, for i2s series protocol, it will set frame sync width the equal to the + * word width. + * @param base Register base address of SAI module. + * @param protocol Protocol used for tx now. + * @param bits Tx word width. + */ +void SAI_HAL_TxSetWordWidth(I2S_Type * base, sai_protocol_t protocol, uint32_t bits); + +/*! + * @brief Set Rx word width. + * + * This interface is for i2s and PCM series protocol, it would set the width of first word and other word + * the same. At the same time, for i2s series protocol, it will set frame sync width the equal to the + * word width. + * @param base Register base address of SAI module. + * @param protocol Protocol used for rx now. + * @param bits Rx word width. + */ +void SAI_HAL_RxSetWordWidth(I2S_Type * base, sai_protocol_t protocol, uint32_t bits); + +/*!@}*/ + +#if (FSL_FEATURE_SAI_FIFO_COUNT > 1) +/*! +* @name watermark settings +* @{ +*/ + +/*! + * @brief Sets the Tx watermark value. + * + * While the value in the FIFO is less or equal to the watermark , it generates an interrupt + * request or a DMA request. The watermark value cannot be greater than the depth of FIFO. + * @param base Register base address of SAI module. + * @param watermark Watermark value of a FIFO. + */ +static inline void SAI_HAL_TxSetWatermark(I2S_Type * base, uint32_t watermark) +{ + I2S_BWR_TCR1_TFW(base, watermark); +} + +/*! + * @brief Sets the Tx watermark value. + * + * While the value in the FIFO is more or equal to the watermark , it generates an interrupt + * request or a DMA request. The watermark value cannot be greater than the depth of FIFO. + * @param base Register base address of SAI module. + * @param watermark Watermark value of a FIFO. + */ +static inline void SAI_HAL_RxSetWatermark(I2S_Type * base, uint32_t watermark) +{ + I2S_BWR_RCR1_RFW(base, watermark); +} + +/*! + * @brief Gets the Tx watermark value. + * + * @param base Register base address of SAI module. + * @return The Tx watermark value. + */ +static inline uint32_t SAI_HAL_TxGetWatermark(I2S_Type * base) +{ + return I2S_BRD_TCR1_TFW(base); +} + +/*! + * @brief Gets the Rx watermark value. + * + * @param base Register base address of SAI module. + * @return The Tx watermark value. + */ +static inline uint32_t SAI_HAL_RxGetWatermark(I2S_Type * base) +{ + return I2S_BRD_RCR1_RFW(base); +} + +#endif + +/*! @}*/ + +/*! + * @brief SAI Tx sync mode setting. + * + * The mode can be asynchronous mode, synchronous, or synchronous with another SAI device. + * When configured for a synchronous mode of operation, the receiver must be configured for the + * asynchronous operation. + * @param base Register base address of SAI module. + * @param sync_mode Synchronous mode or Asynchronous mode. + */ +void SAI_HAL_TxSetSyncMode(I2S_Type * base, sai_sync_mode_t sync_mode); + +/*! + * @brief SAI Rx sync mode setting. + * + * The mode can be asynchronous mode, synchronous, or synchronous with another SAI device. + * When configured for a synchronous mode of operation, the receiver must be configured for the + * asynchronous operation. + * @param base Register base address of SAI module. + * @param sync_mode Synchronous mode or Asynchronous mode. + */ +void SAI_HAL_RxSetSyncMode(I2S_Type * base, sai_sync_mode_t sync_mode); + +#if (FSL_FEATURE_SAI_FIFO_COUNT > 1) +/*! + * @brief Gets the Tx FIFO read and write pointer. + * + * It is used to determine whether the FIFO is full or empty and know how much space there is for FIFO. + * If read_ptr == write_ptr, the FIFO is empty. While the bit of the read_ptr and the write_ptr are + * equal except for the MSB, the FIFO is full. + * @param base Register base address of SAI module. + * @param fifo_channel FIFO channel selected. + * @param r_ptr Pointer to get tx fifo read pointer. + * @param w_ptr Pointer to get tx fifo write pointer. + */ +void SAI_HAL_TxGetFifoWRPointer(I2S_Type * base, uint32_t fifo_channel, + uint32_t * r_ptr, uint32_t * w_ptr); + +/*! + * @brief Gets the Rx FIFO read and write pointer. + * + * It is used to determine whether the FIFO is full or empty and know how much space there is for FIFO. + * If read_ptr == write_ptr, the FIFO is empty. While the bit of the read_ptr and the write_ptr are + * equal except for the MSB, the FIFO is full. + * @param base Register base address of SAI module. + * @param fifo_channel FIFO channel selected. + * @param r_ptr Pointer to get rx fifo read pointer. + * @param w_ptr Pointer to get rx fifo write pointer. + */ +void SAI_HAL_RxGetFifoWRPointer(I2S_Type * base, uint32_t fifo_channel, + uint32_t * r_ptr, uint32_t * w_ptr); +#endif + +/*! + * @brief Gets the TDR register address. + * + * This function determines the dest/src address of the DMA transfer. + * @param base Register base address of SAI module. + * @param fifo_channel FIFO channel selected. + * @return TDR register or RDR register address + */ +static inline uint32_t SAI_HAL_TxGetFifoAddr(I2S_Type * base, uint32_t fifo_channel) +{ + return (uint32_t)(&I2S_TDR_REG(base, fifo_channel)); +} + +/*! + * @brief Gets the RDR register address. + * + * This function determines the dest/src address of the DMA transfer. + * @param base Register base address of SAI module. + * @param fifo_channel FIFO channel selected. + * @return TDR register or RDR register address + */ +static inline uint32_t SAI_HAL_RxGetFifoAddr(I2S_Type * base, uint32_t fifo_channel) +{ + return (uint32_t)(&I2S_RDR_REG(base, fifo_channel)); +} + +/*! + * @brief Enables the SAI Tx module. + * + * Enables the Tx. This function enables both the bit clock and the transfer channel. + * @param base Register base address of SAI module. + */ +static inline void SAI_HAL_TxEnable(I2S_Type * base) +{ + I2S_BWR_TCSR_BCE(base,true); + I2S_BWR_TCSR_TE(base,true); +} + +/*! + * @brief Enables the SAI Rx module. + * + * Enables the Rx. This function enables both the bit clock and the receive channel. + * @param base Register base address of SAI module. + */ +static inline void SAI_HAL_RxEnable(I2S_Type * base) +{ + I2S_BWR_RCSR_BCE(base,true); + I2S_BWR_RCSR_RE(base,true); +} + +/*! + * @brief Disables the Tx module. + * + * Disables the Tx. This function disables both the bit clock and the transfer channel. + * @param base Register base address of SAI module. + */ +static inline void SAI_HAL_TxDisable(I2S_Type * base) +{ + I2S_BWR_TCSR_TE(base,false); + I2S_BWR_TCSR_BCE(base,false); +} + +/*! + * @brief Disables the Rx module. + * + * Disables the Rx. This function disables both the bit clock and the receive channel. + * @param base Register base address of SAI module. + */ +static inline void SAI_HAL_RxDisable(I2S_Type * base) +{ + I2S_BWR_RCSR_RE(base,false); + I2S_BWR_RCSR_BCE(base,false); +} + +/*! + * @brief Enables the Tx interrupt from different interrupt sources. + * + * The interrupt source can be : Word start flag, Sync error flag, FIFO error flag, FIFO warning flag, FIFO request flag. + * This function sets which flag causes an interrupt request. + * @param base Register base address of SAI module. + * @param source SAI interrupt request source. + * @param enable Enable or disable. + */ +void SAI_HAL_TxSetIntCmd(I2S_Type * base, uint32_t source, bool enable); + +/*! + * @brief Enables the Rx interrupt from different interrupt sources. + * + * The interrupt source can be : Word start flag, Sync error flag, FIFO error flag, FIFO warning flag, FIFO request flag. + * This function sets which flag causes an interrupt request. + * @param base Register base address of SAI module. + * @param source SAI interrupt request source. + * @param enable Enable or disable. + */ +void SAI_HAL_RxSetIntCmd(I2S_Type * base, uint32_t source, bool enable); + +/*! + * @brief Enables the Tx DMA request from different sources. + * + * The DMA sources can be: FIFO warning and FIFO request. + * This function enables the DMA request from different DMA request sources. + * @param base Register base address of SAI module. + * @param source SAI DMA request source. + * @param enable Enable or disable. + */ +void SAI_HAL_TxSetDmaCmd(I2S_Type * base, uint32_t source, bool enable); + +/*! + * @brief Enables the Rx DMA request from different sources. + * + * The DMA sources can be: FIFO warning and FIFO request. + * This function enables the DMA request from different DMA request sources. + * @param base Register base address of SAI module. + * @param source SAI DMA request source. + * @param enable Enable or disable. + */ +void SAI_HAL_RxSetDmaCmd(I2S_Type * base, uint32_t source, bool enable); + +/*! + * @brief Clears the Tx state flags. + * + * The function is used to clear the flags manually. It can clear word start, FIFO warning, FIFO error, + * FIFO request flag. + * @param base Register base address of SAI module. + * @param flag SAI state flag type. The flag can be word start, sync error, FIFO error/warning. + */ +void SAI_HAL_TxClearStateFlag(I2S_Type * base, uint32_t flag_mask); + +/*! + * @brief Clears the Rx state flags. + * + * The function is used to clear the flags manually. It can clear word start, FIFO warning, FIFO error, + * FIFO request flag. + * @param base Register base address of SAI module. + * @param flag SAI state flag type. The flag can be word start, sync error, FIFO error/warning. + */ +void SAI_HAL_RxClearStateFlag(I2S_Type * base, uint32_t flag_mask); + +/*! + * @brief Resets the Tx module. + * + * There are two kinds of resets: Software reset and FIFO reset. + * Software reset: resets all transmitter internal logic, including the bit clock generation, + * status flags and FIFO pointers. It does not reset the configuration registers. + * FIFO reset: synchronizes the FIFO write pointer to the same value as the FIFO read pointer. + * This empties the FIFO contents and is to be used after the Transmit FIFO Error Flag is set, + * and before the FIFO is re-initialized and the Error Flag is cleared. + * @param base Register base address of SAI module. + * @param type SAI reset type. + */ +void SAI_HAL_TxSetReset(I2S_Type * base, uint32_t reset_mask); + +/*! + * @brief Resets the Rx module. + * + * There are two kinds of resets: Software reset and FIFO reset. + * Software reset: resets all transmitter internal logic, including the bit clock generation, + * status flags and FIFO pointers. It does not reset the configuration registers. + * FIFO reset: synchronizes the FIFO write pointer to the same value as the FIFO read pointer. + * This empties the FIFO contents and is to be used after the Transmit FIFO Error Flag is set, + * and before the FIFO is re-initialized and the Error Flag is cleared. + * @param base Register base address of SAI module. + * @param type SAI reset type. + */ +void SAI_HAL_RxSetReset(I2S_Type * base, uint32_t reset_mask); + +/*! + * @brief Sets the Tx FIFO channel. + * + * A SAI base includes a Tx and an Rx. Each has several channels according to + * different platforms. A channel means a path for the audio data input/output. + * @param base Register base address of SAI module. + * @param fifo_channel FIFO channel number. + */ +static inline void SAI_HAL_TxSetDataChn(I2S_Type * base, uint8_t fifo_channel) +{ + I2S_BWR_TCR3_TCE(base, 1u << fifo_channel); +} + +/*! + * @brief Sets the Rx FIFO channel. + * + * A SAI base includes a Tx and a Rx. Each has several channels according to + * different platforms. A channel means a path for the audio data input/output. + * @param base Register base address of SAI module. + * @param fifo_channel FIFO channel number. + */ +static inline void SAI_HAL_RxSetDataChn(I2S_Type * base, uint8_t fifo_channel) +{ + I2S_BWR_RCR3_RCE(base, 1u << fifo_channel); +} + +/*! + * @brief Sets the running mode of the Tx. There is a debug mode, stop mode, and a normal mode. + * + * This function can set the working mode of the SAI base. Stop mode is always + * used in low power cases, and the debug mode disables the SAI after the current + * transmit/receive is completed. + * @param base Register base address of SAI module. + * @param run_mode SAI running mode. + * @param enable Enable or disable a mode. + */ +void SAI_HAL_TxSetRunModeCmd(I2S_Type * base, sai_run_mode_t run_mode, bool enable); + +/*! + * @brief Sets the running mode of the Rx. There is a debug mode, stop mode, and a normal mode. + * + * This function can set the working mode of the SAI base. Stop mode is always + * used in low power cases, and the debug mode disables the SAI after the current + * transmit/receive is completed. + * @param base Register base address of SAI module. + * @param run_mode SAI running mode. + * @param enable Enable or disable a mode. + */ +void SAI_HAL_RxSetRunModeCmd(I2S_Type * base, sai_run_mode_t run_mode, bool enable); + +/*! + * @brief Gets the state of the flags in the TCSR. + * @param base Register base address of SAI module. + * @param flag State flag type, it can be FIFO error, FIFO warning and so on. + * @return True if detect word start otherwise false. + */ +static inline uint32_t SAI_HAL_TxGetStateFlag(I2S_Type * base, uint32_t flag_mask) +{ + return (I2S_RD_TCSR(base) & flag_mask); +} + +/*! + * @brief Gets the state of the flags in the RCSR. + * @param base Register base address of SAI module. + * @param flag State flag type, it can be FIFO error, FIFO warning and so on. + * @return True if detect word start otherwise false. + */ +static inline uint32_t SAI_HAL_RxGetStateFlag(I2S_Type * base, uint32_t flag_mask) +{ + return (I2S_RD_RCSR(base) & flag_mask); +} + +/*! + * @brief Receives the data from the FIFO. + * @param base Register base address of SAI module. + * @param rx_channel Rx FIFO channel. + * @param data Pointer to the address to be written in. + * @return Received data. + */ +static inline uint32_t SAI_HAL_ReceiveData(I2S_Type * base, uint32_t rx_channel) +{ + assert(rx_channel < FSL_FEATURE_SAI_CHANNEL_COUNT); + return I2S_RD_RDR(base, rx_channel); +} + +/*! + * @brief Transmits data to the FIFO. + * @param base Register base address of SAI module. + * @param tx_channel Tx FIFO channel. + * @param data Data value which needs to be written into FIFO. + */ +static inline void SAI_HAL_SendData(I2S_Type * base, uint32_t tx_channel, uint32_t data) +{ + assert(tx_channel < FSL_FEATURE_SAI_CHANNEL_COUNT); + I2S_WR_TDR(base,tx_channel,data); +} + +/*! +* @brief Uses blocking to receive data. +* @param base The SAI base. +* @param rx_channel Rx FIFO channel. +* @return Received data. +*/ +void SAI_HAL_ReceiveDataBlocking(I2S_Type * base, uint32_t rx_channel, + uint8_t * rxBuff, uint32_t size); + +/*! +* @brief Uses blocking to send data. +* @param base The SAI base. +* @param tx_channel Tx FIFO channel. +* @param data Data value which needs to be written into FIFO. +*/ +void SAI_HAL_SendDataBlocking(I2S_Type * base, uint32_t tx_channel, + uint8_t * txBuff, uint32_t size); + +#if FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE +/*! + * @brief Tx on-demand mode setting. + * + * When set, the frame sync is generated internally. A frame sync is only generated when the + * FIFO warning flag is clear. + * @param base Register base address of SAI module. + * @param enable True means on demand mode enable, false means disable. + */ +static inline void SAI_HAL_TxSetOndemandCmd(I2S_Type * base, bool enable) +{ + I2S_BWR_TCR4_ONDEM(base, enable); +} + +/*! + * @brief Rx on-demand mode setting. + * + * When set, the frame sync is generated internally. A frame sync is only generated when the + * FIFO warning flag is clear. + * @param base Register base address of SAI module. + * @param enable True means on demand mode enable, false means disable. + */ +static inline void SAI_HAL_RxSetOndemandCmd(I2S_Type * base, bool enable) +{ + I2S_BWR_RCR4_ONDEM(base, enable); +} +#endif + +#if FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR +/*! + * @brief Tx FIFO continues on error. + * + * Configures when the SAI continues transmitting after a FIFO error has been detected. + * @param base Register base address of SAI module. + * @param enable True means on demand mode enable, false means disable. + */ +static inline void SAI_HAL_TxSetFIFOErrorContinueCmd(I2S_Type * base, bool enable) +{ + I2S_BWR_TCR4_FCONT(base, enable); +} + +/*! + * @brief Rx FIFO continues on error. + * + * Configures when the SAI continues transmitting after a FIFO error has been detected. + * @param base Register base address of SAI module. + * @param enable True means on demand mode enable, false means disable. + */ +static inline void SAI_HAL_RxSetFIFOErrorContinueCmd(I2S_Type * base, bool enable) +{ + I2S_BWR_RCR4_FCONT(base, enable); +} +#endif + +#if FSL_FEATURE_SAI_HAS_FIFO_PACKING +/*! + * @brief Tx FIFO packing mode setting. + * + * Enables packing 8-bit data or 16-bit data into each 32-bit FIFO word. If the word size is + * greater than 8-bit or 16-bit, only the first 8-bit or 16-bits are loaded from the FIFO. + * The first word in each frame always starts with a new 32-bit FIFO word and the first bit shifted + * must be configured within the first packed word. When FIFO packing is enabled, the FIFO write + * pointer only increments when the full 32-bit FIFO word has been written by software. + * @param base Register base address of SAI module. + * @param mode FIFO packing mode. + */ +static inline void SAI_HAL_TxSetFIFOPackingMode(I2S_Type * base, sai_fifo_packing_t mode) +{ + I2S_BWR_TCR4_FPACK(base,mode); +} + +/*! + * @brief Rx FIFO packing mode setting. + * + * Enables packing 8-bit data or 16-bit data into each 32-bit FIFO word. If the word size is + * greater than 8-bit or 16-bit, only the first 8-bit or 16-bits are loaded from the FIFO. + * The first word in each frame always starts with a new 32-bit FIFO word and the first bit shifted + * must be configured within the first packed word. When FIFO packing is enabled, the FIFO write + * pointer only increments when the full 32-bit FIFO word has been written by software. + * @param base Register base address of SAI module. + * @param mode FIFO packing mode. + */ +static inline void SAI_HAL_RxSetFIFOPackingMode(I2S_Type * base, sai_fifo_packing_t mode) +{ + I2S_BWR_RCR4_FPACK(base,mode); +} +#endif + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif +#endif /* __FSL_SAI_HAL_H__ */ +/******************************************************************************* +* EOF +*******************************************************************************/ diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_sdhc_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_sdhc_hal.h new file mode 100755 index 0000000..813894d --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_sdhc_hal.h @@ -0,0 +1,635 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_SDHC_HAL_H__ +#define __FSL_SDHC_HAL_H__ + +#include <assert.h> +#include <stdbool.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_SDHC_COUNT + +/*! @addtogroup sdhc_hal */ +/*! @{ */ + +/* PRSSTA */ +#define SDHC_HAL_DAT0_LEVEL (SDHC_PRSSTAT_DLSL_MASK & (1 << 24)) + +/* XFERTYP */ +#define SDHC_HAL_MAX_BLOCK_COUNT ((1 << SDHC_BLKATTR_BLKCNT_WIDTH) - 1) +#define SDHC_HAL_ENABLE_DMA SDHC_XFERTYP_DMAEN_MASK + +#define SDHC_HAL_CMD_TYPE_SUSPEND (SDHC_XFERTYP_CMDTYP(1)) +#define SDHC_HAL_CMD_TYPE_RESUME (SDHC_XFERTYP_CMDTYP(2)) +#define SDHC_HAL_CMD_TYPE_ABORT (SDHC_XFERTYP_CMDTYP(3)) + +#define SDHC_HAL_ENABLE_BLOCK_COUNT SDHC_XFERTYP_BCEN_MASK +#define SDHC_HAL_ENABLE_AUTO_CMD12 SDHC_XFERTYP_AC12EN_MASK +#define SDHC_HAL_ENABLE_DATA_READ SDHC_XFERTYP_DTDSEL_MASK +#define SDHC_HAL_MULTIPLE_BLOCK SDHC_XFERTYP_MSBSEL_MASK + +#define SDHC_HAL_RESP_LEN_136 ((0x1 << SDHC_XFERTYP_RSPTYP_SHIFT) & SDHC_XFERTYP_RSPTYP_MASK) +#define SDHC_HAL_RESP_LEN_48 ((0x2 << SDHC_XFERTYP_RSPTYP_SHIFT) & SDHC_XFERTYP_RSPTYP_MASK) +#define SDHC_HAL_RESP_LEN_48_BC ((0x3 << SDHC_XFERTYP_RSPTYP_SHIFT) & SDHC_XFERTYP_RSPTYP_MASK) + +#define SDHC_HAL_ENABLE_CRC_CHECK SDHC_XFERTYP_CCCEN_MASK +#define SDHC_HAL_ENABLE_INDEX_CHECK SDHC_XFERTYP_CICEN_MASK +#define SDHC_HAL_DATA_PRESENT SDHC_XFERTYP_DPSEL_MASK + +/* SYSCTL */ +#define SDHC_HAL_MAX_DVS (16U) +#define SDHC_HAL_INITIAL_DVS (1U) /* initial value of divisor to calculate clock rate */ +#define SDHC_HAL_INITIAL_CLKFS (2U) /* initial value of clock selector to calculate clock rate */ +#define SDHC_HAL_NEXT_DVS(x) do { ((x) += 1); } while(0) +#define SDHC_HAL_PREV_DVS(x) do { ((x) -= 1); } while(0) +#define SDHC_HAL_MAX_CLKFS (256U) +#define SDHC_HAL_NEXT_CLKFS(x) do { ((x) <<= 1); } while(0) +#define SDHC_HAL_PREV_CLKFS(x) do { ((x) >>= 1); } while(0) + +/* IRQSTAT */ +#define SDHC_HAL_CMD_COMPLETE_INT SDHC_IRQSTAT_CC_MASK +#define SDHC_HAL_DATA_COMPLETE_INT SDHC_IRQSTAT_TC_MASK +#define SDHC_HAL_BLOCK_GAP_EVENT_INT SDHC_IRQSTAT_BGE_MASK +#define SDHC_HAL_DMA_INT SDHC_IRQSTAT_DINT_MASK +#define SDHC_HAL_DMA_ERR_INT SDHC_IRQSTAT_DMAE_MASK +#define SDHC_HAL_BUF_WRITE_READY_INT SDHC_IRQSTAT_BWR_MASK +#define SDHC_HAL_BUF_READ_READY_INT SDHC_IRQSTAT_BRR_MASK +#define SDHC_HAL_CARD_INSERTION_INT SDHC_IRQSTAT_CINS_MASK +#define SDHC_HAL_CARD_REMOVAL_INT SDHC_IRQSTAT_CRM_MASK +#define SDHC_HAL_CARD_INT SDHC_IRQSTAT_CINT_MASK +#define SDHC_HAL_CMD_TIMEOUT_ERR_INT SDHC_IRQSTAT_CTOE_MASK +#define SDHC_HAL_CMD_CRC_ERR_INT SDHC_IRQSTAT_CCE_MASK +#define SDHC_HAL_CMD_END_BIT_ERR_INT SDHC_IRQSTAT_CEBE_MASK +#define SDHC_HAL_CMD_INDEX_ERR_INT SDHC_IRQSTAT_CIE_MASK +#define SDHC_HAL_DATA_TIMEOUT_ERR_INT SDHC_IRQSTAT_DTOE_MASK +#define SDHC_HAL_DATA_CRC_ERR_INT SDHC_IRQSTAT_DCE_MASK +#define SDHC_HAL_DATA_END_BIT_ERR_INT SDHC_IRQSTAT_DEBE_MASK +#define SDHC_HAL_AUTO_CMD12_ERR_INT SDHC_IRQSTAT_AC12E_MASK + +#define SDHC_HAL_CMD_ERR_INT ((uint32_t)(SDHC_HAL_CMD_TIMEOUT_ERR_INT | \ + SDHC_HAL_CMD_CRC_ERR_INT | \ + SDHC_HAL_CMD_END_BIT_ERR_INT | \ + SDHC_HAL_CMD_INDEX_ERR_INT)) +#define SDHC_HAL_DATA_ERR_INT ((uint32_t)(SDHC_HAL_DATA_TIMEOUT_ERR_INT | \ + SDHC_HAL_DATA_CRC_ERR_INT | \ + SDHC_HAL_DATA_END_BIT_ERR_INT)) +#define SDHC_HAL_DATA_ALL_INT ((uint32_t)(SDHC_HAL_DATA_ERR_INT | \ + SDHC_HAL_DATA_COMPLETE_INT | \ + SDHC_HAL_BUF_READ_READY_INT | \ + SDHC_HAL_BUF_WRITE_READY_INT | \ + SDHC_HAL_DMA_ERR_INT | SDHC_HAL_DMA_INT)) +#define SDHC_HAL_CMD_ALL_INT ((uint32_t)(SDHC_HAL_CMD_ERR_INT | \ + SDHC_HAL_CMD_COMPLETE_INT | \ + SDHC_HAL_AUTO_CMD12_ERR_INT)) +#define SDHC_HAL_CD_ALL_INT ((uint32_t)(SDHC_HAL_CARD_INSERTION_INT | \ + SDHC_HAL_CARD_REMOVAL_INT)) +#define SDHC_HAL_ALL_ERR_INT ((uint32_t)(SDHC_HAL_CMD_ERR_INT | \ + SDHC_HAL_DATA_ERR_INT | \ + SDHC_HAL_AUTO_CMD12_ERR_INT | \ + SDHC_HAL_DMA_ERR_INT)) + +/* AC12ERR */ +#define SDHC_HAL_ACMD12_NOT_EXEC_ERR SDHC_AC12ERR_AC12NE_MASK +#define SDHC_HAL_ACMD12_TIMEOUT_ERR SDHC_AC12ERR_AC12TOE_MASK +#define SDHC_HAL_ACMD12_END_BIT_ERR SDHC_AC12ERR_AC12EBE_MASK +#define SDHC_HAL_ACMD12_CRC_ERR SDHC_AC12ERR_AC12CE_MASK +#define SDHC_HAL_ACMD12_INDEX_ERR SDHC_AC12ERR_AC12IE_MASK +#define SDHC_HAL_ACMD12_NOT_ISSUE_ERR SDHC_AC12ERR_CNIBAC12E_MASK + +/* ADMAES */ +/* ADMA Error State (When ADMA Error Is Occurred.) */ +#define SDHC_HAL_ADMA_STATE_ERR SDHC_ADMAES_ADMAES_MASK +/* ADMA Length Mismatch Error */ +#define SDHC_HAL_ADMA_LEN_MIS_MATCH_FLAG SDHC_ADMAES_ADMALME_MASK +/* ADMA Descriptor Error */ +#define SDHC_HAL_ADMA_DESP_ERR_FLAG SDHC_ADMAES_ADMADCE_MASK + +/* HTCAPBLT */ +#define SDHC_HAL_SUPPORT_ADMA SDHC_HTCAPBLT_ADMAS_MASK +#define SDHC_HAL_SUPPORT_HIGHSPEED SDHC_HTCAPBLT_HSS_MASK +#define SDHC_HAL_SUPPORT_DMA SDHC_HTCAPBLT_DMAS_MASK +#define SDHC_HAL_SUPPORT_SUSPEND_RESUME SDHC_HTCAPBLT_SRS_MASK +#define SDHC_HAL_SUPPORT_3_3_V SDHC_HTCAPBLT_VS33_MASK +#define SDHC_HAL_SUPPORT_3_0_V SDHC_HTCAPBLT_VS30_MASK +#define SDHC_HAL_SUPPORT_1_8_V SDHC_HTCAPBLT_VS18_MASK + +/* FEVT */ +#define SDHC_HAL_ACMD12_NOT_EXEC_ERR_EVENT SDHC_FEVT_AC12NE_MASK +#define SDHC_HAL_ACMD12_TIMEOUT_ERR_EVENT SDHC_FEVT_AC12TOE_MASK +#define SDHC_HAL_ACMD12_CRC_ERR_EVENT SDHC_FEVT_AC12CE_MASK +#define SDHC_HAL_ACMD12_END_BIT_ERR_EVENT SDHC_FEVT_AC12EBE_MASK +#define SDHC_HAL_ACMD12_INDEX_ERR_EVENT SDHC_FEVT_AC12IE_MASK +#define SDHC_HAL_ACMD12_NOT_ISSUE_ERR_EVENT SDHC_FEVT_CNIBAC12E_MASK +#define SDHC_HAL_CMD_TIMEOUT_ERR_EVENT SDHC_FEVT_CTOE_MASK +#define SDHC_HAL_CMD_CRC_ERR_EVENT SDHC_FEVT_CCE_MASK +#define SDHC_HAL_CMD_END_BIT_ERR_EVENT SDHC_FEVT_CEBE_MASK +#define SDHC_HAL_CMD_INDEX_ERR_EVENT SDHC_FEVT_CIE_MASK +#define SDHC_HAL_DATA_TIMEOUT_ERR_EVENT SDHC_FEVT_DTOE_MASK +#define SDHC_HAL_DATA_CRC_ERR_EVENT SDHC_FEVT_DCE_MASK +#define SDHC_HAL_DATA_END_BIT_ERR_EVENT SDHC_FEVT_DEBE_MASK +#define SDHC_HAL_ACMD12_ERR_EVENT SDHC_FEVT_AC12E_MASK +#define SDHC_HAL_CARD_INT_EVENT SDHC_FEVT_CINT_MASK +#define SDHC_HAL_DMA_ERROR_EVENT SDHC_FEVT_DMAE_MASK + +/*! @brief MMC card BOOT type */ +typedef enum _sdhc_hal_mmcboot { + kSdhcHalMmcbootNormal = 0, + kSdhcHalMmcbootAlter = 1, +} sdhc_hal_mmcboot_t; + +/*! @brief Led control status */ +typedef enum _sdhc_hal_led { + kSdhcHalLedOff = 0, + kSdhcHalLedOn = 1, +} sdhc_hal_led_t; + +/*! @brief Data transfer width */ +typedef enum _sdhc_hal_dtw { + kSdhcHalDtw1Bit = 0, + kSdhcHalDtw4Bit = 1, + kSdhcHalDtw8Bit = 2, +} sdhc_hal_dtw_t; + +/*! @brief SDHC endian mode */ +typedef enum _sdhc_hal_endian { + kSdhcHalEndianBig = 0, + kSdhcHalEndianHalfWordBig = 1, + kSdhcHalEndianLittle = 2, +} sdhc_hal_endian_t; + +/*! @brief SDHC dma mode */ +typedef enum _sdhc_hal_dma_mode { + kSdhcHalDmaSimple = 0, + kSdhcHalDmaAdma1 = 1, + kSdhcHalDmaAdma2 = 2, +} sdhc_hal_dma_mode_t; + +/*! @brief SDHC ADMA address alignment size and length alignment size */ +#define SDHC_HAL_ADMA1_ADDR_ALIGN (4096) +#define SDHC_HAL_ADMA1_LEN_ALIGN (4096) +#define SDHC_HAL_ADMA2_ADDR_ALIGN (4) +#define SDHC_HAL_ADMA2_LEN_ALIGN (4) + +/* + * ADMA1 descriptor table + * |------------------------|---------|--------------------------| + * | Address/page Field |reserved | Attribute | + * |------------------------|---------|--------------------------| + * |31 12|11 6|05 |04 |03|02 |01 |00 | + * |------------------------|---------|----|----|--|---|---|-----| + * | address or data length | 000000 |Act2|Act1| 0|Int|End|Valid| + * |------------------------|---------|----|----|--|---|---|-----| + * + * + * |------|------|-----------------|-------|-------------| + * | Act2 | Act1 | Comment | 31-28 | 27 - 12 | + * |------|------|-----------------|---------------------| + * | 0 | 0 | No op | Don't care | + * |------|------|-----------------|-------|-------------| + * | 0 | 1 | Set data length | 0000 | Data Length | + * |------|------|-----------------|-------|-------------| + * | 1 | 0 | Transfer data | Data address | + * |------|------|-----------------|---------------------| + * | 1 | 1 | Link descriptor | Descriptor address | + * |------|------|-----------------|---------------------| + * + */ +typedef uint32_t sdhc_hal_adma1_descriptor_t; +#define SDHC_HAL_ADMA1_DESC_VALID_MASK (1 << 0) +#define SDHC_HAL_ADMA1_DESC_END_MASK (1 << 1) +#define SDHC_HAL_ADMA1_DESC_INT_MASK (1 << 2) +#define SDHC_HAL_ADMA1_DESC_ACT1_MASK (1 << 4) +#define SDHC_HAL_ADMA1_DESC_ACT2_MASK (1 << 5) +#define SDHC_HAL_ADMA1_DESC_TYPE_NOP (SDHC_HAL_ADMA1_DESC_VALID_MASK) +#define SDHC_HAL_ADMA1_DESC_TYPE_TRAN (SDHC_HAL_ADMA1_DESC_ACT2_MASK | SDHC_HAL_ADMA1_DESC_VALID_MASK) +#define SDHC_HAL_ADMA1_DESC_TYPE_LINK (SDHC_HAL_ADMA1_DESC_ACT1_MASK | SDHC_HAL_ADMA1_DESC_ACT2_MASK | SDHC_HAL_ADMA1_DESC_VALID_MASK) +#define SDHC_HAL_ADMA1_DESC_TYPE_SET (SDHC_HAL_ADMA1_DESC_ACT1_MASK | SDHC_HAL_ADMA1_DESC_VALID_MASK) +#define SDHC_HAL_ADMA1_DESC_ADDRESS_SHIFT (12) +#define SDHC_HAL_ADMA1_DESC_ADDRESS_MASK (0xFFFFFU) +#define SDHC_HAL_ADMA1_DESC_LEN_SHIFT (12) +#define SDHC_HAL_ADMA1_DESC_LEN_MASK (0xFFFFU) +#define SDHC_HAL_ADMA1_DESC_MAX_LEN_PER_ENTRY (SDHC_HAL_ADMA1_DESC_LEN_MASK + 1) + +/* + * ADMA2 descriptor table + * |----------------|---------------|-------------|--------------------------| + * | Address Field | length | reserved | Attribute | + * |----------------|---------------|-------------|--------------------------| + * |63 32|31 16|15 06|05 |04 |03|02 |01 |00 | + * |----------------|---------------|-------------|----|----|--|---|---|-----| + * | 32-bit address | 16-bit length | 0000000000 |Act2|Act1| 0|Int|End|Valid| + * |----------------|---------------|-------------|----|----|--|---|---|-----| + * + * + * | Act2 | Act1 | Comment | Operation | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 0 | 0 | No op | Don't care | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 0 | 1 | Reserved | Read this line and go to next one | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 1 | 0 | Transfer data | Transfer data with address and length set in this descriptor line | + * |------|------|-----------------|-------------------------------------------------------------------| + * | 1 | 1 | Link descriptor | Link to another descriptor | + * |------|------|-----------------|-------------------------------------------------------------------| + * + */ +typedef struct SdhcHalAdma2Descriptor { + uint32_t attribute; + uint32_t *address; +} sdhc_hal_adma2_descriptor_t; + +/* ADMA1 descriptor control and status mask */ +#define SDHC_HAL_ADMA2_DESC_VALID_MASK (1 << 0) +#define SDHC_HAL_ADMA2_DESC_END_MASK (1 << 1) +#define SDHC_HAL_ADMA2_DESC_INT_MASK (1 << 2) +#define SDHC_HAL_ADMA2_DESC_ACT1_MASK (1 << 4) +#define SDHC_HAL_ADMA2_DESC_ACT2_MASK (1 << 5) +#define SDHC_HAL_ADMA2_DESC_TYPE_NOP (SDHC_HAL_ADMA2_DESC_VALID_MASK) +#define SDHC_HAL_ADMA2_DESC_TYPE_RCV (SDHC_HAL_ADMA2_DESC_ACT1_MASK | SDHC_HAL_ADMA2_DESC_VALID_MASK) +#define SDHC_HAL_ADMA2_DESC_TYPE_TRAN (SDHC_HAL_ADMA2_DESC_ACT2_MASK | SDHC_HAL_ADMA2_DESC_VALID_MASK) +#define SDHC_HAL_ADMA2_DESC_TYPE_LINK (SDHC_HAL_ADMA2_DESC_ACT1_MASK | SDHC_HAL_ADMA2_DESC_ACT2_MASK | SDHC_HAL_ADMA2_DESC_VALID_MASK) +#define SDHC_HAL_ADMA2_DESC_LEN_SHIFT (16) +#define SDHC_HAL_ADMA2_DESC_LEN_MASK (0xFFFFU) +#define SDHC_HAL_ADMA2_DESC_MAX_LEN_PER_ENTRY (SDHC_HAL_ADMA2_DESC_LEN_MASK) + +/* Card response type */ +#define SDHC_HAL_RST_TYPE_ALL SDHC_SYSCTL_RSTA_MASK +#define SDHC_HAL_RST_TYPE_CMD SDHC_SYSCTL_RSTC_MASK +#define SDHC_HAL_RST_TYPE_DATA SDHC_SYSCTL_RSTD_MASK + +/* Max block length sdhc support */ +#define SDHC_HAL_MAX_BLKLEN_512B (0U) +#define SDHC_HAL_MAX_BLKLEN_1024B (1U) +#define SDHC_HAL_MAX_BLKLEN_2048B (2U) +#define SDHC_HAL_MAX_BLKLEN_4096B (3U) + +/* Voltage Support 3.3 V */ +#define SDHC_HAL_SUPPORT_V330_FLAG (1U << 0) +/* Voltage Support 3.0 V */ +#define SDHC_HAL_SUPPORT_V300_FLAG (1U << 1) +/* High Speed Support */ +#define SDHC_HAL_SUPPORT_HIGHSPEED_FLAG (1U << 2) +/* DMA Support */ +#define SDHC_HAL_SUPPORT_DMA_FLAG (1U << 3) +/* ADMA Support */ +#define SDHC_HAL_SUPPORT_ADMA_FLAG (1U << 4) +/* Suspend/Resume Support */ +#define SDHC_HAL_SUPPORT_SUSPEND_RESUME_FLAG (1U << 5) +/* Voltage Support 1.8 V */ +#define SDHC_HAL_SUPPORT_V180_FLAG (1U << 6) +/* Support external dma */ +#define SDHC_HAL_SUPPORT_EXDMA_FLAG (1U << 7) + +/*! @brief Data structure to get the basic information of SDHC */ +typedef struct SdhcHalBasicInfo +{ + uint8_t specVer; /*!< Save the specification version */ + uint8_t vendorVer; /*!< Save the verdor version */ + uint16_t maxBlkLen; /*!< Save the max block length */ + uint32_t capability; /*!< The capability flags */ +}sdhc_hal_basic_info_t; + +/*! @brief SD clock configuration to configure the clock of SD protocol unit */ +typedef struct SdhcHalSdClkConfig +{ + bool enable; + uint32_t maxHostClk; + uint32_t destClk; +}sdhc_hal_sdclk_config_t; + +/*! @brief Current sdhc status type */ +typedef enum _sdhc_hal_curstat_type_t { + kSdhcHalIsCmdInhibit, /*!< Checks whether the command inhibit bit is set or not. */ + kSdhcHalIsDataInhibit, /*!< Checks whether data inhibit bit is set or not. */ + kSdhcHalIsDataLineActive, /*!< Checks whether data line is active. */ + kSdhcHalIsSdClockStable, /*!< Checks whether the SD clock is stable or not. */ + kSdhcHalIsIpgClockOff, /*!< Checks whether the IPG clock is off or not. */ + kSdhcHalIsSysClockOff, /*!< Checks whether the system clock is off or not. */ + kSdhcHalIsPeripheralClockOff, /*!< Checks whether the peripheral clock is off or not. */ + kSdhcHalIsSdClkOff, /*!< Checks whether the SD clock is off or not. */ + kSdhcHalIsWriteTransferActive, /*!< Checks whether the write transfer is active or not. */ + kSdhcHalIsReadTransferActive, /*!< Checks whether the read transfer is active or not. */ + kSdhcHalIsBuffWriteEnabled, /*!< Check whether the buffer write is enabled or not. */ + kSdhcHalIsBuffReadEnabled, /*!< Checks whether the buffer read is enabled or not. */ + kSdhcHalIsCardInserted, /*!< Checks whether the card is inserted or not. */ + kSdhcHalIsCmdLineLevelHigh, /*!< Checks whether the command line signal is high or not. */ + kSdhcHalGetDataLine0Level, /*!< Gets the data line 0 signal level or not. */ + kSdhcHalGetDataLine1Level, /*!< Gets the data line 1 signal level or not. */ + kSdhcHalGetDataLine2Level, /*!< Gets the data line 2 signal level or not. */ + kSdhcHalGetDataLine3Level, /*!< Gets the data line 3 signal level or not. */ + kSdhcHalGetDataLine4Level, /*!< Gets the data line 4 signal level or not. */ + kSdhcHalGetDataLine5Level, /*!< Gets the data line 5 signal level or not. */ + kSdhcHalGetDataLine6Level, /*!< Gets the data line 6 signal level or not. */ + kSdhcHalGetDataLine7Level, /*!< Gets the data line 7 signal level or not. */ + kSdhcHalGetCdTestLevel, /*!< Gets the card detect test level. */ +}sdhc_hal_curstat_type_t; + +/* DAT3 As Card Detection Pin */ +#define SDHC_HAL_EN_D3CD_FLAG (1U << 0) +/* Enables the card detect signal selection. */ +#define SDHC_HAL_EN_CD_SIG_SEL_FLAG (1U << 1) +/* Enables stop at the block gap. */ +#define SDHC_HAL_EN_STOP_AT_BLK_GAP_FLAG (1U << 2) +/* Enables the read wait control for the SDIO cards. */ +#define SDHC_HAL_EN_READ_WAIT_CTRL_FLAG (1U << 3) +/* Enables stop at the block gap requests interrupt. */ +#define SDHC_HAL_EN_INT_STOP_AT_BLK_GAP_FLAG (1U << 4) +/* Enables wakeup event on the card interrupt. */ +#define SDHC_HAL_EN_WAKEUP_ON_CARD_INT_FLAG (1U << 5) +/* Enables wakeup event on the card insertion. */ +#define SDHC_HAL_EN_WAKEUP_ON_CARD_INS_FLAG (1U << 6) +/* Enables wakeup event on card removal. */ +#define SDHC_HAL_EN_WAKEUP_ON_CARD_REM_FLAG (1U << 7) +/* Enables the external DMA request. */ +#define SDHC_HAL_EN_EXT_DMA_REQ_FLAG (1U << 8) +/* Enables the exact block number for the SDIO CMD53. */ +#define SDHC_HAL_EN_EXACT_BLK_NUM_FLAG (1U << 9) + +/* Enables the boot ACK. */ +#define SDHC_HAL_EN_BOOT_ACK_FLAG (1 << 0) +/* Enables the fast boot. */ +#define SDHC_HAL_EN_FAST_BOOT_FLAG (1 << 1) +/* Enables the automatic stop at the block gap. */ +#define SDHC_HAL_EN_BOOT_STOP_AT_BLK_GAP_FLAG (1 << 2) + +/*! @brief Data structure to configure the MMC boot feature */ +typedef struct SdhcHalMmcBootParam +{ + uint32_t ackTimeout; /*!< Sets the timeout value for the boot ACK. */ + sdhc_hal_mmcboot_t mode; /*!< Configures the boot mode. */ + uint32_t blockCount; /*!< Configures the the block count for the boot. */ + uint32_t enFlags; +}sdhc_mmcboot_param_t; + +/*! @brief Data structure to initialize the SDHC */ +typedef struct SdhcHalInitConfig +{ + sdhc_hal_led_t ledState; /*!< Sets the LED state. */ + sdhc_hal_endian_t endianMode; /*!< Configures the endian mode. */ + sdhc_hal_dma_mode_t dmaMode; /*!< Sets the DMA mode. */ + uint8_t writeWatermarkLevel; /*!< Sets the watermark for writing. */ + uint8_t readWatermarkLevel; /*!< Sets the watermark for reading. */ + uint32_t enFlags; /*!< Enable or disable corresponding feature */ + sdhc_mmcboot_param_t bootParams; /*!< Configture read MMC card boot data feature*/ +}sdhc_hal_config_t; + +/*! @brief Command request structure */ +typedef struct SdhcHalCmdReq +{ + uint32_t dataBlkSize; /*!< Cmd data Block size */ + uint32_t dataBlkCount; /*!< Cmd data Block count */ + uint32_t arg; /*!< Cmd argument */ + uint32_t index; /*!< Cmd index */ + uint32_t flags; /*!< Cmd Flags */ +}sdhc_hal_cmd_req_t; + +/*! @brief SDHC error type */ +typedef enum _sdhc_hal_err_type +{ + kAc12Err, /*!< Auto CMD12 error */ + kAdmaErr, /*!< ADMA error */ +}sdhc_hal_err_type_t; + + + +/************************************************************************************************* + * API + ************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! @name SDHC HAL FUNCTION */ +/*@{ */ + +/*! + * @brief Sends command to card. + * + * @param base SDHC base address + * @param cmdReq command request structure + */ +void SDHC_HAL_SendCmd(SDHC_Type * base, const sdhc_hal_cmd_req_t* cmdReq); + +/*! + * @brief Fills the the data port. + * + * @param base SDHC base address + * @param data the data about to be sent + */ +static inline void SDHC_HAL_SetData(SDHC_Type * base, uint32_t data) +{ + SDHC_WR_DATPORT(base, data); +} + +/*! + * @brief Retrieves the data from the data port. + * + * @param base SDHC base address + * @return the data has been read + */ +static inline uint32_t SDHC_HAL_GetData(SDHC_Type * base) +{ + return SDHC_RD_DATPORT(base); +} + +/*! + * @brief Gets current card's status. + * + * @param base SDHC base address + * @return the status if happened corresponding to stateType + * - true: status flag has been set + * - false: status flag has not been set + */ +bool SDHC_HAL_GetCurState(SDHC_Type * base, sdhc_hal_curstat_type_t stateType); + +/*! + * @brief Sets the data transfer width. + * + * @param base SDHC base address + * @param dtw data transfer width + */ +static inline void SDHC_HAL_SetDataTransferWidth(SDHC_Type * base, sdhc_hal_dtw_t dtw) +{ + SDHC_BWR_PROCTL_DTW(base, dtw); +} + +/*! +* @brief Restarts a transaction which has stopped at the block gap. +* +* @param base SDHC base address +*/ +static inline void SDHC_HAL_SetContinueRequest(SDHC_Type * base) +{ + SDHC_BWR_PROCTL_CREQ(base, 1); +} + +/*! +* @brief Initialize the SDHC according to the configuration user input. +* +* @param base SDHC base address +* @param initConfig The configuration structure +*/ +void SDHC_HAL_Config(SDHC_Type * base, const sdhc_hal_config_t* initConfig); + +/*! + * @brief Sets SDHC SD protol unit clock. + * + * @param base SDHC base address + * @param clkConfItms SDHC SD protol unit clock configuration items. + */ +void SDHC_HAL_ConfigSdClock(SDHC_Type * base, sdhc_hal_sdclk_config_t* clkConfItms); + +/*! +* @brief Gets the current interrupt status. +* +* @param base SDHC base address +* @return current interrupt flags +*/ +static inline uint32_t SDHC_HAL_GetIntFlags(SDHC_Type * base) +{ + return SDHC_RD_IRQSTAT(base); +} + +/*! +* @brief Clears a specified interrupt status. +* +* @param base SDHC base address +* @param mask to specify interrupts' flags to be cleared +*/ +static inline void SDHC_HAL_ClearIntFlags(SDHC_Type * base, uint32_t mask) +{ + SDHC_WR_IRQSTAT(base, mask); +} + +/*! + * @brief Get the error status of SDHC . + * + * @param base SDHC base address + * @param sdhc_hal_err_type_t the error type + * @param errFlags the result error flags +*/ +void SDHC_HAL_GetAllErrStatus(SDHC_Type * base, sdhc_hal_err_type_t errType, uint32_t* errFlags); + +/*! +* @brief Sets the force events according to the given mask. +* +* @param base SDHC base address +* @param mask to specify the force events' flags to be set +*/ +static inline void SDHC_HAL_SetForceEventFlags(SDHC_Type * base, uint32_t mask) +{ + SDHC_WR_FEVT(base, mask); +} + +/*! +* @brief Sets the ADMA address. +* +* @param base SDHC base address +* @param address for ADMA transfer +*/ +static inline void SDHC_HAL_SetAdmaAddress(SDHC_Type * base, uint32_t address) +{ + /* When use ADMA, disable simple DMA*/ + SDHC_WR_DSADDR(base, 0); + SDHC_WR_ADSADDR(base, address); +} + +/*! + * @brief Gets the command response. + * + * @param base SDHC base address + * @param index of response register, range from 0 to 3 + */ +uint32_t SDHC_HAL_GetResponse(SDHC_Type * base, uint32_t index); + +/*! +* @brief Enables the specified interrupts. +* +* @param base SDHC base address +* @param enable enable or disable +* @param mask to specify interrupts to be isEnabledd +*/ +void SDHC_HAL_SetIntSignal(SDHC_Type * base, bool enable, uint32_t mask); + +/*! +* @brief Enables the specified interrupt state. +* +* @param base SDHC base address +* @param enable enable or disable +* @param mask to specify interrupts' state to be enabled +*/ +void SDHC_HAL_SetIntState(SDHC_Type * base, bool enable, uint32_t mask); + +/*! +* @brief Performs an SDHC reset. +* +* @param base SDHC base address +* @param type the type of reset +* @param timeout timeout for reset +* @return 0 on success, else on error +*/ +uint32_t SDHC_HAL_Reset(SDHC_Type * base, uint32_t type, uint32_t timeout); + +/*! +* @brief Sends 80 clocks to the card to initialize the card. +* +* @param base SDHC base address +* @param timeout timeout for initialize card +* @return 0 on success, else on error +*/ +uint32_t SDHC_HAL_InitCard(SDHC_Type * base, uint32_t timeout); + +/*! + * @brief Initializes the SDHC HAL. + * + * @param base SDHC base address + */ +void SDHC_HAL_Init(SDHC_Type * base); + +/*! + * @brief Get the capability of SDHC + * + * @param base SDHC base address + */ +void SDHC_HAL_GetBasicInfo(SDHC_Type * base, sdhc_hal_basic_info_t* basicInfo); + +/*@} */ +#if defined(__cplusplus) +} +#endif +/*! @} */ + +#endif + +#endif +/************************************************************************************************* + * EOF + ************************************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_sim_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_sim_hal.h new file mode 100755 index 0000000..50e67fa --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_sim_hal.h @@ -0,0 +1,304 @@ +/* +* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. +* All rights reserved. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#if !defined(__FSL_SIM_HAL_H__) +#define __FSL_SIM_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> +#include <assert.h> +#include "fsl_device_registers.h" + +/*! @addtogroup sim_hal*/ +/*! @{*/ + +/*! @file*/ + +/******************************************************************************* +* Definitions +******************************************************************************/ + +/*! @brief SIM HAL API return status*/ +typedef enum _sim_hal_status { + kSimHalSuccess, /*!< Success. */ + kSimHalFail, /*!< Error occurs. */ +} sim_hal_status_t; + +/******************************************************************************* +* API +******************************************************************************/ + +/* +* Include the CPU-specific clock API header files. +*/ +#if (defined(K02F12810_SERIES)) + /* Clock System Level API header file */ + #include "../src/sim/MK02F12810/fsl_sim_hal_MK02F12810.h" + +#elif (defined(K20D5_SERIES)) + +#elif (defined(K22F12810_SERIES)) + +/* Clock System Level API header file */ +#include "../src/sim/MK22F12810/fsl_sim_hal_MK22F12810.h" + + +#elif (defined(K22F25612_SERIES)) + +/* Clock System Level API header file */ +#include "../src/sim/MK22F25612/fsl_sim_hal_MK22F25612.h" + + +#elif (defined(K22F51212_SERIES)) + +/* Clock System Level API header file */ +#include "../src/sim/MK22F51212/fsl_sim_hal_MK22F51212.h" + + +#elif (defined(K24F12_SERIES)) + +/* Clock System Level API header file */ +#include "../src/sim/MK24F12/fsl_sim_hal_MK24F12.h" + +#elif (defined(K24F25612_SERIES)) + +#include "../src/sim/MK24F25612/fsl_sim_hal_MK24F25612.h" + +#elif (defined(K26F18_SERIES)) +/* Clock System Level API header file */ +#include "../src/sim/MK26F18/fsl_sim_hal_MK26F18.h" + +#elif (defined(K10D10_SERIES)) +#include "../src/sim/MK10D10/fsl_sim_hal_MK10D10.h" + +#elif (defined(K20D10_SERIES)) +#include "../src/sim/MK20D10/fsl_sim_hal_MK20D10.h" + +#elif (defined(K30D10_SERIES)) +#include "../src/sim/MK30D10/fsl_sim_hal_MK30D10.h" + +#elif (defined(K40D10_SERIES)) +#include "../src/sim/MK40D10/fsl_sim_hal_MK40D10.h" + +#elif (defined(K50D10_SERIES)) +#include "../src/sim/MK50D10/fsl_sim_hal_MK50D10.h" + +#elif (defined(K51D10_SERIES)) +#include "../src/sim/MK51D10/fsl_sim_hal_MK51D10.h" + +#elif (defined(K52D10_SERIES)) +#include "../src/sim/MK52D10/fsl_sim_hal_MK52D10.h" + +#elif (defined(K53D10_SERIES)) +#include "../src/sim/MK53D10/fsl_sim_hal_MK53D10.h" + +#elif (defined(K60D10_SERIES)) + +/* Clock System Level API header file */ +#include "../src/sim/MK60D10/fsl_sim_hal_MK60D10.h" + +#elif (defined(K63F12_SERIES)) + +/* Clock System Level API header file */ +#include "../src/sim/MK63F12/fsl_sim_hal_MK63F12.h" + +#elif (defined(K64F12_SERIES)) + +/* Clock System Level API header file */ +#include "../src/sim/MK64F12/fsl_sim_hal_MK64F12.h" + +#elif (defined(K65F18_SERIES)) + +/* Clock System Level API header file */ +#include "../src/sim/MK65F18/fsl_sim_hal_MK65F18.h" + +#elif (defined(K66F18_SERIES)) + +/* Clock System Level API header file */ +#include "../src/sim/MK66F18/fsl_sim_hal_MK66F18.h" + +#elif (defined(K70F12_SERIES)) + + +#elif (defined(K70F15_SERIES)) + + +#elif (defined(KL02Z4_SERIES)) +#include "../src/sim/MKL02Z4/fsl_sim_hal_MKL02Z4.h" + +#elif (defined(KL03Z4_SERIES)) +/* Clock System Level API header file */ +#include "../src/sim/MKL03Z4/fsl_sim_hal_MKL03Z4.h" + +#elif (defined(KL28T7_SERIES)) +#include "../src/sim/MKL28T7/fsl_sim_hal_MKL28T7.h" + +#elif (defined(KL05Z4_SERIES)) + + +#elif (defined(KL13Z4_SERIES)) + +#elif (defined(KL14Z4_SERIES)) +#include "../src/sim/MKL14Z4/fsl_sim_hal_MKL14Z4.h" + +#elif (defined(KL15Z4_SERIES)) +#include "../src/sim/MKL15Z4/fsl_sim_hal_MKL15Z4.h" + +#elif (defined(KL23Z4_SERIES)) + +#elif (defined(KL24Z4_SERIES)) +#include "../src/sim/MKL24Z4/fsl_sim_hal_MKL24Z4.h" + +#elif (defined(KL25Z4_SERIES)) +/* Clock System Level API header file */ +#include "../src/sim/MKL25Z4/fsl_sim_hal_MKL25Z4.h" + +#elif (defined(KL17Z4_SERIES)) +#include "../src/sim/MKL17Z4/fsl_sim_hal_MKL17Z4.h" + +#elif (defined(KL27Z4_SERIES)) +#include "../src/sim/MKL27Z4/fsl_sim_hal_MKL27Z4.h" + +#elif (defined(KL33Z4_SERIES)) +#include "../src/sim/MKL33Z4/fsl_sim_hal_MKL33Z4.h" + +#elif (defined(KL34Z4_SERIES)) +#include "../src/sim/MKL34Z4/fsl_sim_hal_MKL34Z4.h" + +#elif (defined(KL43Z4_SERIES)) +#include "../src/sim/MKL43Z4/fsl_sim_hal_MKL43Z4.h" + +#elif (defined (KL17Z644_SERIES)) +#include "../src/sim/MKL17Z644/fsl_sim_hal_MKL17Z644.h" + +#elif (defined (KL27Z644_SERIES)) +#include "../src/sim/MKL27Z644/fsl_sim_hal_MKL27Z644.h" + +#elif (defined(KL16Z4_SERIES)) +#include "../src/sim/MKL16Z4/fsl_sim_hal_MKL16Z4.h" + +#elif (defined(KL26Z4_SERIES)) +#include "../src/sim/MKL26Z4/fsl_sim_hal_MKL26Z4.h" + +#elif (defined(KL36Z4_SERIES)) +#include "../src/sim/MKL36Z4/fsl_sim_hal_MKL36Z4.h" + +#elif (defined(KL46Z4_SERIES)) + +/* Clock System Level API header file */ +#include "../src/sim/MKL46Z4/fsl_sim_hal_MKL46Z4.h" + +#elif (defined(KV30F12810_SERIES)) +/* Clock System Level API header file */ +#include "../src/sim/MKV30F12810/fsl_sim_hal_MKV30F12810.h" + +#elif (defined(KV31F12810_SERIES)) + +/* Clock System Level API header file */ +#include "../src/sim/MKV31F12810/fsl_sim_hal_MKV31F12810.h" + +#elif (defined(KV31F25612_SERIES)) + +/* Clock System Level API header file */ +#include "../src/sim/MKV31F25612/fsl_sim_hal_MKV31F25612.h" + + +#elif (defined(KV31F51212_SERIES)) + +/* Clock System Level API header file */ +#include "../src/sim/MKV31F51212/fsl_sim_hal_MKV31F51212.h" + +#elif (defined(KV40F15_SERIES)) + +#include "../src/sim/MKV40F15/fsl_sim_hal_MKV40F15.h" + +#elif (defined(KV43F15_SERIES)) + +#include "../src/sim/MKV43F15/fsl_sim_hal_MKV43F15.h" + +#elif (defined(KV44F15_SERIES)) + +#include "../src/sim/MKV44F15/fsl_sim_hal_MKV44F15.h" + +#elif (defined(KV45F15_SERIES)) + +#include "../src/sim/MKV45F15/fsl_sim_hal_MKV45F15.h" + +#elif (defined(KV46F15_SERIES)) + +#include "../src/sim/MKV46F15/fsl_sim_hal_MKV46F15.h" + +#elif (defined(KV10Z7_SERIES)) + +#include "../src/sim/MKV10Z7/fsl_sim_hal_MKV10Z7.h" + +#elif (defined(KW01Z4_SERIES)) +/* Clock System Level API header file */ +#include "../src/sim/MKW01Z4/fsl_sim_hal_MKW01Z4.h" + +#elif (defined(K11DA5_SERIES)) + +#include "../src/sim/MK11DA5/fsl_sim_hal_MK11DA5.h" + +#elif (defined(K21DA5_SERIES)) + +#include "../src/sim/MK21DA5/fsl_sim_hal_MK21DA5.h" + + + +#elif (defined(KW21D5_SERIES)) + + +#include "../src/sim/MKW21D5/fsl_sim_hal_MKW21D5.h" + + +#elif (defined(KW22D5_SERIES)) + +#include "../src/sim/MKW22D5/fsl_sim_hal_MKW22D5.h" + +#elif (defined(KW24D5_SERIES)) + +#include "../src/sim/MKW24D5/fsl_sim_hal_MKW24D5.h" + +#elif (defined(K21FA12_SERIES)) +#include "../src/sim/MK21FA12/fsl_sim_hal_MK21FA12.h" +#if FSL_FEATURE_SOC_SIM_COUNT +#else +#error "No valid CPU defined!" +#endif + +/*! @}*/ + +#endif +#endif /* __FSL_SIM_HAL_H__*/ +/******************************************************************************* +* EOF +******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_smc_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_smc_hal.h new file mode 100755 index 0000000..d269e0e --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_smc_hal.h @@ -0,0 +1,320 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#if !defined(__FSL_SMC_HAL_H__) +#define __FSL_SMC_HAL_H__ + +#include <stdint.h> +#include <stdbool.h> +#include <assert.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_SMC_COUNT + +/*! @addtogroup smc_hal*/ +/*! @{*/ + +/*! @file fsl_smc_hal.h */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Power Modes */ +typedef enum _power_modes { + kPowerModeRun = 0x01U << 0U, + kPowerModeWait = 0x01U << 1U, + kPowerModeStop = 0x01U << 2U, + kPowerModeVlpr = 0x01U << 3U, + kPowerModeVlpw = 0x01U << 4U, + kPowerModeVlps = 0x01U << 5U, + kPowerModeLls = 0x01U << 6U, + kPowerModeVlls = 0x01U << 7U, + kPowerModeHsrun = 0x01U << 8U, + kPowerModeMax = 0x01U << 9U, +} power_modes_t; + +/*! + * @brief Error code definition for the system mode controller manager APIs. + */ +typedef enum _smc_hal_error_code { + kSmcHalSuccess, /*!< Success */ + kSmcHalNoSuchModeName, /*!< Cannot find the mode name specified*/ + kSmcHalAlreadyInTheState, /*!< Already in the required state*/ + kSmcHalFailed /*!< Unknown error, operation failed*/ +} smc_hal_error_code_t; + +/*! @brief Power Modes in PMSTAT*/ +typedef enum _power_mode_stat { + kStatRun = 0x01U, /*!< 0000_0001 - Current power mode is RUN*/ + kStatStop = 0x02U, /*!< 0000_0010 - Current power mode is STOP*/ + kStatVlpr = 0x04U, /*!< 0000_0100 - Current power mode is VLPR*/ + kStatVlpw = 0x08U, /*!< 0000_1000 - Current power mode is VLPW*/ + kStatVlps = 0x10U, /*!< 0001_0000 - Current power mode is VLPS*/ +#if FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE + kStatLls = 0x20U, /*!< 0010_0000 - Current power mode is LLS*/ +#endif + kStatVlls = 0x40U, /*!< 0100_0000 - Current power mode is VLLS*/ +#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE + kStatHsrun = 0x80U /*!< 1000_0000 - Current power mode is HSRUN*/ +#endif +} power_mode_stat_t; + +/*! @brief Power Modes Protection*/ +typedef enum _power_modes_protect { + kAllowPowerModeVlls = SMC_PMPROT_AVLLS_MASK, /*!< Allow Very-Low-Leakage Stop Mode*/ +#if FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE + kAllowPowerModeLls = SMC_PMPROT_ALLS_MASK, /*!< Allow Low-Leakage Stop Mode*/ +#endif + kAllowPowerModeVlp = SMC_PMPROT_AVLP_MASK, /*!< Allow Very-Low-Power Modes*/ +#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE + kAllowPowerModeHsrun = SMC_PMPROT_AHSRUN_MASK, /*!< Allow High Speed Run mode*/ +#endif + kAllowPowerModeAll = (SMC_PMPROT_AVLLS_MASK | +#if FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE + SMC_PMPROT_ALLS_MASK | +#endif +#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE + SMC_PMPROT_AHSRUN_MASK | +#endif + SMC_PMPROT_AVLP_MASK) /*!< Allow all power modes. */ +} power_modes_protect_t; + +/*! + * @brief Run mode definition + */ +typedef enum _smc_run_mode { + kSmcRun, /*!< normal RUN mode*/ + kSmcReservedRun, + kSmcVlpr, /*!< Very-Low-Power RUN mode*/ +#if FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE + kSmcHsrun /*!< High Speed Run mode (HSRUN)*/ +#endif +} smc_run_mode_t; + +/*! + * @brief Stop mode definition + */ +typedef enum _smc_stop_mode { + kSmcStop = 0U, /*!< Normal STOP mode*/ + kSmcReservedStop1 = 1U, /*!< Reserved*/ + kSmcVlps = 2U, /*!< Very-Low-Power STOP mode*/ +#if FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE + kSmcLls = 3U, /*!< Low-Leakage Stop mode*/ +#endif + kSmcVlls = 4U /*!< Very-Low-Leakage Stop mode*/ +} smc_stop_mode_t; + +/*! + * @brief VLLS/LLS stop sub mode definition + */ +typedef enum _smc_stop_submode { + kSmcStopSub0, /*!< Stop submode 0, for VLLS0/LLS0. */ + kSmcStopSub1, /*!< Stop submode 1, for VLLS1/LLS1. */ + kSmcStopSub2, /*!< Stop submode 2, for VLLS2/LLS2. */ + kSmcStopSub3 /*!< Stop submode 3, for VLLS3/LLS3. */ +} smc_stop_submode_t; + +/*! @brief Low Power Wake Up on Interrupt option*/ +typedef enum _smc_lpwui_option { + kSmcLpwuiEnabled, /*!< Low Power Wake Up on Interrupt enabled. @internal gui name="Enabled" */ + kSmcLpwuiDisabled /*!< Low Power Wake Up on Interrupt disabled. @internal gui name="Disabled" */ +} smc_lpwui_option_t; + +/*! @brief Partial STOP option*/ +typedef enum _smc_pstop_option { + kSmcPstopStop, /*!< STOP - Normal Stop mode*/ + kSmcPstopStop1, /*!< Partial Stop with both system and bus clocks disabled*/ + kSmcPstopStop2, /*!< Partial Stop with system clock disabled and bus clock enabled*/ + kSmcPstopReserved +} smc_pstop_option_t; + +/*! @brief POR option*/ +typedef enum _smc_por_option { + kSmcPorEnabled, /*!< POR detect circuit is enabled in VLLS0. @internal gui name="Enabled" */ + kSmcPorDisabled /*!< POR detect circuit is disabled in VLLS0. @internal gui name="Disabled" */ +} smc_por_option_t; + +/*! @brief RAM2 power option*/ +typedef enum _smc_ram2_option { + kSmcRam2DisPowered, /*!< RAM2 not powered in LLS2/VLLS2. @internal gui name="Not Powered" */ + kSmcRam2Powered /*!< RAM2 powered in LLS2/VLLS2. @internal gui name="Powered" */ +} smc_ram2_option_t; + +/*! @brief LPO power option*/ +typedef enum _smc_lpo_option { + kSmcLpoEnabled, /*!< LPO clock is enabled in LLS/VLLSx. @internal gui name="Enabled" */ + kSmcLpoDisabled /*!< LPO clock is disabled in LLS/VLLSx. @internal gui name="Disabled" */ +} smc_lpo_option_t; + +/*! @brief Power mode control configuration used for calling the SMC_SYS_SetPowerMode API. */ +typedef struct _smc_power_mode_config { + power_modes_t powerModeName; /*!< Power mode(enum), see power_modes_t */ + smc_stop_submode_t stopSubMode; /*!< Stop submode(enum), see smc_stop_submode_t */ +#if FSL_FEATURE_SMC_HAS_LPWUI + smc_lpwui_option_t lpwuiOptionValue; /*!< LPWUI option(enum), see smc_lpwui_option_t */ +#endif +#if FSL_FEATURE_SMC_HAS_PORPO + smc_por_option_t porOptionValue; /*!< POR option(enum), see smc_por_option_t */ +#endif +#if FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION + smc_ram2_option_t ram2OptionValue; /*!< RAM2 option(enum), see smc_ram2_option_t */ +#endif +#if FSL_FEATURE_SMC_HAS_PSTOPO + smc_pstop_option_t pstopOptionValue; /*!< PSTOPO option(enum), see smc_por_option_t */ +#endif +#if FSL_FEATURE_SMC_HAS_LPOPO + smc_lpo_option_t lpoOptionValue; /*!< LPOPO option, see smc_lpo_option_t */ +#endif +} smc_power_mode_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! @name System mode controller APIs*/ +/*@{*/ + +/*! + * @brief Configures the power mode. + * + * This function configures the power mode base on configuration structure, if + * could not switch to the target mode directly, this function could check + * internally and choose the right path. + * + * @param base Base address for current SMC instance. + * @param powerModeConfig Power mode configuration structure smc_power_mode_config_t + * @return SMC error code. + */ +smc_hal_error_code_t SMC_HAL_SetMode(SMC_Type * base, + const smc_power_mode_config_t *powerModeConfig); + +/*! + * @brief Configures all power mode protection settings. + * + * This function configures the power mode protection settings for + * supported power modes in the specified chip family. The available power modes + * are defined in the power_modes_protect_t. This should be done at an early + * system level initialization stage. See the reference manual for details. + * This register can only write once after the power reset. + * + * The allowed modes are passed as bit map, for example, to allow LLS and VLLS, + * plase use SMC_HAL_SetProtection(SMC, kAllowPowerModeLls | kAllowPowerModeVlls). + * To allow all modes, please use SMC_HAL_SetProtection(SMC, kAllowPowerModeAll). + * + * @param base Base address for current SMC instance. + * @param allowedModes Bitmap of the allowed power modes. + */ +static inline void SMC_HAL_SetProtection(SMC_Type * base, uint8_t allowedModes) +{ + SMC_WR_PMPROT(base, allowedModes); +} + +/*! + * @brief Get the power mode protection setting. + * + * This function checks whether the power modes are allowed. The modes to check + * are passed as bit map, for example, to check LLS and VLLS, + * plase use SMC_HAL_GetProtection(SMC, kAllowPowerModeLls | kAllowPowerModeVlls). + * To test all modes, please use SMC_HAL_GetProtection(SMC, kAllowPowerModeAll). + * + * @param base Base address for current SMC instance. + * @param modes Bitmap of the power modes to check. + * @return Bitmap of the allowed power modes. + */ +static inline uint8_t SMC_HAL_GetProtection(SMC_Type * base, uint8_t modes) +{ + return (uint8_t)(SMC_RD_PMPROT(base) & modes); +} + +#if FSL_FEATURE_SMC_HAS_LPWUI +/*! + * @brief Configures the LPWUI (Low Power Wake Up on interrupt) option. + * + * This function sets the LPWUI option and cause the system to exit + * to normal RUN mode when any active interrupt occurs while in a specific lower + * power mode. See the smc_lpwui_option_t for supported options and the + * reference manual for more details about this option. + * The function SMC_HAL_SetMode does not affect this bit, to configure it, + * please make sure current power mode is normal RUN mode. + * + * @param base Base address for current SMC instance. + * @param option LPWUI option setting defined in smc_lpwui_option_t + */ +static inline void SMC_HAL_SetLpwuiMode(SMC_Type * base, smc_lpwui_option_t option) +{ + SMC_BWR_PMCTRL_LPWUI(base, option); +} +#endif + +/*! + * @brief Check whether previous stop mode entry was successsful. + * + * @param base Base address for current SMC instance. + * @retval true The previous stop mode entry was aborted. + * @retval false The previous stop mode entry was successsful. + */ +static inline bool SMC_HAL_IsStopAbort(SMC_Type * base) +{ + return (bool)SMC_BRD_PMCTRL_STOPA(base); +} + +/*! + * @brief Gets the current power mode status. + * + * This function returns the current power mode stat. Once application + * switches the power mode, it should always check the stat to check whether it + * runs into the specified mode or not. An application should check + * this mode before switching to a different mode. The system requires that + * only certain modes can switch to other specific modes. See the + * reference manual for details and the _power_mode_stat for information about + * the power stat. + * + * @param base Base address for current SMC instance. + * @return Current power mode status. + */ +power_mode_stat_t SMC_HAL_GetStat(SMC_Type * base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif +#endif /* __FSL_SMC_HAL_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_spi_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_spi_hal.h new file mode 100755 index 0000000..e75bb72 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_spi_hal.h @@ -0,0 +1,879 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#if !defined(__FSL_SPI_HAL_H__) +#define __FSL_SPI_HAL_H__ + +#include "fsl_device_registers.h" +#include <stdint.h> +#include <stdbool.h> + +#if FSL_FEATURE_SOC_SPI_COUNT + +/*! @addtogroup spi_hal*/ +/*! @{*/ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Error codes for the SPI driver.*/ +typedef enum _spi_errors +{ + kStatus_SPI_Success = 0, + kStatus_SPI_SlaveTxUnderrun, /*!< SPI Slave TX Underrun error.*/ + kStatus_SPI_SlaveRxOverrun, /*!< SPI Slave RX Overrun error.*/ + kStatus_SPI_Timeout, /*!< SPI transfer timed out.*/ + kStatus_SPI_Busy, /*!< SPI instance is already busy performing a transfer.*/ + kStatus_SPI_NoTransferInProgress, /*!< Attempt to abort a transfer when no transfer + was in progress.*/ + kStatus_SPI_OutOfRange, /*!< SPI out-of-range error used in slave callback */ + kStatus_SPI_TxBufferNotEmpty, /*!< SPI TX buffer register is not empty */ + kStatus_SPI_InvalidParameter, /*!< Parameter is invalid */ + kStatus_SPI_NonInit, /*!< SPI driver is not initialized */ + kStatus_SPI_AlreadyInitialized, /*!< SPI driver already initialized */ + kStatus_SPI_DMAChannelInvalid, /*!< SPI driver cannot requests DMA channel */ +} spi_status_t; + +/*! @brief SPI master or slave configuration.*/ +typedef enum _spi_master_slave_mode { + kSpiMaster = 1, /*!< SPI peripheral operates in master mode.*/ + kSpiSlave = 0 /*!< SPI peripheral operates in slave mode.*/ +} spi_master_slave_mode_t; + +/*! @brief SPI clock polarity configuration.*/ +typedef enum _spi_clock_polarity { + kSpiClockPolarity_ActiveHigh = 0, /*!< Active-high SPI clock (idles low). @internal gui name="Active high" */ + kSpiClockPolarity_ActiveLow = 1 /*!< Active-low SPI clock (idles high).@internal gui name="Active low" */ +} spi_clock_polarity_t; + +/*! @brief SPI clock phase configuration.*/ +typedef enum _spi_clock_phase { + kSpiClockPhase_FirstEdge = 0, /*!< First edge on SPSCK occurs at the middle of the first + * cycle of a data transfer. @internal gui name="First edge" */ + kSpiClockPhase_SecondEdge = 1 /*!< First edge on SPSCK occurs at the start of the + * first cycle of a data transfer.@internal gui name="Second edge" */ +} spi_clock_phase_t; + +/*! @brief SPI data shifter direction options.*/ +typedef enum _spi_shift_direction { + kSpiMsbFirst = 0, /*!< Data transfers start with most significant bit. @internal gui name="Msb first" */ + kSpiLsbFirst = 1 /*!< Data transfers start with least significant bit. @internal gui name="Lsb first" */ +} spi_shift_direction_t; + +/*! @brief SPI slave select output mode options.*/ +typedef enum _spi_ss_output_mode { + kSpiSlaveSelect_AsGpio = 0, /*!< Slave select pin configured as GPIO.*/ + kSpiSlaveSelect_FaultInput = 2, /*!< Slave select pin configured for fault detection.*/ + kSpiSlaveSelect_AutomaticOutput = 3 /*!< Slave select pin configured for automatic SPI output.*/ +} spi_ss_output_mode_t; + +/*! @brief SPI pin mode options.*/ +typedef enum _spi_pin_mode { + kSpiPinMode_Normal = 0, /*!< Pins operate in normal, single-direction mode.*/ + kSpiPinMode_Input = 1, /*!< Bidirectional mode. Master: MOSI pin is input; + * Slave: MISO pin is input*/ + kSpiPinMode_Output = 3 /*!< Bidirectional mode. Master: MOSI pin is output; + * Slave: MISO pin is output*/ +} spi_pin_mode_t; + +/*! @brief SPI data length mode options.*/ +typedef enum _spi_data_bitcount_mode { + kSpi8BitMode = 0, /*!< 8-bit data transmission mode @internal gui name="8-bit" */ + kSpi16BitMode = 1, /*!< 16-bit data transmission mode @internal gui name="16-bit" */ +} spi_data_bitcount_mode_t; + +/*! @brief SPI interrupt sources.*/ +typedef enum _spi_interrupt_source { + kSpiRxFullAndModfInt = 1, /*!< Receive buffer full (SPRF) and mode fault (MODF) interrupt */ + kSpiTxEmptyInt = 2, /*!< Transmit buffer empty interrupt */ + kSpiMatchInt = 3, /*!< Match interrupt */ +} spi_interrupt_source_t; + +/*! @brief SPI interrupt status flags.*/ +typedef enum _spi_int_status_flag { + kSpiRxBufferFullFlag = SPI_S_SPRF_SHIFT, /*!< Read buffer full flag */ + kSpiMatchFlag = SPI_S_SPMF_SHIFT, /*!< Match flag */ + kSpiTxBufferEmptyFlag = SPI_S_SPTEF_SHIFT, /*!< Transmit buffer empty flag */ + kSpiModeFaultFlag = SPI_S_MODF_SHIFT, /*!< Mode fault flag */ +} spi_int_status_flag_t ; + +/*! @brief SPI FIFO interrupt sources.*/ +typedef enum _spi_fifo_interrupt_source { + kSpiRxFifoNearFullInt = 1, /*!< Receive FIFO nearly full interrupt */ + kSpiTxFifoNearEmptyInt = 2, /*!< Transmit FIFO nearly empty interrupt */ +} spi_fifo_interrupt_source_t ; + +/*! @brief SPI FIFO write-1-to-clear interrupt flags.*/ +typedef enum _spi_w1c_interrupt { + kSpiRxFifoFullClearInt = 0, /*!< Receive FIFO full interrupt */ + kSpiTxFifoEmptyClearInt = 1, /*!< Transmit FIFO empty interrupt */ + kSpiRxNearFullClearInt = 2, /*!< Receive FIFO nearly full interrupt */ + kSpiTxNearEmptyClearInt = 3, /*!< Transmit FIFO nearly empty interrupt */ +} spi_w1c_interrupt_t; + +/*! @brief SPI TX FIFO watermark settings.*/ +typedef enum _spi_txfifo_watermark { + kSpiTxFifoOneFourthEmpty = 0, + kSpiTxFifoOneHalfEmpty = 1 +} spi_txfifo_watermark_t; + +/*! @brief SPI RX FIFO watermark settings.*/ +typedef enum _spi_rxfifo_watermark { + kSpiRxFifoThreeFourthsFull = 0, + kSpiRxFifoOneHalfFull = 1 +} spi_rxfifo_watermark_t; + +/*! @brief SPI status flags.*/ +typedef enum _spi_fifo_status_flag { + kSpiRxFifoEmpty = 0, + kSpiTxFifoFull = 1, + kSpiTxNearEmpty = 2, + kSpiRxNearFull = 3 +} spi_fifo_status_flag_t; + +/*! @brief SPI error flags.*/ +typedef enum _spi_fifo_error_flag { + kSpiNoFifoError = 0, /*!< No error is detected */ + kSpiRxfof = 1, /*!< Rx FIFO Overflow */ + kSpiTxfof = 2, /*!< Tx FIFO Overflow */ + kSpiRxfofTxfof = 3, /*!< Rx FIFO Overflow, Tx FIFO Overflow */ + kSpiRxferr = 4, /*!< Rx FIFO Error */ + kSpiRxfofRxferr = 5, /*!< Rx FIFO Overflow, Rx FIFO Error */ + kSpiTxfofRxferr = 6, /*!< Tx FIFO Overflow, Rx FIFO Error */ + kSpiRxfofTxfofRxferr = 7, /*!< Rx FIFO Overflow, Tx FIFO Overflow, Rx FIFO Error */ + kSpiTxferr = 8, /*!< Tx FIFO Error */ + kSpiRxfofTxferr = 9, /*!< Rx FIFO Overflow, Tx FIFO Error */ + kSpiTxfofTxferr = 10, /*!< Tx FIFO Overflow, Tx FIFO Error */ + kSpiRxfofTxfofTxferr = 11, /*!< Rx FIFO Overflow, Tx FIFO Overflow, Tx FIFO Error */ + kSpiRxferrTxferr = 12, /*!< Rx FIFO Error, Tx FIFO Error */ + kSpiRxfofRxferrTxferr = 13, /*!< Rx FIFO Overflow, Rx FIFO Error, Tx FIFO Error */ + kSpiTxfofRxferrTxferr = 14, /*!< Tx FIFO Overflow, Rx FIFO Error, Tx FIFO Error */ + kSpiRxfofTxfofRxferrTxferr =15 /*!< Rx FIFO Overflow, Tx FIFO Overflow + * Rx FIFO Error, Tx FIFO Error */ +} spi_fifo_error_flag_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Configuration + * @{ + */ + +/*! + * @brief Restores the SPI to reset configuration. + * + * This function basically resets all of the SPI registers to their default setting including + * disabling the module. + * + * @param base Module base pointer of type SPI_Type. + */ +void SPI_HAL_Init(SPI_Type * base); + +/*! + * @brief Enables the SPI peripheral. + * + * @param base Module base pointer of type SPI_Type. + */ +static inline void SPI_HAL_Enable(SPI_Type * base) +{ + SPI_BWR_C1_SPE(base, 1); +} + +/*! + * @brief Disables the SPI peripheral. + * + * @param base Module base pointer of type SPI_Type. + */ +static inline void SPI_HAL_Disable(SPI_Type * base) +{ + SPI_BWR_C1_SPE(base, 0); +} + +/*! + * @brief Sets the SPI baud rate in bits per second. + * + * This function takes in the desired bitsPerSec (baud rate) and calculates the nearest + * possible baud rate without exceeding the desired baud rate unless the baud rate requested is + * less than the absolute minimum in which case the minimum baud rate will be returned. The returned + * baud rate is in bits-per-second. It requires that the caller also provide the frequency of the + * module source clock (in Hertz). + * + * @param base Module base pointer of type SPI_Type. + * @param bitsPerSec The desired baud rate in bits per second. + * @param sourceClockInHz Module source input clock in Hertz. + * @return The actual calculated baud rate in Hz. + */ +uint32_t SPI_HAL_SetBaud(SPI_Type * base, uint32_t bitsPerSec, uint32_t sourceClockInHz); + +/*! + * @brief Configures the baud rate divisors manually. + * + * This function allows the caller to manually set the baud rate divisors in the event that + * these dividers are known and the caller does not wish to call the SPI_HAL_SetBaudRate function. + * + * @param base Module base pointer of type SPI_Type. + * @param prescaleDivisor baud rate prescale divisor setting. + * @param rateDivisor baud rate divisor setting. + */ +static inline void SPI_HAL_SetBaudDivisors(SPI_Type * base, uint32_t prescaleDivisor, + uint32_t rateDivisor) +{ + SPI_WR_BR(base, SPI_BR_SPR(rateDivisor) | SPI_BR_SPPR(prescaleDivisor)); +} + +/*! + * @brief Configures the SPI for master or slave. + * + * @param base Module base pointer of type SPI_Type. + * @param mode Mode setting (master or slave) of type dspi_master_slave_mode_t. + */ +static inline void SPI_HAL_SetMasterSlave(SPI_Type * base, spi_master_slave_mode_t mode) +{ + SPI_BWR_C1_MSTR(base, (uint32_t)mode); +} + +/*! + * @brief Returns whether the SPI module is in master mode. + * + * @param base Module base pointer of type SPI_Type. + * @return true The module is in master mode. + * false The module is in slave mode. + */ +static inline bool SPI_HAL_IsMaster(SPI_Type * base) +{ + return (bool)SPI_RD_C1_MSTR(base); +} + +/*! + * @brief Sets how the slave select output operates. + * + * This function allows the user to configure the slave select in one of the three operational + * modes: as GPIO, as a fault input, or as an automatic output for standard SPI modes. + * + * @param base Module base pointer of type SPI_Type. + * @param mode Selection input of one of three modes of type spi_ss_output_mode_t. + */ +void SPI_HAL_SetSlaveSelectOutputMode(SPI_Type * base, spi_ss_output_mode_t mode); + +/*! + * @brief Sets the polarity, phase, and shift direction. + * + * This function configures the clock polarity, clock phase, and data shift direction. + * + * @param base Module base pointer of type SPI_Type. + * @param polarity Clock polarity setting of type spi_clock_polarity_t. + * @param phase Clock phase setting of type spi_clock_phase_t. + * @param direction Data shift direction (MSB or LSB) of type spi_shift_direction_t. + */ +void SPI_HAL_SetDataFormat(SPI_Type * base, + spi_clock_polarity_t polarity, + spi_clock_phase_t phase, + spi_shift_direction_t direction); + + +#if FSL_FEATURE_SPI_16BIT_TRANSFERS + +/*! + * @brief Sets the SPI data length to 8-bit or 16-bit. + * + * This function configures the SPI data length to 8-bit or 16-bit. + * + * @param base Module base pointer of type SPI_Type. + * @param mode The SPI data length (8- or 16-bit) of type spi_data_bitcount_t. + */ +static inline void SPI_HAL_Set8or16BitMode(SPI_Type * base, spi_data_bitcount_mode_t mode) +{ + SPI_BWR_C2_SPIMODE(base, (uint32_t)mode); +} + +/*! + * @brief Gets the SPI data length to 8-bit or 16-bit. + * + * This function gets the SPI data length (8-bit or 16-bit) configuration. + * + * @param base Module base pointer of type SPI_Type. + * @return The SPI data length (8- or 16-bit) setting of type spi_data_bitcount_t. + */ +static inline spi_data_bitcount_mode_t SPI_HAL_Get8or16BitMode(SPI_Type * base) +{ + return (spi_data_bitcount_mode_t)SPI_RD_C2_SPIMODE(base); +} + +/*! + * @brief Gets the SPI data register address for DMA operation. + * + * This function gets the SPI data register address as this value is needed for + * DMA operation. In the case of 16-bit transfers, return the SPI_DL as SPI_DH is + * implied for 16-bit accesses. + * + * @param base Module base pointer of type SPI_Type. + * @return The SPI data data register address. + */ +static inline uint32_t SPI_HAL_GetDataRegAddr(SPI_Type * base) +{ + return (uint32_t)(&SPI_DL_REG(base)); +} + +#else + +/*! + * @brief Gets the SPI data register address for DMA operation. + * + * This function gets the SPI data register address as this value is needed for + * DMA operation. + * + * @param base Module base pointer of type SPI_Type. + * @return The SPI data register address. + */ +static inline uint32_t SPI_HAL_GetDataRegAddr(SPI_Type * base) +{ + return (uint32_t)(&SPI_D_REG(base)); +} + +#endif + +/*! + * @brief Sets the SPI pin mode. + * + * This function configures the SPI data pins to one of three modes (of type spi_pin_mode_t): + * Single direction mode: MOSI and MISO pins operate in normal, single direction mode. + * Bidirectional mode: Master: MOSI configured as input, Slave: MISO configured as input. + * Bidirectional mode: Master: MOSI configured as output, Slave: MISO configured as output. + * + * @param base Module base pointer of type SPI_Type. + * @param mode Operational of SPI pins of type spi_pin_mode_t. + */ +void SPI_HAL_SetPinMode(SPI_Type * base, spi_pin_mode_t mode); + +/*@}*/ + +/*! + * @name DMA + * @{ + */ +#if FSL_FEATURE_SPI_HAS_DMA_SUPPORT +/*! + * @brief Configures the transmit DMA request. + * + * This function enables or disables the SPI TX DMA request. When the TX DMA is enabled + * it disables the TX interrupt. + * + * @param base Module base pointer of type SPI_Type. + * @param enableTransmit Enable (true) or disable (false) the transmit DMA request. + */ +static inline void SPI_HAL_SetTxDmaCmd(SPI_Type * base, bool enableTransmit) +{ + SPI_BWR_C2_TXDMAE(base, (enableTransmit == true)); +} + +/*! + * @brief Configures the receive DMA requests. + * + * This function enables or disables the SPI RX DMA request. When the RX DMA is enabled + * it disables the RX interrupt. + * + * @param base Module base pointer of type SPI_Type. + * @param enableReceive Enable (true) or disable (false) the receive DMA request. + */ +static inline void SPI_HAL_SetRxDmaCmd(SPI_Type * base, bool enableReceive) +{ + SPI_BWR_C2_RXDMAE(base, (enableReceive == true)); +} +#endif +/*@}*/ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables or disables the SPI interrupts. + * + * This function enables or disables the + * SPI receive buffer (or FIFO if the module supports a FIFO) full and mode fault interrupt + * SPI transmit buffer (or FIFO if the module supports a FIFO) empty interrupt + * SPI match interrupt + * + * Example, to set the receive and mode fault interrupt: + * SPI_HAL_SetIntMode(base, kSpiRxFullAndModfInt, true); + * + * @param base Module base pointer of type SPI_Type. + * @param interrupt SPI interrupt source to configure of type spi_interrupt_source_t. + * @param enable Enable (true) or disable (false) the receive buffer full and mode fault interrupt. + */ +void SPI_HAL_SetIntMode(SPI_Type * base, spi_interrupt_source_t interrupt, bool enable); + +/*! + * @brief Enables or disables the SPI receive buffer/FIFO full and mode fault interrupt. + * + * This function enables or disables the SPI receive buffer (or FIFO if the module supports a + * FIFO) full and mode fault interrupt. + * + * @param base Module base pointer of type SPI_Type. + * @param enable Enable (true) or disable (false) the receive buffer full and mode fault interrupt. + */ +static inline void SPI_HAL_SetReceiveAndFaultIntCmd(SPI_Type * base, bool enable) +{ + SPI_BWR_C1_SPIE(base, (enable == true)); +} + +/*! + * @brief Enables or disables the SPI transmit buffer/FIFO empty interrupt. + * + * This function enables or disables the SPI transmit buffer (or FIFO if the module supports a + * FIFO) empty interrupt. + * + * @param base Module base pointer of type SPI_Type. + * @param enable Enable (true) or disable (false) the transmit buffer empty interrupt. + */ +static inline void SPI_HAL_SetTransmitIntCmd(SPI_Type * base, bool enable) +{ + SPI_BWR_C1_SPTIE(base, (enable == true)); +} + +/*! + * @brief Enables or disables the SPI match interrupt. + * + * This function enables or disables the SPI match interrupt. + * + * @param base Module base pointer of type SPI_Type. + * @param enable Enable (true) or disable (false) the match interrupt. + */ +static inline void SPI_HAL_SetMatchIntCmd(SPI_Type * base, bool enable) +{ + SPI_BWR_C2_SPMIE(base, (enable == true)); +} + +/*@}*/ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the SPI interrupt status flag state.. + * + * This function returns the state (set or cleared) of the SPI interrupt status flag. + * + * @param base Module base pointer of type SPI_Type. + * @param flag The requested interrupt status flag of type spi_int_status_flag_t. + * @return Current setting of the requested interrupt status flag. + */ +static inline bool SPI_HAL_GetIntStatusFlag(SPI_Type * base, spi_int_status_flag_t flag) +{ + return (SPI_RD_S(base) >> flag) & 1U; +} + +/*! + * @brief Checks whether the read buffer/FIFO is full. + * + * The read buffer (or FIFO if the module supports a FIFO) full flag is only cleared by reading + * it when it is set, then reading the data register by calling the SPI_HAL_ReadData(). + * This example code demonstrates how to check the flag, read data, and clear the flag. + @code + // Check read buffer flag. + if (SPI_HAL_IsReadBuffFullPending(base)) + { + // Read the data in the buffer, which also clears the flag. + byte = SPI_HAL_ReadData(base); + } + @endcode + * + * @param base Module base pointer of type SPI_Type. + * @return Current setting of the read buffer full flag. + */ +static inline bool SPI_HAL_IsReadBuffFullPending(SPI_Type * base) +{ + return SPI_RD_S_SPRF(base); +} + +/*! + * @brief Checks whether the transmit buffer/FIFO is empty. + * + * To clear the transmit buffer (or FIFO if the module supports a FIFO) empty flag, you must first + * read the flag when it is set. Then write a new data value into the transmit buffer with a call + * to the SPI_HAL_WriteData(). The example code shows how to do this. + @code + // Check if transmit buffer is empty. + if (SPI_HAL_IsTxBuffEmptyPending(base)) + { + // Buffer has room, so write the next data value. + SPI_HAL_WriteData(base, byte); + } + @endcode + * + * @param base Module base pointer of type SPI_Type. + * @return Current setting of the transmit buffer empty flag. + */ +static inline bool SPI_HAL_IsTxBuffEmptyPending(SPI_Type * base) +{ + return SPI_RD_S_SPTEF(base); +} + +/*! + * @brief Checks whether a mode fault occurred. + * + * @param base Module base pointer of type SPI_Type. + * @return Current setting of the mode fault flag. + */ +static inline bool SPI_HAL_IsModeFaultPending(SPI_Type * base) +{ + return SPI_RD_S_MODF(base); +} + +/*! + * @brief Clears the mode fault flag. + * + * @param base Module base pointer of type SPI_Type + */ +void SPI_HAL_ClearModeFaultFlag(SPI_Type * base); + +/*! + * @brief Checks whether the data received matches the previously-set match value. + * + * @param base Module base pointer of type SPI_Type. + * @return Current setting of the match flag. + */ +static inline bool SPI_HAL_IsMatchPending(SPI_Type * base) +{ + return SPI_RD_S_SPMF(base); +} + +/*! + * @brief Clears the match flag. + * + * @param base Module base pointer of type SPI_Type. + */ +void SPI_HAL_ClearMatchFlag(SPI_Type * base); + +/*@}*/ + +/*! + * @name Data transfer + *@{ + */ + +#if FSL_FEATURE_SPI_16BIT_TRANSFERS + +/*! + * @brief Reads a byte from the high (upper 8-bits) data buffer. + * + * @param base Module base pointer of type SPI_Type. + * @return The data read from the upper 8-bit data buffer. + */ +static inline uint8_t SPI_HAL_ReadDataHigh(SPI_Type * base) +{ + return SPI_RD_DH(base); +} + +/*! + * @brief Reads a byte from the low (lower 8-bits) data buffer. + * + * @param base Module base pointer of type SPI_Type. + * @return The data read from the lower 8-bit data buffer. + */ +static inline uint8_t SPI_HAL_ReadDataLow(SPI_Type * base) +{ + return SPI_RD_DL(base); +} + +/*! + * @brief Writes a byte into the high (upper 8-bits) data buffer. + * + * @param base Module base pointer of type SPI_Type. + * @param data The data to send, upper 8-bits. + */ +static inline void SPI_HAL_WriteDataHigh(SPI_Type * base, uint8_t data) +{ + SPI_WR_DH(base, data); +} + +/*! + * @brief Writes a byte into the low (lower 8-bits) data buffer. + * + * @param base Module base pointer of type SPI_Type. + * @param data The data to send, lower 8-bits. + */ +static inline void SPI_HAL_WriteDataLow(SPI_Type * base, uint8_t data) +{ + SPI_WR_DL(base, data); +} + +/*! + * @brief Writes a byte into the data buffer and waits till complete to return. + * + * This function writes data to the SPI data registers and waits until the + * TX is empty to return. For 16-bit data, the lower byte is written to dataLow while + * the upper byte is written to dataHigh. The paramter bitCount is used to + * distinguish between 8- and 16-bit writes. + * + * Note, for 16-bit data writes, make sure that function SPI_HAL_Set8or16BitMode is set to + * kSpi16BitMode. + * + * @param base Module base pointer of type SPI_Type. + * @param bitCount the number of data bits to send, 8 or 16, of type spi_data_bitcount_mode_t. + * @param dataHigh The upper 8-bit data to send, set to 0 if only sending 8-bits. + * @param dataLow The lower 8-bit data to send, if only sending 8-bits, then use this parameter. + */ +void SPI_HAL_WriteDataBlocking(SPI_Type * base, spi_data_bitcount_mode_t bitCount, + uint8_t dataHigh, uint8_t dataLow); + +#else + +/*! + * @brief Reads a byte from the data buffer. + * + * @param base Module base pointer of type SPI_Type. + * @return The data read from the data buffer. + */ +static inline uint8_t SPI_HAL_ReadData(SPI_Type * base) +{ + return SPI_RD_D(base); +} + +/*! + * @brief Writes a byte into the data buffer. + * + * @param base Module base pointer of type SPI_Type. + * @param data The data to send. + */ +static inline void SPI_HAL_WriteData(SPI_Type * base, uint8_t data) +{ + SPI_WR_D(base, data); +} + +/*! + * @brief Writes a byte into the data buffer and waits till complete to return. + * + * This function writes data to the SPI data register and waits until the + * TX is empty to return. + * + * @param base Module base pointer of type SPI_Type. + * @param data The data to send. + */ +void SPI_HAL_WriteDataBlocking(SPI_Type * base, uint8_t data); + +#endif + +/*@}*/ + +/*! @name Match byte*/ +/*@{*/ + +#if FSL_FEATURE_SPI_16BIT_TRANSFERS +/*! + * @brief Sets the upper 8-bit value which triggers the match interrupt. + * + * @param base Module base pointer of type SPI_Type. + * @param matchByte The upper 8-bit value which triggers the match interrupt. + */ +static inline void SPI_HAL_SetMatchValueHigh(SPI_Type * base, uint8_t matchByte) +{ + SPI_WR_MH(base, matchByte); +} + +/*! + * @brief Sets the lower 8-bit value which triggers the match interrupt. + * + * @param base Module base pointer of type SPI_Type. + * @param matchByte The lower 8-bit value which triggers the match interrupt. + */ +static inline void SPI_HAL_SetMatchValueLow(SPI_Type * base, uint8_t matchByte) +{ + SPI_WR_ML(base, matchByte); +} +#else +/*! + * @brief Sets the value which triggers the match interrupt. + * + * @param base Module base pointer of type SPI_Type. + * @param matchByte The value which triggers the match interrupt. + */ +static inline void SPI_HAL_SetMatchValue(SPI_Type * base, uint8_t matchByte) +{ + SPI_WR_M(base, matchByte); +} +#endif + +/*@}*/ + +#if FSL_FEATURE_SPI_FIFO_SIZE +/*! + * @name FIFO support + *@{ + */ + +/*! + * @brief Enables or disables the SPI write-1-to-clear interrupt clearing mechanism. + * + * This function enables or disables the SPI write-1-to-clear interrupt clearing mechanism. + * When enabled, it allows the user to clear certain interrupts using bit writes. + * + * @param base Module base pointer of type SPI_Type. + * @param enable Enable (true) or disable (false) the write-1-to-clear interrupt clearing mechanism. + */ +static inline void SPI_HAL_SetIntClearCmd(SPI_Type * base, bool enable) +{ + SPI_BWR_C3_INTCLR(base, (enable == true)); +} + +/*! + * @brief Enables or disables the SPI FIFO and configures the TX/RX FIFO watermarks. + * + * This all-in-one function will do the following: + * Configure the TX FIFO empty watermark to be 16bits (1/4) or 32bits (1/2) + * Configure the RX FIFO full watermark to be 48bits (3/4) or 32bits (1/2) + * Enable/disable the FIFO + * + * @param base Module base pointer of type SPI_Type. + * @param enable Enable (true) or disable (false) the FIFO. + * @param txWaterMark The TX watermark setting of type spi_txfifo_watermark_t. + * @param rxWaterMark The RX watermark setting of type spi_rxfifo_watermark_t. + */ +void SPI_HAL_SetFifoMode(SPI_Type * base, bool enable, + spi_txfifo_watermark_t txWaterMark, + spi_rxfifo_watermark_t rxWaterMark); + +/*! + * @brief Returns the setting of the SPI FIFO mode (enable or disable). + * + * This function returns the setting of the SPI FIFO mode (enable or disable). + * + * @param baseAddr Module base address. + * @return The setting, enable (true) or disable (false), of the FIFO mode. + */ +static inline bool SPI_HAL_GetFifoCmd(SPI_Type * base) +{ + return SPI_RD_C3_FIFOMODE(base); +} + +/*! + * @brief Enables or disables the SPI FIFO specific interrupts. + * + * This function enables or disables the SPI FIFO interrupts. These FIFO interrupts are the TX + * FIFO nearly empty and the RX FIFO nearly full. Note, there are separate HAL functions + * to enable/disable receive buffer/FIFO full interrupt and the transmit buffer/FIFO empty + * interrupt. + * + * @param base Module base pointer of type SPI_Type. + * @param intSrc The FIFO interrupt source of type spi_fifo_interrupt_source_t. + * @param enable Enable (true) or disable (false) the specific FIFO interrupt. + */ +void SPI_HAL_SetFifoIntCmd(SPI_Type * base, spi_fifo_interrupt_source_t intSrc, + bool enable); + +/*! + * @brief Clears the FIFO related interrupt sources using write-1-to-clear feature. + * + * This function allows the user to clear particular FIFO interrupt sources using the + * write-1-to-clear feature. The function first determines if SPIx_C3[INTCLR] is enabled + * as needs to first be set in order to enable the write to clear mode. If not enabled, the + * function enables this bit, performs the interrupt source clear, then disables the write to + * clear mode. The FIFO related interrupt sources that can be cleared using this function are: + * Receive FIFO full interrupt + * Receive FIFO nearly full interrupt + * Transmit FIFO empty interrupt + * Transmit FIFO nearly empty interrupt + * + * @param base Module base pointer of type SPI_Type. + * @param intSrc The FIFO interrupt source to clear of type spi_w1c_interrupt_t. + */ +void SPI_HAL_ClearFifoIntUsingBitWrite(SPI_Type * base, spi_w1c_interrupt_t intSrc); + +/*! + * @brief Returns the desired FIFO related status flag. + * + * This function allows the user to ascertain the state of a FIFO related status flag. The user + * simply passes in the desired status flag and the function will return its current value. + * The status flags are as follows: + * Rx Fifo Empty + * Tx Fifo Full + * Tx Near Empty (based on SPI_C3[TNEAREF_MARK] setting) + * Rx Near Full (based on SPI_C3[RNFULLF_MARK] setting) + * + * @param base Module base pointer of type SPI_Type. + * @param status The FIFO related status flag of type spi_fifo_status_flag_t. + * @return Current setting of the desired status flag. + */ +static inline bool SPI_HAL_GetFifoStatusFlag(SPI_Type * base, spi_fifo_status_flag_t status) +{ + return ((SPI_RD_S(base) >> status) & 0x1U); +} + +/*! + * @brief Returns the FIFO related error flags. + * + * This function returns the consummate value of all four FIFO error flags. + * Note that simply reading the SPI_CI register will clear all of the error flags that are set, + * hence it is important to read them all at once and return the consummate value. + * This consummate value is typecasted as type spi_fifo_error_flag_t and provides the details + * of which flags are set. + * The combination of error flags are as follows: + * Rx FIFO Overflow + * Tx FIFO Overflow + * Rx FIFO Error + * Tx FIFO Error + * @param base Module base pointer of type SPI_Type. + * @return The consummate value of all four FIFO error flags of type spi_fifo_error_flag_t. + */ +static inline spi_fifo_error_flag_t SPI_HAL_GetFifoErrorFlag(SPI_Type * base) +{ + return (spi_fifo_error_flag_t)((SPI_RD_CI(base) >> 4) & 0xFU); +} + +/*@}*/ +#endif + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_FEATURE_SOC_SPI_COUNT */ +#endif /* __FSL_SPI_HAL_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_tpm_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_tpm_hal.h new file mode 100755 index 0000000..17d64a7 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_tpm_hal.h @@ -0,0 +1,569 @@ +/* + * Copyright (c) 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#if !defined(__FSL_TPM_HAL_H__) +#define __FSL_TPM_HAL_H__ + +#include "fsl_device_registers.h" +#include <stdbool.h> +#include <assert.h> + +#if FSL_FEATURE_SOC_TPM_COUNT + +/*! + * @addtogroup tpm_hal + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Table of number of channels for each TPM instance */ +extern const uint32_t g_tpmChannelCount[TPM_INSTANCE_COUNT]; + +/*! @brief TPM clock source selection for TPM_SC[CMOD].*/ +typedef enum _tpm_clock_mode +{ + kTpmClockSourceNoneClk = 0, /*TPM clock mode, None CLK*/ + kTpmClockSourceModuleClk, /*TPM clock mode, Module CLK*/ + kTpmClockSourceExternalClk, /*TPM clock mode, External input clock*/ + kTpmClockSourceReservedClk /*TPM clock mode, Reserved*/ +}tpm_clock_mode_t; + +/*! @brief TPM counting mode, up or down*/ +typedef enum _tpm_counting_mode +{ + kTpmCountingUp = 0, /*TPM counter mode, Up counting only*/ + kTpmCountingUpDown /*TPM counter mode, Up/Down counting mode*/ +}tpm_counting_mode_t; + +/*! @brief TPM prescaler factor selection for clock source*/ +typedef enum _tpm_clock_ps +{ + kTpmDividedBy1 = 0, /*TPM module clock prescaler, by 1*/ + kTpmDividedBy2 , /*TPM module clock prescaler, by 2*/ + kTpmDividedBy4 , /*TPM module clock prescaler, by 4*/ + kTpmDividedBy8, /*TPM module clock prescaler, by 8*/ + kTpmDividedBy16, /*TPM module clock prescaler, by 16*/ + kTpmDividedBy32, /*TPM module clock prescaler, by 32*/ + kTpmDividedBy64, /*TPM module clock prescaler, by 64*/ + kTpmDividedBy128 /*TPM module clock prescaler, by 128*/ +}tpm_clock_ps_t; + +/*! @brief TPM trigger sources, please refer to the chip reference manual for available options */ +typedef enum _tpm_trigger_source_t +{ + kTpmTrigSel0 = 0, /*!< TPM trigger source 0 */ + kTpmTrigSel1, /*!< TPM trigger source 1 */ + kTpmTrigSel2, /*!< TPM trigger source 2 */ + kTpmTrigSel3, /*!< TPM trigger source 3 */ + kTpmTrigSel4, /*!< TPM trigger source 4 */ + kTpmTrigSel5, /*!< TPM trigger source 5 */ + kTpmTrigSel6, /*!< TPM trigger source 6 */ + kTpmTrigSel7, /*!< TPM trigger source 7 */ + kTpmTrigSel8, /*!< TPM trigger source 8 */ + kTpmTrigSel9, /*!< TPM trigger source 8 */ + kTpmTrigSel10, /*!< TPM trigger source 10 */ + kTpmTrigSel11, /*!< TPM trigger source 11 */ + kTpmTrigSel12, /*!< TPM trigger source 12 */ + kTpmTrigSel13, /*!< TPM trigger source 13 */ + kTpmTrigSel14, /*!< TPM trigger source 14 */ + kTpmTrigSel15 /*!< TPM trigger source 15 */ +}tpm_trigger_source_t; + +/*! @brief TPM operation mode */ +typedef enum _tpm_pwm_mode_t +{ + kTpmEdgeAlignedPWM = 0, /*!< Edge aligned mode @internal gui name="Edge aligned" */ + kTpmCenterAlignedPWM /*!< Center aligned mode @internal gui name="Center aligned" */ +}tpm_pwm_mode_t; + +/*! @brief TPM PWM output pulse mode, high-true or low-true on match up */ +typedef enum _tpm_pwm_edge_mode_t +{ + kTpmHighTrue = 0, /*!< Clear output on match, set output on reload @internal gui name="High true" */ + kTpmLowTrue /*!< Set output on match, clear output on reload @internal gui name="Low true" */ +}tpm_pwm_edge_mode_t; + +/*! @brief TPM input capture modes */ +typedef enum _tpm_input_capture_mode_t +{ + kTpmRisingEdge = 1, + kTpmFallingEdge, + kTpmRiseOrFallEdge +}tpm_input_capture_mode_t; + +/*! @brief TPM output compare modes */ +typedef enum _tpm_output_compare_mode_t +{ + kTpmOutputNone = 0, + kTpmToggleOutput, + kTpmClearOutput, + kTpmSetOutput, + kTpmHighPulseOutput, + kTpmLowPulseOutput +}tpm_output_compare_mode_t; + +/*! @brief Error codes for TPM driver. */ +typedef enum _tpm_status +{ + kStatusTpmSuccess = 0x00U, /*!< TPM success status.*/ + kStatusTpmFail = 0x01U /*!< TPM error status.*/ +} tpm_status_t; + +/*! + * @brief TPM driver PWM parameter + * @internal gui name="PWM channels configuration" id="tpmPwmCfg" + */ +typedef struct TpmPwmParam +{ + tpm_pwm_mode_t mode; /*!< TPM PWM operation mode @internal gui name="Mode" id="PWMmode" */ + tpm_pwm_edge_mode_t edgeMode; /*!< PWM output mode @internal gui name="Edge mode" id="ChannelEdgeMode" */ + uint32_t uFrequencyHZ; /*!< PWM period in Hz @internal gui name="Frequency" id="Frequency" */ + uint32_t uDutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 + 0=inactive signal(0% duty cycle)... + 100=active signal (100% duty cycle). @internal gui name="Duty cycle" id="ChannelDuty" */ +}tpm_pwm_param_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief reset tpm registers + * + * @param tpmBase TPM module base address pointer + * @param instance The TPM peripheral instance number. + */ +void TPM_HAL_Reset(TPM_Type *tpmBase, uint32_t instance); + +/*! + * @brief Enables the TPM PWM output mode. + * + * @param tpmBase TPM module base address pointer + * @param config PWM configuration parameter + * @param channel The TPM channel number. + */ +void TPM_HAL_EnablePwmMode(TPM_Type *tpmBase, tpm_pwm_param_t *config, uint8_t channel); + +/*! + * @brief Disables the TPM channel. + * + * @param tpmBase TPM module base address pointer + * @param channel The TPM channel number. + */ +void TPM_HAL_DisableChn(TPM_Type *tpmBase, uint8_t channel); + +/*! + * @brief Set TPM clock mode. + * + * When disabling the TPM counter, the function will wait till it receives an acknowledge from the + * TPM clock domain + * + * @param tpmBase TPM module base address pointer + * @param mode The TPM counter clock mode (source). + */ +void TPM_HAL_SetClockMode(TPM_Type *tpmBase, tpm_clock_mode_t mode); + +/*! + * @brief get TPM clock mode. + * @param tpmBase TPM module base address pointer + * @return The TPM counter clock mode (source). + */ +static inline tpm_clock_mode_t TPM_HAL_GetClockMode(TPM_Type *tpmBase) +{ + return (tpm_clock_mode_t) TPM_BRD_SC_CMOD(tpmBase); +} + +/*! + * @brief set TPM clock divider. + * @param tpmBase TPM module base address pointer + * @param ps The TPM peripheral clock prescale divider + */ +static inline void TPM_HAL_SetClockDiv(TPM_Type *tpmBase, tpm_clock_ps_t ps) +{ + TPM_BWR_SC_PS(tpmBase, ps); +} + +/*! + * @brief get TPM clock divider. + * @param tpmBase TPM module base address pointer + * @return The TPM peripheral clock prescale divider. + */ +static inline tpm_clock_ps_t TPM_HAL_GetClockDiv(TPM_Type *tpmBase) +{ + return (tpm_clock_ps_t)TPM_BRD_SC_PS(tpmBase); +} + +/*! + * @brief Enable the TPM peripheral timer overflow interrupt. + * + * @param tpmBase TPM module base address pointer + */ +static inline void TPM_HAL_EnableTimerOverflowInt(TPM_Type *tpmBase) +{ + TPM_BWR_SC_TOIE(tpmBase, 1); +} + +/*! + * @brief Disable the TPM peripheral timer overflow interrupt. + * + * @param tpmBase TPM module base address pointer + */ +static inline void TPM_HAL_DisableTimerOverflowInt(TPM_Type *tpmBase) +{ + TPM_BWR_SC_TOIE(tpmBase, 0); +} + +/*! + * @brief Read the bit that controls TPM timer overflow interrupt enablement. + * + * @param tpmBase TPM module base address pointer + * @return true if overflow interrupt is enabled, false if not + */ +static inline bool TPM_HAL_IsOverflowIntEnabled(TPM_Type *tpmBase) +{ + return (bool)(TPM_BRD_SC_TOIE(tpmBase)); +} + +/*! + * @brief return TPM peripheral timer overflow interrupt flag. + * @param tpmBase TPM module base address pointer + * @return true if overflow, false if not + */ +static inline bool TPM_HAL_GetTimerOverflowStatus(TPM_Type *tpmBase) +{ + return (bool)(TPM_BRD_SC_TOF(tpmBase)); +} + +/*! + * @brief Clear the TPM timer overflow interrupt flag. + * @param tpmBase TPM module base address pointer + */ +static inline void TPM_HAL_ClearTimerOverflowFlag(TPM_Type *tpmBase) +{ + TPM_BWR_SC_TOF(tpmBase, 1); +} + +/*! + * @brief set TPM center-aligned PWM select. + * @param tpmBase TPM module base address pointer + * @param mode 1:upcounting mode 0:up_down counting mode. + */ +static inline void TPM_HAL_SetCpwms(TPM_Type *tpmBase, uint8_t mode) +{ + assert(mode < 2); + TPM_BWR_SC_CPWMS(tpmBase, mode); +} + +/*! + * @brief get TPM center-aligned PWM selection value. + * @param tpmBase TPM module base address pointer + * @return Whether the TPM center-aligned PWM is selected or not. + */ +static inline bool TPM_HAL_GetCpwms(TPM_Type *tpmBase) +{ + return (bool)TPM_BRD_SC_CPWMS(tpmBase); +} + +/*! + * @brief clear TPM peripheral current counter value. + * @param tpmBase TPM module base address pointer + */ +static inline void TPM_HAL_ClearCounter(TPM_Type *tpmBase) +{ + TPM_BWR_CNT_COUNT(tpmBase, 0); +} + +/*! + * @brief return TPM peripheral current counter value. + * @param tpmBase TPM module base address pointer + * @return current TPM timer counter value + */ +static inline uint16_t TPM_HAL_GetCounterVal(TPM_Type *tpmBase) +{ + return TPM_BRD_CNT_COUNT(tpmBase); +} + +/*! + * @brief set TPM peripheral timer modulo value. + * @param tpmBase TPM module base address pointer + * @param val The value to be set to the timer modulo + */ +static inline void TPM_HAL_SetMod(TPM_Type *tpmBase, uint16_t val) +{ + /*As RM mentioned, first clear TPM_CNT then write value to TPM_MOD*/ + TPM_BWR_CNT_COUNT(tpmBase, 0); + TPM_BWR_MOD_MOD(tpmBase, val); +} + +/*! + * @brief return TPM peripheral counter modulo value. + * @param tpmBase TPM module base address pointer + * @return TPM timer modula value + */ +static inline uint16_t TPM_HAL_GetMod(TPM_Type *tpmBase) +{ + return TPM_BRD_MOD_MOD(tpmBase); +} + +/*TPM channel operate mode(Mode, edge and level selection) for capture, output, pwm*/ + +/*! + * @brief Set TPM peripheral timer channel mode and edge level, + * + * TPM channel operate mode, MSnBA and ELSnBA shoud be set at the same time. + * + * @param tpmBase The TPM base address + * @param channel The TPM peripheral channel number + * @param value The value to set for MSnBA and ELSnBA + */ +static inline void TPM_HAL_SetChnMsnbaElsnbaVal(TPM_Type *tpmBase, uint8_t channel, uint8_t value) +{ + assert(channel < FSL_FEATURE_TPM_CHANNEL_COUNT); + + /* Keep CHIE bit value not changed by this function, so read it first and or with value*/ + value |= TPM_RD_CnSC(tpmBase, channel) & TPM_CnSC_CHIE_MASK; + + TPM_WR_CnSC(tpmBase, channel, value); +} + +/*! + * @brief get TPM peripheral timer channel mode. + * @param tpmBase TPM module base address pointer + * @param channel The TPM peripheral channel number + * @return The MSnB:MSnA mode value, will be 00,01, 10, 11 + */ +static inline uint8_t TPM_HAL_GetChnMsnbaVal(TPM_Type *tpmBase, uint8_t channel) +{ + assert(channel < FSL_FEATURE_TPM_CHANNEL_COUNT); + return (TPM_RD_CnSC(tpmBase, channel) & (TPM_CnSC_MSA_MASK | TPM_CnSC_MSB_MASK)) >> TPM_CnSC_MSA_SHIFT; +} + +/*! + * @brief get TPM peripheral timer channel edge level. + * @param tpmBase TPM module base address pointer + * @param channel The TPM peripheral channel number + * @return The ELSnB:ELSnA mode value, will be 00,01, 10, 11 + */ +static inline uint8_t TPM_HAL_GetChnElsnbaVal(TPM_Type *tpmBase, uint8_t channel) +{ + assert(channel < FSL_FEATURE_TPM_CHANNEL_COUNT); + return (TPM_RD_CnSC(tpmBase, channel) & (TPM_CnSC_ELSA_MASK | TPM_CnSC_ELSB_MASK)) >> TPM_CnSC_ELSA_SHIFT; +} + +/*! + * @brief enable TPM peripheral timer channel(n) interrupt. + * @param tpmBase TPM module base address pointer + * @param channel The TPM peripheral channel number + */ +static inline void TPM_HAL_EnableChnInt(TPM_Type *tpmBase, uint8_t channel) +{ + assert(channel < FSL_FEATURE_TPM_CHANNEL_COUNT); + TPM_BWR_CnSC_CHIE(tpmBase, channel, 1); +} + +/*! + * @brief disable TPM peripheral timer channel(n) interrupt. + * @param tpmBase TPM module base address pointer + * @param channel The TPM peripheral channel number + */ +static inline void TPM_HAL_DisableChnInt(TPM_Type *tpmBase, uint8_t channel) +{ + assert(channel < FSL_FEATURE_TPM_CHANNEL_COUNT); + TPM_BWR_CnSC_CHIE(tpmBase, channel, 0); +} + +/*! + * @brief get TPM peripheral timer channel(n) interrupt enabled or not. + * @param tpmBase TPM module base address pointer + * @param channel The TPM peripheral channel number + * @return Whether the TPM peripheral timer channel(n) interrupt is enabled or not. + */ +static inline bool TPM_HAL_IsChnIntEnabled(TPM_Type *tpmBase, uint8_t channel) +{ + assert(channel < FSL_FEATURE_TPM_CHANNEL_COUNT); + return (bool)(TPM_BRD_CnSC_CHIE(tpmBase, channel)); +} + +/*! + * @brief return if any event for TPM peripheral timer channel has occourred , + * @param tpmBase TPM module base address pointer + * @param channel The TPM peripheral channel number. + * @return true if event occourred, false otherwise + */ +static inline bool TPM_HAL_GetChnStatus(TPM_Type *tpmBase, uint8_t channel) +{ + assert(channel < FSL_FEATURE_TPM_CHANNEL_COUNT); + return (bool)(TPM_BRD_CnSC_CHF(tpmBase, channel)); +} + +/*! + * @brief return if any event for TPM peripheral timer channel has occourred , + * @param tpmBase TPM module base address pointer + * @param channel The TPM peripheral channel number. + */ +static inline void TPM_HAL_ClearChnInt(TPM_Type *tpmBase, uint8_t channel) +{ + assert(channel < FSL_FEATURE_TPM_CHANNEL_COUNT); + TPM_BWR_CnSC_CHF(tpmBase, channel, 0x1); +} + +/*TPM Channel control*/ +/*! + * @brief set TPM peripheral timer channel counter value, + * @param tpmBase TPM module base address pointer + * @param channel The TPM peripheral channel number. + * @param val counter value to be set + */ +static inline void TPM_HAL_SetChnCountVal(TPM_Type *tpmBase, uint8_t channel, uint16_t val) +{ + assert(channel < FSL_FEATURE_TPM_CHANNEL_COUNT); + TPM_BWR_CnV_VAL(tpmBase, channel, val); +} + +/*! + * @brief get TPM peripheral timer channel counter value. + * @param tpmBase TPM module base address pointer + * @param channel The TPM peripheral channel number. + * @return The TPM timer channel counter value. + */ +static inline uint16_t TPM_HAL_GetChnCountVal(TPM_Type *tpmBase, uint8_t channel) +{ + assert(channel < FSL_FEATURE_TPM_CHANNEL_COUNT); + return TPM_BRD_CnV_VAL(tpmBase, channel); +} + +/*! + * @brief get TPM peripheral timer channel event status. + * @param tpmBase TPM module base address pointer + * @return The TPM timer channel event status. + */ +static inline uint32_t TPM_HAL_GetStatusRegVal(TPM_Type *tpmBase) +{ + return TPM_RD_STATUS(tpmBase); +} + +/*! + * @brief clear TPM peripheral timer clear status register value, + * @param tpmBase TPM module base address pointer + * @param tpm_status tpm channel or overflow flag to clear + */ +static inline void TPM_HAL_ClearStatusReg(TPM_Type *tpmBase, uint16_t tpm_status) +{ + TPM_WR_STATUS(tpmBase, tpm_status); +} + +/*! + * @brief set TPM peripheral timer trigger. + * @param tpmBase TPM module base address pointer + * @param trigger_num 0-15 + */ +static inline void TPM_HAL_SetTriggerSrc(TPM_Type *tpmBase, tpm_trigger_source_t trigger_num) +{ + TPM_BWR_CONF_TRGSEL(tpmBase, trigger_num); +} + +/*! + * @brief set TPM peripheral timer running on trigger or not . + * @param tpmBase TPM module base address pointer + * @param enable true to enable, 1 to enable + */ +static inline void TPM_HAL_SetTriggerMode(TPM_Type *tpmBase, bool enable) +{ + TPM_BWR_CONF_CSOT (tpmBase, enable); +} + +/*! + * @brief enable TPM timer counter reload on selected trigger or not. + * @param tpmBase TPM module base address pointer + * @param enable true to enable, false to disable. + */ +static inline void TPM_HAL_SetReloadOnTriggerMode(TPM_Type *tpmBase, bool enable) +{ + TPM_BWR_CONF_CROT(tpmBase, enable); +} + +/*! + * @brief enable TPM timer counter sotp on selected trigger or not. + * @param tpmBase TPM module base address pointer + * @param enable true to enable, false to disable. + */ +static inline void TPM_HAL_SetStopOnOverflowMode(TPM_Type *tpmBase, bool enable) +{ + TPM_BWR_CONF_CSOO(tpmBase, enable); +} + +/*! + * @brief enable TPM timer global time base. + * @param tpmBase TPM module base address pointer + * @param enable true to enable, false to disable. + */ +static inline void TPM_HAL_EnableGlobalTimeBase(TPM_Type *tpmBase, bool enable) +{ + TPM_BWR_CONF_GTBEEN(tpmBase, enable); +} + +/*! + * @brief set BDM mode. + * @param tpmBase TPM module base address pointer + * @param enable false pause, true continue work + */ +static inline void TPM_HAL_SetDbgMode(TPM_Type *tpmBase, bool enable) +{ + TPM_BWR_CONF_DBGMODE(tpmBase, enable ? 3 : 0); +} + +/*! + * @brief set WAIT mode behavior. + * @param tpmBase TPM module base address pointer + * @param enable 0 continue running, 1 stop running + */ +static inline void TPM_HAL_SetWaitMode(TPM_Type *tpmBase, bool enable) +{ + TPM_BWR_CONF_DOZEEN(tpmBase, enable ? 0 : 1); +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* FSL_FEATURE_SOC_TPM_COUNT */ + +#endif /* __FSL_TPM_HAL_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_tsi_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_tsi_hal.h new file mode 100755 index 0000000..4b8fb20 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_tsi_hal.h @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2013, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_TSI_HAL_H__ +#define __FSL_TSI_HAL_H__ + +#include <assert.h> +#include <stdint.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_TSI_COUNT + +// Just for right generation of documentation +#if defined(__DOXYGEN__) + #define FSL_FEATURE_TSI_VERSION 1 +#endif + + + +/*! + * @addtogroup tsi_hal + * @{ + */ + + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Error codes for the TSI driver. */ +typedef enum _tsi_status +{ + kStatus_TSI_Success = 0, + kStatus_TSI_Busy, /*!< TSI still in progress */ + kStatus_TSI_LowPower, /*!< TSI is in low power mode */ + kStatus_TSI_Recalibration, /*!< TSI is under recalibration process */ + kStatus_TSI_InvalidChannel, /*!< Invalid TSI channel */ + kStatus_TSI_InvalidMode, /*!< Invalid TSI mode */ + kStatus_TSI_Initialized, /*!< The driver is initialized and ready to measure */ + kStatus_TSI_Error /*!< The general driver error */ +} tsi_status_t; + +/*! + * @brief TSI number of scan intervals for each electrode. + * + * These constants define the tsi number of consecutive scans in a TSI instance for each electrode. + */ +typedef enum _tsi_n_consecutive_scans { + kTsiConsecutiveScansNumber_1time = 0, /*!< once per electrode */ + kTsiConsecutiveScansNumber_2time = 1, /*!< twice per electrode */ + kTsiConsecutiveScansNumber_3time = 2, /*!< 3 times consecutive scan */ + kTsiConsecutiveScansNumber_4time = 3, /*!< 4 times consecutive scan */ + kTsiConsecutiveScansNumber_5time = 4, /*!< 5 times consecutive scan */ + kTsiConsecutiveScansNumber_6time = 5, /*!< 6 times consecutive scan */ + kTsiConsecutiveScansNumber_7time = 6, /*!< 7 times consecutive scan */ + kTsiConsecutiveScansNumber_8time = 7, /*!< 8 times consecutive scan */ + kTsiConsecutiveScansNumber_9time = 8, /*!< 9 times consecutive scan */ + kTsiConsecutiveScansNumber_10time = 9, /*!< 10 times consecutive scan */ + kTsiConsecutiveScansNumber_11time = 10, /*!< 11 times consecutive scan */ + kTsiConsecutiveScansNumber_12time = 11, /*!< 12 times consecutive scan */ + kTsiConsecutiveScansNumber_13time = 12, /*!< 13 times consecutive scan */ + kTsiConsecutiveScansNumber_14time = 13, /*!< 14 times consecutive scan */ + kTsiConsecutiveScansNumber_15time = 14, /*!< 15 times consecutive scan */ + kTsiConsecutiveScansNumber_16time = 15, /*!< 16 times consecutive scan */ + kTsiConsecutiveScansNumber_17time = 16, /*!< 17 times consecutive scan */ + kTsiConsecutiveScansNumber_18time = 17, /*!< 18 times consecutive scan */ + kTsiConsecutiveScansNumber_19time = 18, /*!< 19 times consecutive scan */ + kTsiConsecutiveScansNumber_20time = 19, /*!< 20 times consecutive scan */ + kTsiConsecutiveScansNumber_21time = 20, /*!< 21 times consecutive scan */ + kTsiConsecutiveScansNumber_22time = 21, /*!< 22 times consecutive scan */ + kTsiConsecutiveScansNumber_23time = 22, /*!< 23 times consecutive scan */ + kTsiConsecutiveScansNumber_24time = 23, /*!< 24 times consecutive scan */ + kTsiConsecutiveScansNumber_25time = 24, /*!< 25 times consecutive scan */ + kTsiConsecutiveScansNumber_26time = 25, /*!< 26 times consecutive scan */ + kTsiConsecutiveScansNumber_27time = 26, /*!< 27 times consecutive scan */ + kTsiConsecutiveScansNumber_28time = 27, /*!< 28 times consecutive scan */ + kTsiConsecutiveScansNumber_29time = 28, /*!< 29 times consecutive scan */ + kTsiConsecutiveScansNumber_30time = 29, /*!< 30 times consecutive scan */ + kTsiConsecutiveScansNumber_31time = 30, /*!< 31 times consecutive scan */ + kTsiConsecutiveScansNumber_32time = 31, /*!< 32 times consecutive scan */ +} tsi_n_consecutive_scans_t; + +/*! + * @brief TSI low power scan intervals limits. + * + * These constants define the limits of the tsi number of consecutive scans in a TSI instance. + */ +typedef struct _tsi_n_consecutive_scans_limits +{ + tsi_n_consecutive_scans_t upper; /*!< upper limit of number of consecutive scan */ + tsi_n_consecutive_scans_t lower; /*!< lower limit of number of consecutive scan */ +}tsi_n_consecutive_scans_limits_t; + + +/*! + * @brief TSI electrode oscillator prescaler. + * + * These constants define the tsi electrode oscillator prescaler in a TSI instance. + */ +typedef enum _tsi_electrode_osc_prescaler { + kTsiElecOscPrescaler_1div = 0, /*!< Electrode oscillator frequency divided by 1 */ + kTsiElecOscPrescaler_2div = 1, /*!< Electrode oscillator frequency divided by 2 */ + kTsiElecOscPrescaler_4div = 2, /*!< Electrode oscillator frequency divided by 4 */ + kTsiElecOscPrescaler_8div = 3, /*!< Electrode oscillator frequency divided by 8 */ + kTsiElecOscPrescaler_16div = 4, /*!< Electrode oscillator frequency divided by 16 */ + kTsiElecOscPrescaler_32div = 5, /*!< Electrode oscillator frequency divided by 32 */ + kTsiElecOscPrescaler_64div = 6, /*!< Electrode oscillator frequency divided by 64 */ + kTsiElecOscPrescaler_128div = 7, /*!< Electrode oscillator frequency divided by 128 */ +} tsi_electrode_osc_prescaler_t; + + + + + + +#if (FSL_FEATURE_TSI_VERSION == 1) || (FSL_FEATURE_TSI_VERSION == 2) + #include "fsl_tsi_v2_hal_specific.h" +#elif (FSL_FEATURE_TSI_VERSION == 4) + #include "fsl_tsi_v4_hal_specific.h" +#else + #error The TSI version is not supported +#endif + + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Initialize hardware. + * + * @param base TSI module base address. + * + * @return none + * + * @details Initialize the peripheral to default state. + */ +void TSI_HAL_Init(TSI_Type * base); + +/** + * @brief Set configuration of hardware. + * + * @param base TSI module base address. + * @param config Pointer to TSI module configuration structure. + * + * @return none + * + * @details Initialize and sets prescalers, number of scans, clocks, delta voltage + * capacitance trimmer, reference and electrode charge current and threshold. + */ +void TSI_HAL_SetConfiguration(TSI_Type * base, tsi_config_t *config); + +/** + * @brief Recalibrate TSI hardware. + * + * @param base TSI module base address. + * @param config Pointer to TSI module configuration structure. + * @param electrodes The map of the electrodes. + * @param parLimits Pointer to TSI module parameter limits structure. + * + * @return Lowest signal + * + * @details This function if TSI basic module is enable, than disable him and if + * module has enabled interrupt, disable him. Then Set prescaler, + * electrode and reference current, number of scan and voltage rails. + * Enable module and interrupt if is not. Better if you see implimetation + * of this function for better understanding @ref TSI_HAL_Recalibrate. + */ +uint32_t TSI_HAL_Recalibrate(TSI_Type * base, tsi_config_t *config, const uint32_t electrodes, const tsi_parameter_limits_t *parLimits); + +/*! + * @brief Enable low power for TSI module. + * + * @param base TSI module base address. + * + * @return none + * + */ +void TSI_HAL_EnableLowPower(TSI_Type * base); + +/*! +* @brief Disable low power for TSI module. +* +* @param base TSI module base address. +* @return None. +*/ +void TSI_HAL_DisableLowPower(TSI_Type * base); + +/*! +* @brief Get module flag enable. +* +* @param base TSI module base address. +* @return State of enable module flag. +*/ +static inline uint32_t TSI_HAL_IsModuleEnabled(TSI_Type * base) +{ + return TSI_BRD_GENCS_TSIEN(base); +} + +/*! +* @brief Get TSI scan trigger mode. +* +* @param base TSI module base address. +* @return Scan trigger mode. +*/ +static inline uint32_t TSI_HAL_GetScanTriggerMode(TSI_Type * base) +{ + return (uint32_t)TSI_BRD_GENCS_STM(base); +} + +/*! +* @brief Get scan in progress flag. +* +* @param base TSI module base address. +* @return True - if scan is in progress. False - otherwise +*/ +static inline uint32_t TSI_HAL_IsScanInProgress(TSI_Type * base) +{ + return (uint32_t)TSI_BRD_GENCS_SCNIP(base); +} + +/*! +* @brief Get end of scan flag. +* +* @param base TSI module base address. +* @return Current state of end of scan flag. +*/ +static inline uint32_t TSI_HAL_GetEndOfScanFlag(TSI_Type * base) +{ + return (uint32_t)TSI_BRD_GENCS_EOSF(base); +} + +/*! +* @brief Get out of range flag. +* +* @param base TSI module base address. +* @return State of out of range flag. +*/ +static inline uint32_t TSI_HAL_GetOutOfRangeFlag(TSI_Type * base) +{ + return (uint32_t)TSI_BRD_GENCS_OUTRGF(base); +} + +/*! +* @brief Get prescaler. +* +* @param base TSI module base address. +* @return Prescaler value. +*/ +static inline tsi_electrode_osc_prescaler_t TSI_HAL_GetPrescaler(TSI_Type * base) +{ + return (tsi_electrode_osc_prescaler_t)TSI_BRD_GENCS_PS(base); +} + +/*! +* @brief Get number of scans (NSCN). +* +* @param base TSI module base address. +* @return Number of scans. +*/ +static inline tsi_n_consecutive_scans_t TSI_HAL_GetNumberOfScans(TSI_Type * base) +{ + return (tsi_n_consecutive_scans_t)TSI_BRD_GENCS_NSCN(base); +} + +#ifdef __cplusplus +} +#endif + +/*! @}*/ +#endif +#endif /* __FSL_TSI_HAL_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_tsi_v2_hal_specific.h b/KSDK_1.2.0/platform/hal/inc/fsl_tsi_v2_hal_specific.h new file mode 100755 index 0000000..ed3cd93 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_tsi_v2_hal_specific.h @@ -0,0 +1,936 @@ +/* + * Copyright (c) 2013, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_TSI_V2_HAL_SPECIFIC_H__ +#define __FSL_TSI_V2_HAL_SPECIFIC_H__ + +#include <stdint.h> +#include "fsl_device_registers.h" +#include "fsl_tsi_hal.h" +#if FSL_FEATURE_SOC_TSI_COUNT + +// Just for right generation of documentation +#if defined(__DOXYGEN__) + #define FSL_FEATURE_TSI_VERSION 1 +#endif + +/*! + * @addtogroup tsi_hal + * @{ + */ + + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + + +/*! + * @brief TSI low power scan intervals. + * + * These constants define the tsi low power scan intervals in a TSI instance. + */ +typedef enum _tsi_low_power_interval { + kTsiLowPowerInterval_1ms = 0, /*!< 1ms scan interval */ + kTsiLowPowerInterval_5ms = 1, /*!< 5ms scan interval */ + kTsiLowPowerInterval_10ms = 2, /*!< 10ms scan interval */ + kTsiLowPowerInterval_15ms = 3, /*!< 15ms scan interval */ + kTsiLowPowerInterval_20ms = 4, /*!< 20ms scan interval */ + kTsiLowPowerInterval_30ms = 5, /*!< 30ms scan interval */ + kTsiLowPowerInterval_40ms = 6, /*!< 40ms scan interval */ + kTsiLowPowerInterval_50ms = 7, /*!< 50ms scan interval */ + kTsiLowPowerInterval_75ms = 8, /*!< 75ms scan interval */ + kTsiLowPowerInterval_100ms = 9, /*!< 100ms scan interval */ + kTsiLowPowerInterval_125ms = 10, /*!< 125ms scan interval */ + kTsiLowPowerInterval_150ms = 11, /*!< 150ms scan interval */ + kTsiLowPowerInterval_200ms = 12, /*!< 200ms scan interval */ + kTsiLowPowerInterval_300ms = 13, /*!< 300ms scan interval */ + kTsiLowPowerInterval_400ms = 14, /*!< 400ms scan interval */ + kTsiLowPowerInterval_500ms = 15, /*!< 500ms scan interval */ +} tsi_low_power_interval_t; + +/*! + * @brief TSI Reference oscillator charge current select. + * + * These constants define the tsi Reference oscillator charge current select in a TSI instance. + */ +typedef enum _tsi_reference_osc_charge_current { + kTsiRefOscChargeCurrent_2uA = 0, /*!< Reference oscillator charge current is 2uA */ + kTsiRefOscChargeCurrent_4uA = 1, /*!< Reference oscillator charge current is 4uA */ + kTsiRefOscChargeCurrent_6uA = 2, /*!< Reference oscillator charge current is 6uA */ + kTsiRefOscChargeCurrent_8uA = 3, /*!< Reference oscillator charge current is 8uA */ + kTsiRefOscChargeCurrent_10uA = 4, /*!< Reference oscillator charge current is 10uA */ + kTsiRefOscChargeCurrent_12uA = 5, /*!< Reference oscillator charge current is 12uA */ + kTsiRefOscChargeCurrent_14uA = 6, /*!< Reference oscillator charge current is 14uA */ + kTsiRefOscChargeCurrent_16uA = 7, /*!< Reference oscillator charge current is 16uA */ + kTsiRefOscChargeCurrent_18uA = 8, /*!< Reference oscillator charge current is 18uA */ + kTsiRefOscChargeCurrent_20uA = 9, /*!< Reference oscillator charge current is 20uA */ + kTsiRefOscChargeCurrent_22uA = 10, /*!< Reference oscillator charge current is 22uA */ + kTsiRefOscChargeCurrent_24uA = 11, /*!< Reference oscillator charge current is 24uA */ + kTsiRefOscChargeCurrent_26uA = 12, /*!< Reference oscillator charge current is 26uA */ + kTsiRefOscChargeCurrent_28uA = 13, /*!< Reference oscillator charge current is 28uA */ + kTsiRefOscChargeCurrent_30uA = 14, /*!< Reference oscillator charge current is 30uA */ + kTsiRefOscChargeCurrent_32uA = 15, /*!< Reference oscillator charge current is 32uA */ +} tsi_reference_osc_charge_current_t; + +/*! + * @brief TSI Reference oscillator charge current select limits. + * + * These constants define the limits of the TSI Reference oscillator charge current select in a TSI instance. + */ +typedef struct _tsi_reference_osc_charge_current_limits +{ + tsi_reference_osc_charge_current_t upper; /*!< Reference oscillator charge current upper limit */ + tsi_reference_osc_charge_current_t lower; /*!< Reference oscillator charge current lower limit */ +}tsi_reference_osc_charge_current_limits_t; + +/*! + * @brief TSI External oscillator charge current select. + * + * These constants define the tsi External oscillator charge current select in a TSI instance. + */ +typedef enum _tsi_external_osc_charge_current { + kTsiExtOscChargeCurrent_2uA = 0, /*!< External oscillator charge current is 2uA */ + kTsiExtOscChargeCurrent_4uA = 1, /*!< External oscillator charge current is 4uA */ + kTsiExtOscChargeCurrent_6uA = 2, /*!< External oscillator charge current is 6uA */ + kTsiExtOscChargeCurrent_8uA = 3, /*!< External oscillator charge current is 8uA */ + kTsiExtOscChargeCurrent_10uA = 4, /*!< External oscillator charge current is 10uA */ + kTsiExtOscChargeCurrent_12uA = 5, /*!< External oscillator charge current is 12uA */ + kTsiExtOscChargeCurrent_14uA = 6, /*!< External oscillator charge current is 14uA */ + kTsiExtOscChargeCurrent_16uA = 7, /*!< External oscillator charge current is 16uA */ + kTsiExtOscChargeCurrent_18uA = 8, /*!< External oscillator charge current is 18uA */ + kTsiExtOscChargeCurrent_20uA = 9, /*!< External oscillator charge current is 20uA */ + kTsiExtOscChargeCurrent_22uA = 10, /*!< External oscillator charge current is 22uA */ + kTsiExtOscChargeCurrent_24uA = 11, /*!< External oscillator charge current is 24uA */ + kTsiExtOscChargeCurrent_26uA = 12, /*!< External oscillator charge current is 26uA */ + kTsiExtOscChargeCurrent_28uA = 13, /*!< External oscillator charge current is 28uA */ + kTsiExtOscChargeCurrent_30uA = 14, /*!< External oscillator charge current is 30uA */ + kTsiExtOscChargeCurrent_32uA = 15, /*!< External oscillator charge current is 32uA */ +} tsi_external_osc_charge_current_t; + +/*! + * @brief TSI External oscillator charge current select limits. + * + * These constants define the limits of the TSI External oscillator charge current select in a TSI instance. + */ +typedef struct _tsi_external_osc_charge_current_limits +{ + tsi_external_osc_charge_current_t upper; /*!< External oscillator charge current upper limit */ + tsi_external_osc_charge_current_t lower; /*!< External oscillator charge current lower limit */ +}tsi_external_osc_charge_current_limits_t; + +/*! + * @brief TSI Internal capacitance trim value. + * + * These constants define the tsi Internal capacitance trim value in a TSI instance. + */ +typedef enum _tsi_internal_cap_trim { + kTsiIntCapTrim_0_5pF = 0, /*!< 0.5 pF internal reference capacitance */ + kTsiIntCapTrim_0_6pF = 1, /*!< 0.6 pF internal reference capacitance */ + kTsiIntCapTrim_0_7pF = 2, /*!< 0.7 pF internal reference capacitance */ + kTsiIntCapTrim_0_8pF = 3, /*!< 0.8 pF internal reference capacitance */ + kTsiIntCapTrim_0_9pF = 4, /*!< 0.9 pF internal reference capacitance */ + kTsiIntCapTrim_1_0pF = 5, /*!< 1.0 pF internal reference capacitance */ + kTsiIntCapTrim_1_1pF = 6, /*!< 1.1 pF internal reference capacitance */ + kTsiIntCapTrim_1_2pF = 7, /*!< 1.2 pF internal reference capacitance */ +} tsi_internal_cap_trim_t; + +/*! + * @brief TSI Delta voltage applied to analog oscillators. + * + * These constants define the tsi Delta voltage applied to analog oscillators in a TSI instance. + */ +typedef enum _tsi_osc_delta_voltage { + kTsiOscDeltaVoltage_100mV = 0, /*!< 100 mV delta voltage is applied */ + kTsiOscDeltaVoltage_150mV = 1, /*!< 150 mV delta voltage is applied */ + kTsiOscDeltaVoltage_200mV = 2, /*!< 200 mV delta voltage is applied */ + kTsiOscDeltaVoltage_250mV = 3, /*!< 250 mV delta voltage is applied */ + kTsiOscDeltaVoltage_300mV = 4, /*!< 300 mV delta voltage is applied */ + kTsiOscDeltaVoltage_400mV = 5, /*!< 400 mV delta voltage is applied */ + kTsiOscDeltaVoltage_500mV = 6, /*!< 500 mV delta voltage is applied */ + kTsiOscDeltaVoltage_600mV = 7, /*!< 600 mV delta voltage is applied */ +} tsi_osc_delta_voltage_t; + +/*! + * @brief TSI Active mode clock divider. + * + * These constants define the active mode clock divider in a TSI instance. + */ +typedef enum _tsi_active_mode_clock_divider { + kTsiActiveClkDiv_1div = 0, /*!< Active mode clock divider is set to 1 */ + kTsiActiveClkDiv_2048div = 1, /*!< Active mode clock divider is set to 2048 */ +} tsi_active_mode_clock_divider_t; + +/*! + * @brief TSI Active mode clock source. + * + * These constants define the active mode clock source in a TSI instance. + */ +typedef enum _tsi_active_mode_clock_source { + kTsiActiveClkSource_BusClock = 0, /*!< Active mode clock source is set to Bus Clock */ + kTsiActiveClkSource_MCGIRCLK = 1, /*!< Active mode clock source is set to MCG Internal reference clock */ + kTsiActiveClkSource_OSCERCLK = 2, /*!< Active mode clock source is set to System oscillator output */ +} tsi_active_mode_clock_source_t; + +/*! + * @brief TSI active mode prescaler. + * + * These constants define the tsi active mode prescaler in a TSI instance. + */ +typedef enum _tsi_active_mode_prescaler { + kTsiActiveModePrescaler_1div = 0, /*!< Input clock source divided by 1 */ + kTsiActiveModePrescaler_2div = 1, /*!< Input clock source divided by 2 */ + kTsiActiveModePrescaler_4div = 2, /*!< Input clock source divided by 4 */ + kTsiActiveModePrescaler_8div = 3, /*!< Input clock source divided by 8 */ + kTsiActiveModePrescaler_16div = 4, /*!< Input clock source divided by 16 */ + kTsiActiveModePrescaler_32div = 5, /*!< Input clock source divided by 32 */ + kTsiActiveModePrescaler_64div = 6, /*!< Input clock source divided by 64 */ + kTsiActiveModePrescaler_128div = 7, /*!< Input clock source divided by 128 */ +} tsi_active_mode_prescaler_t; + +/*! +* @brief TSI active mode prescaler limits. +* +* These constants define the limits of the TSI active mode prescaler in a TSI instance. +*/ +typedef struct _tsi_active_mode_prescaler_limits { + tsi_active_mode_prescaler_t upper; /*!< Input clock source prescaler upper limit */ + tsi_active_mode_prescaler_t lower; /*!< Input clock source prescaler lower limit */ +}tsi_active_mode_prescaler_limits_t; + +/*! +* @brief TSI operation mode limits +* +* These constants is used to specify the valid range of settings for the recalibration process of TSI parameters +*/ +typedef struct _tsi_parameter_limits { + tsi_n_consecutive_scans_limits_t consNumberOfScan; /*!< number of consecutive scan limits */ + tsi_reference_osc_charge_current_limits_t refOscChargeCurrent; /*!< Reference oscillator charge current limits */ + tsi_external_osc_charge_current_limits_t extOscChargeCurrent; /*!< External oscillator charge current limits */ + tsi_active_mode_prescaler_limits_t activeModePrescaler; /*!< Input clock source prescaler limits */ +}tsi_parameter_limits_t; + + +#if (FSL_FEATURE_TSI_VERSION == 1) +/*! + * @brief TSI configuration structure. + * + * This structure contains the settings for the most common TSI configurations including + * the TSI module charge currents, number of scans, thresholds, trimming etc. + */ +typedef struct TsiConfig { + tsi_electrode_osc_prescaler_t ps; /*!< Prescaler */ + tsi_external_osc_charge_current_t extchrg; /*!< Electrode charge current */ + tsi_reference_osc_charge_current_t refchrg; /*!< Reference charge current */ + tsi_n_consecutive_scans_t nscn; /*!< Number of scans. */ + uint8_t lpclks; /*!< Low power clock. */ + tsi_active_mode_clock_source_t amclks; /*!< Active mode clock source. */ + tsi_active_mode_clock_divider_t amclkdiv; /*!< Active mode prescaler. */ + tsi_active_mode_prescaler_t ampsc; /*!< Active mode prescaler. */ + tsi_low_power_interval_t lpscnitv; /*!< Low power scan interval. */ + tsi_osc_delta_voltage_t delvol; /*!< Delta voltage. */ + tsi_internal_cap_trim_t captrm; /*!< Internal capacitence trimmer. */ + uint16_t thresh; /*!< High threshold. */ + uint16_t thresl; /*!< Low threshold. */ +}tsi_config_t; + +#elif (FSL_FEATURE_TSI_VERSION == 2) +/*! + * @brief TSI configuration structure. + * + * This structure contains the settings for the most common TSI configurations including + * the TSI module charge currents, number of scans, thresholds, trimming etc. + */ +typedef struct TsiConfig { + tsi_electrode_osc_prescaler_t ps; /*!< Prescaler */ + tsi_external_osc_charge_current_t extchrg; /*!< Electrode charge current */ + tsi_reference_osc_charge_current_t refchrg; /*!< Reference charge current */ + tsi_n_consecutive_scans_t nscn; /*!< Number of scans. */ + uint8_t lpclks; /*!< Low power clock. */ + tsi_active_mode_clock_source_t amclks; /*!< Active mode clock source. */ + tsi_active_mode_prescaler_t ampsc; /*!< Active mode prescaler. */ + tsi_low_power_interval_t lpscnitv; /*!< Low power scan interval. */ + uint16_t thresh; /*!< High threshold. */ + uint16_t thresl; /*!< Low threshold. */ +}tsi_config_t; + +#else +#error TSI version not supported. +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/*! +* @brief Enable Touch Sensing Input Module. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_EnableModule(TSI_Type * base) +{ + TSI_BWR_GENCS_TSIEN(base, 1); +} + +/*! +* @brief Disable Touch Sensing Input Module. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_DisableModule(TSI_Type * base) +{ + TSI_BWR_GENCS_TSIEN(base, 0); +} + +/*! +* @brief Enable TSI module in stop mode. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_EnableStop(TSI_Type * base) +{ + TSI_BWR_GENCS_STPE(base, 1); +} + +/*! +* @brief Disable TSI module in stop mode. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_DisableStop(TSI_Type * base) +{ + TSI_BWR_GENCS_STPE(base, 0); +} + +/*! +* @brief Enable out of range interrupt. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_EnableOutOfRangeInterrupt(TSI_Type * base) +{ + TSI_BWR_GENCS_ESOR(base, 0); +} + +/*! +* @brief Enable end of scan interrupt. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_EnableEndOfScanInterrupt(TSI_Type * base) +{ + TSI_BWR_GENCS_ESOR(base, 1); +} + +/*! +* @brief Enable periodical (hardware) trigger scan. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_EnablePeriodicalScan(TSI_Type * base) +{ + TSI_BWR_GENCS_STM(base, 1); +} + +/*! +* @brief Enable software trigger scan. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_EnableSoftwareTriggerScan(TSI_Type * base) +{ + TSI_BWR_GENCS_STM(base, 0); +} + +/*! +* @brief Enable error interrupt. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_EnableErrorInterrupt(TSI_Type * base) +{ + TSI_BWR_GENCS_ERIE(base, 1); +} + +/*! +* @brief Disable error interrupt. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_DisableErrorInterrupt(TSI_Type * base) +{ + TSI_BWR_GENCS_ERIE(base, 0); +} + +/*! +* @brief Clear out of range flag. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_ClearOutOfRangeFlag(TSI_Type * base) +{ + TSI_BWR_GENCS_OUTRGF(base, 1); +} + +/*! +* @brief Clear end of scan flag. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_ClearEndOfScanFlag(TSI_Type * base) +{ + TSI_BWR_GENCS_EOSF(base, 1); +} + +/*! +* @brief Enable TSI module interrupt. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_EnableInterrupt(TSI_Type * base) +{ + TSI_BWR_GENCS_TSIIE(base, 1); +} + +/*! +* @brief Disable TSI interrupt. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_DisableInterrupt(TSI_Type * base) +{ + TSI_BWR_GENCS_TSIIE(base, 0); +} + +/*! +* @brief Get interrupt enable flag. +* +* @param base TSI module base address. +* @return State of enable interrupt flag. +*/ +static inline uint32_t TSI_HAL_IsInterruptEnabled(TSI_Type * base) +{ + return TSI_BRD_GENCS_TSIIE(base); +} + +/*! +* @brief Start measurement (trigger the new measurement). +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_StartSoftwareTrigger(TSI_Type * base) +{ + TSI_SET_GENCS(base, TSI_GENCS_SWTS(1)); +} + +/*! +* @brief Get overrun flag. +* +* @param base TSI module base address. +* @return State of over run flag. +*/ +static inline uint32_t TSI_HAL_IsOverrun(TSI_Type * base) +{ + return (uint32_t)TSI_BRD_GENCS_OVRF(base); +} + +/*! +* @brief Clear over run flag +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_ClearOverrunFlag(TSI_Type * base) +{ + TSI_BWR_GENCS_OVRF(base, 1); +} + +/*! +* @brief Get external electrode error flag. +* +* @param base TSI module base address. +* @return Stae of external electrode error flag +*/ +static inline uint32_t TSI_HAL_GetExternalElectrodeErrorFlag(TSI_Type * base) +{ + return (uint32_t)TSI_BRD_GENCS_EXTERF(base); +} + +/*! +* @brief Clear external electrode error flag +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_ClearExternalElectrodeErrorFlag(TSI_Type * base) +{ + TSI_BWR_GENCS_EXTERF(base, 1); +} + +/*! +* @brief Set prescaler. +* +* @param base TSI module base address. +* @param prescaler Prescaler value. +* @return None. +*/ +static inline void TSI_HAL_SetPrescaler(TSI_Type * base, tsi_electrode_osc_prescaler_t prescaler) +{ + TSI_BWR_GENCS_PS(base, prescaler); +} + +/*! +* @brief Set number of scans (NSCN). +* +* @param base TSI module base address. +* @param number Number of scans. +* @return None. +*/ +static inline void TSI_HAL_SetNumberOfScans(TSI_Type * base, tsi_n_consecutive_scans_t number) +{ + TSI_BWR_GENCS_NSCN(base, number); +} + +/*! +* @brief Set low power scan interval. +* +* @param base TSI module base address. +* @param interval Interval for low power scan. +* @return None. +*/ +static inline void TSI_HAL_SetLowPowerScanInterval(TSI_Type * base, tsi_low_power_interval_t interval) +{ + TSI_BWR_GENCS_LPSCNITV(base, interval); +} + +/*! +* @brief Get low power scan interval. +* +* @param base TSI module base address. +* @return Interval for low power scan. +*/ +static inline tsi_low_power_interval_t TSI_HAL_GetLowPowerScanInterval(TSI_Type * base) +{ + return (tsi_low_power_interval_t)TSI_BRD_GENCS_LPSCNITV(base); +} + +/*! +* @brief Set low power clock. +* +* @param base TSI module base address. +* @param clock Low power clock selection. +*/ +static inline void TSI_HAL_SetLowPowerClock(TSI_Type * base, uint32_t clock) +{ + TSI_BWR_GENCS_LPCLKS(base, clock); +} + +/*! +* @brief Get low power clock. +* +* @param base TSI module base address. +* @return Low power clock selection. +*/ +static inline uint32_t TSI_HAL_GetLowPowerClock(TSI_Type * base) +{ + return TSI_BRD_GENCS_LPCLKS(base); +} + +/*! +* @brief Set the reference oscilator charge current. +* +* @param base TSI module base address. +* @param current The charge current. +* @return None. +*/ +static inline void TSI_HAL_SetReferenceChargeCurrent(TSI_Type * base, tsi_reference_osc_charge_current_t current) +{ + TSI_BWR_SCANC_REFCHRG(base, current); +} + +/*! +* @brief Get the reference oscilator charge current. +* +* @param base TSI module base address. +* @return The charge current. +*/ +static inline tsi_reference_osc_charge_current_t TSI_HAL_GetReferenceChargeCurrent(TSI_Type * base) +{ + return (tsi_reference_osc_charge_current_t)TSI_BRD_SCANC_REFCHRG(base); +} + +#if (FSL_FEATURE_TSI_VERSION == 1) +/*! +* @brief Set internal capacitance trim. +* +* @param base TSI module base address. +* @param trim Trim value. +* @return None. +*/ +static inline void TSI_HAL_SetInternalCapacitanceTrim(TSI_Type * base, tsi_internal_cap_trim_t trim) +{ + TSI_BWR_SCANC_CAPTRM(base, trim); +} + +/*! +* @brief Get internal capacitance trim. +* +* @param base TSI module base address. +* @return Trim value. +*/ +static inline tsi_internal_cap_trim_t TSI_HAL_GetInternalCapacitanceTrim(TSI_Type * base) +{ + return (tsi_internal_cap_trim_t)TSI_BRD_SCANC_CAPTRM(base); +} + +#endif + +/*! +* @brief Set electrode charge current. +* +* @param base TSI module base address. +* @param current Electrode current. +* @return None. +*/ +static inline void TSI_HAL_SetElectrodeChargeCurrent(TSI_Type * base, tsi_external_osc_charge_current_t current) +{ + TSI_BWR_SCANC_EXTCHRG(base, current); +} + +/*! +* @brief Get electrode charge current. +* +* @param base TSI module base address. +* @return Charge current. +*/ +static inline tsi_external_osc_charge_current_t TSI_HAL_GetElectrodeChargeCurrent(TSI_Type * base) +{ + return (tsi_external_osc_charge_current_t)TSI_BRD_SCANC_EXTCHRG(base); +} + +#if (FSL_FEATURE_TSI_VERSION == 1) +/*! +* @brief Set delta voltage. +* +* @param base TSI module base address. +* @param voltage delta voltage. +* @return None. +*/ +static inline void TSI_HAL_SetDeltaVoltage(TSI_Type * base, uint32_t voltage) +{ + TSI_BWR_SCANC_DELVOL(base, voltage); +} + +/*! +* @brief Get delta voltage. +* +* @param base TSI module base address. +* @return Delta voltage. +*/ +static inline uint32_t TSI_HAL_GetDeltaVoltage(TSI_Type * base) +{ + return TSI_BRD_SCANC_DELVOL(base); +} + +#endif + +/*! +* @brief Set scan modulo value. +* +* @param base TSI module base address. +* @param modulo Scan modulo value. +* @return None. +*/ +static inline void TSI_HAL_SetScanModulo(TSI_Type * base, uint32_t modulo) +{ + TSI_BWR_SCANC_SMOD(base, modulo); +} + +/*! +* @brief Get scan modulo value. +* +* @param base TSI module base address. +* @return Scan modulo value. +*/ +static inline uint32_t TSI_HAL_GetScanModulo(TSI_Type * base) +{ + return TSI_BRD_SCANC_SMOD(base); +} + +#if (FSL_FEATURE_TSI_VERSION == 1) +/*! +* @brief Set active mode clock divider. +* +* @param base TSI module base address. +* @param divider A value for divider. +* @return None. +*/ +static inline void TSI_HAL_SetActiveModeClockDivider(TSI_Type * base, uint32_t divider) +{ + TSI_BWR_SCANC_AMCLKDIV(base, divider); +} + +/*! +* @brief Get active mode clock divider. +* +* @param base TSI module base address. +* @return A value for divider. +*/ +static inline uint32_t TSI_HAL_GetActiveModeClockDivider(TSI_Type * base) +{ + return TSI_BRD_SCANC_AMCLKDIV(base); +} +#endif + +/*! +* @brief Set active mode source. +* +* @param base TSI module base address. +* @param source Active mode clock source (LPOSCCLK, MCGIRCLK, OSCERCLK). +* @return None. +*/ +static inline void TSI_HAL_SetActiveModeSource(TSI_Type * base, uint32_t source) +{ + TSI_BWR_SCANC_AMCLKS(base, source); +} + +/*! +* @brief Get active mode source. +* +* @param base TSI module base address. +* @return Source value. +*/ +static inline uint32_t TSI_HAL_GetActiveModeSource(TSI_Type * base) +{ + return TSI_BRD_SCANC_AMCLKS(base); +} + +/*! +* @brief Set active mode prescaler. +* +* @param base TSI module base address. +* @param prescaler Prescaler's value. +* @return None. +*/ +static inline void TSI_HAL_SetActiveModePrescaler(TSI_Type * base, tsi_active_mode_prescaler_t prescaler) +{ + TSI_BWR_SCANC_AMPSC(base, prescaler); +} + +/*! +* @brief Get active mode prescaler. +* +* @param base TSI module base address. +* @return Prescaler's value. +*/ +static inline uint32_t TSI_HAL_GetActiveModePrescaler(TSI_Type * base) +{ + return TSI_BRD_SCANC_AMPSC(base); +} + +/*! +* @brief Set low power channel. Only one channel can wake up MCU. +* +* @param base TSI module base address. +* @param channel Channel number. +* @return None. +*/ +static inline void TSI_HAL_SetLowPowerChannel(TSI_Type * base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_TSI_CHANNEL_COUNT); + TSI_BWR_PEN_LPSP(base, channel); +} + +/*! + * @brief Get low power channel. Only one channel can wake up MCU. + * + * @param base TSI module base address. + * @return Channel number. + */ +static inline uint32_t TSI_HAL_GetLowPowerChannel(TSI_Type * base) +{ + return TSI_BRD_PEN_LPSP(base); +} + +/*! +* @brief Enable channel. +* +* @param base TSI module base address. +* @param channel Channel to be enabled. +* @return None. +*/ +static inline void TSI_HAL_EnableChannel(TSI_Type * base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_TSI_CHANNEL_COUNT); + TSI_SET_PEN(base, (1U << channel)); +} + +/*! +* @brief Enable channels. The function enables channels by mask. It can set all +* at once. +* +* @param base TSI module base address. +* @param channelsMask Channels mask to be enabled. +* @return None. +*/ +static inline void TSI_HAL_EnableChannels(TSI_Type * base, uint32_t channelsMask) +{ + TSI_SET_PEN(base, (uint16_t)channelsMask); +} + +/*! +* @brief Disable channel. +* +* @param base TSI module base address. +* @param channel Channel to be disabled. +* @return None. +*/ +static inline void TSI_HAL_DisableChannel(TSI_Type * base, uint32_t channel) +{ + TSI_CLR_PEN(base, (1U << channel)); +} + +/*! +* @brief Disable channels. The function disables channels by mask. It can set all +* at once. +* +* @param base TSI module base address. +* @param channelsMask Channels mask to be disabled. +* @return None. +*/ +static inline void TSI_HAL_DisableChannels(TSI_Type * base, uint32_t channelsMask) +{ + TSI_CLR_PEN(base, channelsMask); +} + +/*! + * @brief Returns if channel is enabled. + * + * @param base TSI module base address. + * @param channel Channel to be checked. + * + * @return True - if channel is enabled, false - otherwise. + */ +static inline uint32_t TSI_HAL_GetEnabledChannel(TSI_Type * base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_TSI_CHANNEL_COUNT); + return (TSI_RD_PEN(base) & (1U << channel)); +} + +/*! +* @brief Returns mask of enabled channels. +* +* @param base TSI module base address. +* @return Channels mask that are enabled. +*/ +static inline uint32_t TSI_HAL_GetEnabledChannels(TSI_Type * base) +{ + return (uint32_t)TSI_RD_PEN(base); +} + +/*! +* @brief Set the Wake up channel counter. +* +* @param base TSI module base address. +* @return Wake up counter value. +*/ +static inline uint16_t TSI_HAL_GetWakeUpChannelCounter(TSI_Type * base) +{ + return TSI_BRD_WUCNTR_WUCNT(base); +} + +/*! +* @brief Get tsi counter on actual channel. +* +* @param base TSI module base address. +* @param channel Index of TSI channel. +* +* @return The counter value. +*/ +static inline uint32_t TSI_HAL_GetCounter(TSI_Type * base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_TSI_CHANNEL_COUNT); + uint16_t *counter = (uint16_t *)((uint32_t)(&(TSI_CNTR1_REG(base))) + (channel * 2U)); + return (uint32_t)(*counter); +} + +/*! +* @brief Set low threshold. +* +* @param base TSI module base address. +* @param low_threshold Low counter threshold. +* @return None. +*/ +static inline void TSI_HAL_SetLowThreshold(TSI_Type * base, uint32_t low_threshold) +{ + TSI_BWR_THRESHOLD_LTHH(base, low_threshold); +} + +/*! +* @brief Set high threshold. +* +* @param base TSI module base address. +* @param high_threshold High counter threshold. +* @return None. +*/ +static inline void TSI_HAL_SetHighThreshold(TSI_Type * base, uint32_t high_threshold) +{ + TSI_BWR_THRESHOLD_HTHH(base, high_threshold); +} + +#ifdef __cplusplus +} +#endif + + +/*! @}*/ + +#endif +#endif /* __FSL_TSI_V2_HAL_SPECIFIC_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_tsi_v4_hal_specific.h b/KSDK_1.2.0/platform/hal/inc/fsl_tsi_v4_hal_specific.h new file mode 100755 index 0000000..bd46937 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_tsi_v4_hal_specific.h @@ -0,0 +1,661 @@ +/* + * Copyright (c) 2013, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_TSI_V4_HAL_SPECIFIC_H__ +#define __FSL_TSI_V4_HAL_SPECIFIC_H__ + +#include <stdint.h> +#include "fsl_device_registers.h" +#include "fsl_tsi_hal.h" +#if FSL_FEATURE_SOC_TSI_COUNT + +/*! + * @addtogroup tsi_hal + * @{ + */ + + +/*! @file*/ + +extern uint32_t tsi_hal_gencs/*[TSI_INSTANCE_COUNT]*/; + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief TSI analog mode select. + * + * Set up TSI analog modes in a TSI instance. + */ +typedef enum _tsi_analog_mode_select { + kTsiAnalogModeSel_Capacitive = 0, /*!< Active TSI capacitive sensing mode */ + kTsiAnalogModeSel_NoiseNoFreqLim = 4, /*!< TSI works in single threshold noise detection mode and the freq. limitation +is disabled */ + kTsiAnalogModeSel_NoiseFreqLim = 8, /*!< TSI analog works in single threshold noise detection mode and the freq. limitation +is enabled */ + kTsiAnalogModeSel_AutoNoise = 12, /*!/ Active TSI analog in automatic noise detection mode */ +} tsi_analog_mode_select_t; + +/*! + * @brief TSI Reference oscillator charge and discharge current select. + * + * These constants define the tsi Reference oscillator charge current select in a TSI (REFCHRG) instance. + */ +typedef enum _tsi_reference_osc_charge_current { + kTsiRefOscChargeCurrent_500nA = 0, /*!< Reference oscillator charge current is 500nA */ + kTsiRefOscChargeCurrent_1uA = 1, /*!< Reference oscillator charge current is 1uA */ + kTsiRefOscChargeCurrent_2uA = 2, /*!< Reference oscillator charge current is 2uA */ + kTsiRefOscChargeCurrent_4uA = 3, /*!< Reference oscillator charge current is 4uA */ + kTsiRefOscChargeCurrent_8uA = 4, /*!< Reference oscillator charge current is 8uA */ + kTsiRefOscChargeCurrent_16uA = 5, /*!< Reference oscillator charge current is 16uA */ + kTsiRefOscChargeCurrent_32uA = 6, /*!< Reference oscillator charge current is 32uA */ + kTsiRefOscChargeCurrent_64uA = 7, /*!< Reference oscillator charge current is 64uA */ +} tsi_reference_osc_charge_current_t; + +/*! + * @brief TSI Reference oscillator charge current select limits. + * + * These constants define the limits of the TSI Reference oscillator charge current select in a TSI instance. + */ +typedef struct _tsi_reference_osc_charge_current_limits +{ + tsi_reference_osc_charge_current_t upper; /*!< Reference oscillator charge current upper limit */ + tsi_reference_osc_charge_current_t lower; /*!< Reference oscillator charge current lower limit */ +}tsi_reference_osc_charge_current_limits_t; + + +/*! + * @brief TSI oscilator's voltage rails. + * + * These bits indicate the oscillator's voltage rails. + */ +typedef enum _tsi_oscilator_voltage_rails { + kTsiOscVolRails_Dv_103 = 0, /*!< DV = 1.03 V; VP = 1.33 V; Vm = 0.30 V */ + kTsiOscVolRails_Dv_073 = 1, /*!< DV = 0.73 V; VP = 1.18 V; Vm = 0.45 V */ + kTsiOscVolRails_Dv_043 = 2, /*!< DV = 0.43 V; VP = 1.03 V; Vm = 0.60 V */ + kTsiOscVolRails_Dv_029 = 3, /*!< DV = 0.29 V; VP = 0.95 V; Vm = 0.67 V */ +} tsi_oscilator_voltage_rails_t; + +/*! + * @brief TSI External oscillator charge and discharge current select. + * + * These bits indicate the electrode oscillator charge and discharge current value + * in TSI (EXTCHRG) instance. + */ +typedef enum _tsi_external_osc_charge_current { + kTsiExtOscChargeCurrent_500nA = 0, /*!< External oscillator charge current is 500nA */ + kTsiExtOscChargeCurrent_1uA = 1, /*!< External oscillator charge current is 1uA */ + kTsiExtOscChargeCurrent_2uA = 2, /*!< External oscillator charge current is 2uA */ + kTsiExtOscChargeCurrent_4uA = 3, /*!< External oscillator charge current is 4uA */ + kTsiExtOscChargeCurrent_8uA = 4, /*!< External oscillator charge current is 8uA */ + kTsiExtOscChargeCurrent_16uA = 5, /*!< External oscillator charge current is 16uA */ + kTsiExtOscChargeCurrent_32uA = 6, /*!< External oscillator charge current is 32uA */ + kTsiExtOscChargeCurrent_64uA = 7, /*!< External oscillator charge current is 64uA */ +} tsi_external_osc_charge_current_t; + +/*! + * @brief TSI External oscillator charge current select limits. + * + * These constants define the limits of the TSI External oscillator charge current select in a TSI instance. + */ +typedef struct _tsi_external_osc_charge_current_limits +{ + tsi_external_osc_charge_current_t upper; /*!< External oscillator charge current upper limit */ + tsi_external_osc_charge_current_t lower; /*!< External oscillator charge current lower limit */ +}tsi_external_osc_charge_current_limits_t; + + +/*! + * @brief TSI channel number. + * + * These bits specify current channel to be measured. + */ +typedef enum _tsi_channel_number { + kTsiChannelNumber_0 = 0, /*!< Channel Number 0 */ + kTsiChannelNumber_1 = 1, /*!< Channel Number 1 */ + kTsiChannelNumber_2 = 2, /*!< Channel Number 2 */ + kTsiChannelNumber_3 = 3, /*!< Channel Number 3 */ + kTsiChannelNumber_4 = 4, /*!< Channel Number 4 */ + kTsiChannelNumber_5 = 5, /*!< Channel Number 5 */ + kTsiChannelNumber_6 = 6, /*!< Channel Number 6 */ + kTsiChannelNumber_7 = 7, /*!< Channel Number 7 */ + kTsiChannelNumber_8 = 8, /*!< Channel Number 8 */ + kTsiChannelNumber_9 = 9, /*!< Channel Number 9 */ + kTsiChannelNumber_10 = 10, /*!< Channel Number 10 */ + kTsiChannelNumber_11 = 11, /*!< Channel Number 11 */ + kTsiChannelNumber_12 = 12, /*!< Channel Number 12 */ + kTsiChannelNumber_13 = 13, /*!< Channel Number 13 */ + kTsiChannelNumber_14 = 14, /*!< Channel Number 14 */ + kTsiChannelNumber_15 = 15, /*!< Channel Number 15 */ +} tsi_channel_number_t; + +/*! + * @brief TSI configuration structure. + * + * This structure contains the settings for the most common TSI configurations including + * the TSI module charge currents, number of scans, thresholds etc. + */ +typedef struct TsiConfig { + tsi_electrode_osc_prescaler_t ps; /*!< Prescaler */ + tsi_external_osc_charge_current_t extchrg; /*!< Electrode charge current */ + tsi_reference_osc_charge_current_t refchrg; /*!< Reference charge current */ + tsi_n_consecutive_scans_t nscn; /*!< Number of scans. */ + tsi_analog_mode_select_t mode; /*!< TSI mode of operation. */ + tsi_oscilator_voltage_rails_t dvolt; /*!< Oscillator's voltage rails. */ + uint16_t thresh; /*!< High threshold. */ + uint16_t thresl; /*!< Low threshold. */ +}tsi_config_t; + +/*! +* @brief TSI operation mode limits +* +* These constants is used to specify the valid range of settings for the recalibration process of TSI parameters +*/ +typedef struct _tsi_parameter_limits { + tsi_n_consecutive_scans_limits_t consNumberOfScan; /*!< number of consecutive scan limits */ + tsi_reference_osc_charge_current_limits_t refOscChargeCurrent; /*!< Reference oscillator charge current limits */ + tsi_external_osc_charge_current_limits_t extOscChargeCurrent; /*!< External oscillator charge current limits */ +}tsi_parameter_limits_t; + +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * @brief Enable low power for TSI module. + * + * @param base TSI module base address. + * + * @return none + * + */ +void TSI_HAL_EnableLowPower(TSI_Type * base); + +/*! +* @brief Enable out of range interrupt. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_EnableOutOfRangeInterrupt(TSI_Type * base) +{ + tsi_hal_gencs &= ~TSI_GENCS_ESOR_MASK; + TSI_WR_GENCS(base, tsi_hal_gencs); +} + +/*! +* @brief Enable end of scan interrupt. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_EnableEndOfScanInterrupt(TSI_Type * base) +{ + tsi_hal_gencs |= TSI_GENCS_ESOR_MASK; + TSI_WR_GENCS(base, tsi_hal_gencs); +} + +/*! +* @brief Enable Touch Sensing Input Module. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_EnableModule(TSI_Type * base) +{ + tsi_hal_gencs |= TSI_GENCS_TSIEN_MASK; + TSI_WR_GENCS(base, tsi_hal_gencs); +} + +/*! +* @brief Disable Touch Sensing Input Module. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_DisableModule(TSI_Type * base) +{ + tsi_hal_gencs &= ~TSI_GENCS_TSIEN_MASK; + TSI_WR_GENCS(base, tsi_hal_gencs); +} + +/*! +* @brief Enable TSI module interrupt. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_EnableInterrupt(TSI_Type * base) +{ + tsi_hal_gencs |= TSI_GENCS_TSIIEN_MASK; + TSI_WR_GENCS(base, tsi_hal_gencs); +} + +/*! +* @brief Disable TSI interrupt. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_DisableInterrupt(TSI_Type * base) +{ + tsi_hal_gencs &= ~TSI_GENCS_TSIIEN_MASK; + TSI_WR_GENCS(base, tsi_hal_gencs); +} + +/*! +* @brief Get interrupt enable flag. +* +* @param base TSI module base address. +* @return State of enable interrupt flag. +*/ +static inline uint32_t TSI_HAL_IsInterruptEnabled(TSI_Type * base) +{ + return TSI_BRD_GENCS_TSIIEN(base); +} + +/*! +* @brief Get TSI STOP enable. +* +* @param base TSI module base address. +* @return Number of scans. +*/ +static inline uint32_t TSI_HAL_GetEnableStop(TSI_Type * base) +{ + return (uint32_t)TSI_BRD_GENCS_STPE(base); +} + +/*! +* @brief Set TSI STOP enable. This enables TSI module function in low power modes. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_EnableStop(TSI_Type * base) +{ + tsi_hal_gencs |= TSI_GENCS_STPE_MASK; + TSI_WR_GENCS(base, tsi_hal_gencs); +} + +/*! +* @brief Set TSI STOP disable. The TSI is disabled in low power modes. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_DisableStop(TSI_Type * base) +{ + tsi_hal_gencs &= ~TSI_GENCS_STPE_MASK; + TSI_WR_GENCS(base, tsi_hal_gencs); +} + +/*! +* @brief Enable periodical (hardware) trigger scan. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_EnableHardwareTriggerScan(TSI_Type * base) +{ + tsi_hal_gencs |= TSI_GENCS_STM_MASK; + TSI_WR_GENCS(base, tsi_hal_gencs); +} + +/*! +* @brief Enable periodical (hardware) trigger scan. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_EnableSoftwareTriggerScan(TSI_Type * base) +{ + tsi_hal_gencs &= ~TSI_GENCS_STM_MASK; + TSI_WR_GENCS(base, tsi_hal_gencs); +} + +/*! +* @brief The current sources (CURSW) of electrode oscillator and reference +* oscillator are swapped. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_CurrentSourcePairSwapped(TSI_Type * base) +{ + tsi_hal_gencs |= TSI_GENCS_CURSW_MASK; + TSI_WR_GENCS(base, tsi_hal_gencs); +} + +/*! +* @brief The current sources (CURSW) of electrode oscillator and reference +* oscillator are not swapped. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_CurrentSourcePairNotSwapped(TSI_Type * base) +{ + tsi_hal_gencs &= ~TSI_GENCS_CURSW_MASK; + TSI_WR_GENCS(base, tsi_hal_gencs); +} + +/*! +* @brief Get current source pair swapped status. +* +* @param base TSI module base address. +* @return Current source pair swapped status. +*/ +static inline uint32_t TSI_HAL_GetCurrentSourcePairSwapped(TSI_Type * base) +{ + return (uint32_t)TSI_BRD_GENCS_CURSW(base); +} + +/*! +* @brief Clear out of range flag. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_ClearOutOfRangeFlag(TSI_Type * base) +{ + TSI_WR_GENCS(base, (tsi_hal_gencs | TSI_GENCS_OUTRGF_MASK)); +} + + +/*! +* @brief Clear end of scan flag. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_ClearEndOfScanFlag(TSI_Type * base) +{ + TSI_WR_GENCS(base, (tsi_hal_gencs | TSI_GENCS_EOSF_MASK)); +} + +/*! +* @brief Set prescaler. +* +* @param base TSI module base address. +* @param prescaler Prescaler value. +* @return None. +*/ +static inline void TSI_HAL_SetPrescaler(TSI_Type * base, tsi_electrode_osc_prescaler_t prescaler) +{ + tsi_hal_gencs &= ~TSI_GENCS_PS_MASK; + tsi_hal_gencs |= TSI_GENCS_PS(prescaler); + TSI_WR_GENCS(base, tsi_hal_gencs); +} + +/*! +* @brief Set number of scans (NSCN). +* +* @param base TSI module base address. +* @param number Number of scans. +* @return None. +*/ +static inline void TSI_HAL_SetNumberOfScans(TSI_Type * base, tsi_n_consecutive_scans_t number) +{ + tsi_hal_gencs &= ~TSI_GENCS_NSCN_MASK; + tsi_hal_gencs |= TSI_GENCS_NSCN(number); + TSI_WR_GENCS(base, tsi_hal_gencs); +} + +/*! +* @brief Set the measured channel number. +* +* @param base TSI module base address. +* @param channel Channel number 0 ... 15. +* @return None. +*/ +static inline void TSI_HAL_SetMeasuredChannelNumber(TSI_Type * base, uint32_t channel) +{ + assert(channel < FSL_FEATURE_TSI_CHANNEL_COUNT); + TSI_BWR_DATA_TSICH(base, channel); +} + +/*! +* @brief Get the measured channel number. +* +* @param base TSI module base address. +* @return uint32_t Channel number 0 ... 15. +*/ +static inline uint32_t TSI_HAL_GetMeasuredChannelNumber(TSI_Type * base) +{ + return (uint32_t)TSI_BRD_DATA_TSICH(base); +} + +/*! +* @brief DMA transfer enable. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_DmaTransferEnable(TSI_Type * base) +{ + TSI_BWR_DATA_DMAEN(base, 1); +} + +/*! +* @brief DMA transfer disable - do not generate DMA transfer request. +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_DmaTransferDisable(TSI_Type * base) +{ + TSI_BWR_DATA_DMAEN(base, 0); +} + +/*! +* @brief Get DMA transfer enable flag. +* +* @param base TSI module base address. +* @return State of enable module flag. +*/ +static inline uint32_t TSI_HAL_IsDmaTransferEnable(TSI_Type * base) +{ + return TSI_BRD_DATA_DMAEN(base); +} + +/*! +* @brief Start measurement (trigger the new measurement). +* +* @param base TSI module base address. +* @return None. +*/ +static inline void TSI_HAL_StartSoftwareTrigger(TSI_Type * base) +{ + TSI_SET_DATA(base, TSI_DATA_SWTS(1)); +} + +/*! +* @brief Get conversion counter value. +* +* @param base TSI module base address. +* @return Accumulated scan counter value ticked by the reference clock. +*/ +static inline uint32_t TSI_HAL_GetCounter(TSI_Type * base) +{ + return (uint32_t)TSI_BRD_DATA_TSICNT(base); +} + +/*! +* @brief Set TSI wake-up channel low threshold. +* +* @param base TSI module base address. +* @param low_threshold Low counter threshold. +* @return None. +*/ +static inline void TSI_HAL_SetLowThreshold(TSI_Type * base, uint32_t low_threshold) +{ + assert(low_threshold < 65535U); + TSI_BWR_TSHD_THRESL(base, low_threshold); +} + +/*! +* @brief Set TSI wake-up channel high threshold. +* +* @param base TSI module base address. +* @param high_threshold High counter threshold. +* @return None. +*/ +static inline void TSI_HAL_SetHighThreshold(TSI_Type * base, uint32_t high_threshold) +{ + assert(high_threshold < 65535U); + TSI_BWR_TSHD_THRESH(base, high_threshold); +} + +/*! +* @brief Set analog mode of the TSI module. +* +* @param base TSI module base address. +* @param mode Mode value. +* @return None. +*/ +static inline void TSI_HAL_SetMode(TSI_Type * base, tsi_analog_mode_select_t mode) +{ + tsi_hal_gencs &= ~TSI_GENCS_MODE_MASK; + tsi_hal_gencs |= TSI_GENCS_MODE(mode); + TSI_WR_GENCS(base, tsi_hal_gencs); +} + +/*! +* @brief Get analog mode of the TSI module. +* +* @param base TSI module base address. +* @return tsi_analog_mode_select_t Mode value. +*/ +static inline tsi_analog_mode_select_t TSI_HAL_GetMode(TSI_Type * base) +{ + return (tsi_analog_mode_select_t)((tsi_hal_gencs & TSI_GENCS_MODE_MASK) >> TSI_GENCS_MODE_SHIFT); +} + +/*! +* @brief Get analog mode of the TSI module. +* +* @param base TSI module base address. +* @return tsi_analog_mode_select_t Mode value. +*/ +static inline uint32_t TSI_HAL_GetNoiseResult(TSI_Type * base) +{ + uint32_t gencs = TSI_RD_GENCS(base); + + return (gencs & TSI_GENCS_MODE_MASK) >> TSI_GENCS_MODE_SHIFT; +} + +/*! +* @brief Set the reference oscilator charge current. +* +* @param base TSI module base address. +* @param current The charge current. +* @return None. +*/ +static inline void TSI_HAL_SetReferenceChargeCurrent(TSI_Type * base, tsi_reference_osc_charge_current_t current) +{ + tsi_hal_gencs &= ~TSI_GENCS_REFCHRG_MASK; + tsi_hal_gencs |= TSI_GENCS_REFCHRG(current); + TSI_WR_GENCS(base, tsi_hal_gencs); +} + +/*! +* @brief Get the reference oscilator charge current. +* +* @param base TSI module base address. +* @return tsi_reference_osc_charge_current_t The charge current. +*/ +static inline tsi_reference_osc_charge_current_t TSI_HAL_GetReferenceChargeCurrent(TSI_Type * base) +{ + return (tsi_reference_osc_charge_current_t)TSI_GENCS_REFCHRG(tsi_hal_gencs); +} + +/*! +* @brief Set the oscilator's volatage rails. +* +* @param base TSI module base address. +* @param dvolt The voltage rails. +* @return None. +*/ +static inline void TSI_HAL_SetOscilatorVoltageRails(TSI_Type * base, tsi_oscilator_voltage_rails_t dvolt) +{ + tsi_hal_gencs &= ~TSI_GENCS_DVOLT_MASK; + tsi_hal_gencs |= TSI_GENCS_DVOLT(dvolt); + TSI_WR_GENCS(base, tsi_hal_gencs); +} + +/*! +* @brief Get the oscilator's volatage rails. +* +* @param base TSI module base address. +* @return dvolt The voltage rails.. +*/ +static inline tsi_oscilator_voltage_rails_t TSI_HAL_GetOscilatorVoltageRails(TSI_Type * base) +{ + return (tsi_oscilator_voltage_rails_t)TSI_BRD_GENCS_DVOLT(base); +} + +/*! +* @brief Set external electrode charge current. +* +* @param base TSI module base address. +* @param current Electrode current. +* @return None. +*/ +static inline void TSI_HAL_SetElectrodeChargeCurrent(TSI_Type * base, tsi_external_osc_charge_current_t current) +{ + tsi_hal_gencs &= ~TSI_GENCS_EXTCHRG_MASK; + tsi_hal_gencs |= TSI_GENCS_EXTCHRG(current); + TSI_WR_GENCS(base, tsi_hal_gencs); +} + +/*! +* @brief Get electrode charge current. +* +* @param base TSI module base address. +* @return Charge current. +*/ +static inline tsi_external_osc_charge_current_t TSI_HAL_GetElectrodeChargeCurrent(TSI_Type * base) +{ + return (tsi_external_osc_charge_current_t)TSI_BRD_GENCS_EXTCHRG(base); +} + +#ifdef __cplusplus +} +#endif + +#endif + +/*! @}*/ + +#endif /* __FSL_TSI_V4_HAL_H_SPECIFIC__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_uart_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_uart_hal.h new file mode 100755 index 0000000..8db8eb6 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_uart_hal.h @@ -0,0 +1,1953 @@ +/* + * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_UART_HAL_H__ +#define __FSL_UART_HAL_H__ + +#include <assert.h> +#include <stdint.h> +#include <stdbool.h> +#include "fsl_device_registers.h" + +/*! + * @addtogroup uart_hal + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define UART_SHIFT (8U) + +/*! @brief Error codes for the UART driver. */ +typedef enum _uart_status +{ + kStatus_UART_Success = 0x00U, + kStatus_UART_Fail = 0x01U, + kStatus_UART_BaudRateCalculationError = 0x02U, + kStatus_UART_RxStandbyModeError = 0x03U, + kStatus_UART_ClearStatusFlagError = 0x04U, + kStatus_UART_TxNotDisabled = 0x05U, + kStatus_UART_RxNotDisabled = 0x06U, + kStatus_UART_TxOrRxNotDisabled = 0x07U, + kStatus_UART_TxBusy = 0x08U, + kStatus_UART_RxBusy = 0x09U, + kStatus_UART_NoTransmitInProgress = 0x0AU, + kStatus_UART_NoReceiveInProgress = 0x0BU, + kStatus_UART_Timeout = 0x0CU, + kStatus_UART_Initialized = 0x0DU, + kStatus_UART_NoDataToDeal = 0x0EU, + kStatus_UART_RxOverRun = 0x0FU +} uart_status_t; + +/*! + * @brief UART number of stop bits. + * + * These constants define the number of allowable stop bits to configure in a UART base. + */ +typedef enum _uart_stop_bit_count { + kUartOneStopBit = 0U, /*!< one stop bit @internal gui name="1" */ + kUartTwoStopBit = 1U, /*!< two stop bits @internal gui name="2" */ +} uart_stop_bit_count_t; + +/*! + * @brief UART parity mode. + * + * These constants define the UART parity mode options: disabled or enabled of type even or odd. + */ +typedef enum _uart_parity_mode { + kUartParityDisabled = 0x0U, /*!< parity disabled @internal gui name="Disabled" */ + kUartParityEven = 0x2U, /*!< parity enabled, type even, bit setting: PE|PT = 10 @internal gui name="Even" */ + kUartParityOdd = 0x3U, /*!< parity enabled, type odd, bit setting: PE|PT = 11 @internal gui name="Odd" */ +} uart_parity_mode_t; + +/*! + * @brief UART number of bits in a character. + * + * These constants define the number of allowable data bits per UART character. Note, check the + * UART documentation to determine if the desired UART base supports the desired number + * of data bits per UART character. + */ +typedef enum _uart_bit_count_per_char { + kUart8BitsPerChar = 0U, /*!< 8-bit data characters @internal gui name="8" */ + kUart9BitsPerChar = 1U, /*!< 9-bit data characters @internal gui name="9" */ +} uart_bit_count_per_char_t; + +/*! + * @brief UART operation configuration constants. + * + * This provides constants for UART operational states: "operates normally" + * or "stops/ceases operation" + */ +typedef enum _uart_operation_config { + kUartOperates = 0U, /*!< UART continues to operate normally */ + kUartStops = 1U, /*!< UART ceases operation */ +} uart_operation_config_t; + +/*! @brief UART receiver source select mode. */ +typedef enum _uart_receiver_source { + kUartLoopBack = 0U, /*!< Internal loop back mode. */ + kUartSingleWire = 1U,/*!< Single wire mode. */ +} uart_receiver_source_t ; + +/*! + * @brief UART wakeup from standby method constants. + * + * This provides constants for the two UART wakeup methods: idle-line or address-mark. + */ +typedef enum _uart_wakeup_method { + kUartIdleLineWake = 0U, /*!< The idle-line wakes UART receiver from standby */ + kUartAddrMarkWake = 1U, /*!< The address-mark wakes UART receiver from standby */ +} uart_wakeup_method_t; + +/*! + * @brief UART idle-line detect selection types. + * + * This provides constants for the UART idle character bit-count start: either after start or + * stop bit. + */ +typedef enum _uart_idle_line_select { + kUartIdleLineAfterStartBit = 0U, /*!< UART idle character bit count start after start bit */ + kUartIdleLineAfterStopBit = 1U, /*!< UART idle character bit count start after stop bit */ +} uart_idle_line_select_t; + +/*! + * @brief UART break character length settings for transmit/detect. + * + * This provides constants for the UART break character length for both transmission and detection + * purposes. Note that the actual maximum bit times may vary depending on the UART base. + */ +typedef enum _uart_break_char_length { + kUartBreakChar10BitMinimum = 0U, /*!< UART break char length 10 bit times (if M = 0, SBNS = 0) or + 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, + SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1) */ + kUartBreakChar13BitMinimum = 1U, /*!< UART break char length 13 bit times (if M = 0, SBNS = 0) or + 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, + SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1) */ +} uart_break_char_length_t; + +/*! + * @brief UART single-wire mode transmit direction. + * + * This provides constants for the UART transmit direction when configured for single-wire mode. + * The transmit line TXDIR is either an input or output. + */ +typedef enum _uart_singlewire_txdir { + kUartSinglewireTxdirIn = 0U, /*!< UART Single-Wire mode TXDIR input */ + kUartSinglewireTxdirOut = 1U, /*!< UART Single-Wire mode TXDIR output */ +} uart_singlewire_txdir_t; + +/*! + * @brief UART infrared transmitter pulse width options. + * + * This provides constants for the UART infrared (IR) pulse widths. Options include 3/16, 1/16 + * 1/32, and 1/4 pulse widths. + */ +typedef enum _uart_ir_tx_pulsewidth { + kUartIrThreeSixteenthsWidth = 0U, /*!< 3/16 pulse */ + kUartIrOneSixteenthWidth = 1U, /*!< 1/16 pulse */ + kUartIrOneThirtysecondsWidth = 2U, /*!< 1/32 pulse */ + kUartIrOneFourthWidth = 3U, /*!< 1/4 pulse */ +} uart_ir_tx_pulsewidth_t; + +/*! + * @brief UART ISO7816 transport protocol type options. + * + * This provides constants for the UART ISO7816 transport ptotocol types. + */ +typedef enum _uart_iso7816_tranfer_protocoltype { + kUartIso7816TransfertType0 = 0U, /*!< Transfer type 0 */ + kUartIso7816TransfertType1 = 1U, /*!< Transfer type 1 */ +} uart_iso7816_transfer_protocoltype_t; + +/*! + * @brief UART ISO7816 ONACK generation. + * + * This provides constants for the UART ISO7816 module ONACK generation. + */ +typedef enum _uart_iso7816_onack_config{ + kUartIso7816OnackEnable = 0U, /*!< Enable ONACK generation */ + kUartIso7816OnackDisable = 1U, /*!< Disable ONACK generation */ +} uart_iso7816_onack_config_t; + +/*! + * @brief UART ISO7816 ANACK generation. + * + * This provides constants for the UART ISO7816 module ANACK generation. + */ +typedef enum _uart_iso7816_anack_config{ + kUartIso7816AnackDisable = 0U, /*!< Disable ANACK generation */ + kUartIso7816AnackEnable = 1U, /*!< Enable ANACK generation */ +} uart_iso7816_anack_config_t; + +/*! + * @brief UART ISO7816 Initital Character detection. + * + * This provides constants for the UART ISO7816 module Initial generation. + */ +typedef enum _uart_iso7816_initd_config{ + kUartIso7816InitdDisable = 0U, /*!< Disable Initial Character detection */ + kUartIso7816InitdEnable = 1U, /*!< Enable Initial Character detection */ +} uart_iso7816_initd_config_t; + +/*! + * @brief UART status flags. + * + * This provides constants for the UART status flags for use in the UART functions. + */ +typedef enum _uart_status_flag { + kUartTxDataRegEmpty = 0U << UART_SHIFT | UART_S1_TDRE_SHIFT, /*!< Tx data register empty flag, sets when Tx buffer is empty */ + kUartTxComplete = 0U << UART_SHIFT | UART_S1_TC_SHIFT, /*!< Transmission complete flag, sets when transmission activity complete */ + kUartRxDataRegFull = 0U << UART_SHIFT | UART_S1_RDRF_SHIFT, /*!< Rx data register full flag, sets when the receive data buffer is full */ + kUartIdleLineDetect = 0U << UART_SHIFT | UART_S1_IDLE_SHIFT, /*!< Idle line detect flag, sets when idle line detected */ + kUartRxOverrun = 0U << UART_SHIFT | UART_S1_OR_SHIFT, /*!< Rx Overrun, sets when new data is received before data is read from receive register */ + kUartNoiseDetect = 0U << UART_SHIFT | UART_S1_NF_SHIFT, /*!< Rx takes 3 samples of each received bit. If any of these samples differ, noise flag sets */ + kUartFrameErr = 0U << UART_SHIFT | UART_S1_FE_SHIFT, /*!< Frame error flag, sets if logic 0 was detected where stop bit expected */ + kUartParityErr = 0U << UART_SHIFT | UART_S1_PF_SHIFT, /*!< If parity enabled, sets upon parity error detection */ +#if FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT + kUartLineBreakDetect = 1U << UART_SHIFT | UART_S2_LBKDIF_SHIFT, /*!< LIN break detect interrupt flag, sets when LIN break char detected and LIN circuit enabled */ +#endif + kUartRxActiveEdgeDetect = 1U << UART_SHIFT | UART_S2_RXEDGIF_SHIFT, /*!< Rx pin active edge interrupt flag, sets when active edge detected */ + kUartRxActive = 1U << UART_SHIFT | UART_S2_RAF_SHIFT, /*!< Receiver Active Flag (RAF), sets at beginning of valid start bit */ +#if FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS + kUartNoiseInCurrentWord = 2U << UART_SHIFT | UART_ED_NOISY_SHIFT, /*!< NOISY bit, sets if noise detected in current data word */ + kUartParityErrInCurrentWord = 2U << UART_SHIFT | UART_ED_PARITYE_SHIFT, /*!< PARITYE bit, sets if noise detected in current data word */ +#endif +#if FSL_FEATURE_UART_HAS_FIFO + kUartTxBuffEmpty = 3U << UART_SHIFT | UART_SFIFO_TXEMPT_SHIFT, /*!< TXEMPT bit, sets if Tx buffer is empty */ + kUartRxBuffEmpty = 3U << UART_SHIFT | UART_SFIFO_RXEMPT_SHIFT, /*!< RXEMPT bit, sets if Rx buffer is empty */ + kUartTxBuffOverflow = 3U << UART_SHIFT | UART_SFIFO_TXOF_SHIFT, /*!< TXOF bit, sets if Tx buffer overflow occurred */ + kUartRxBuffUnderflow = 3U << UART_SHIFT | UART_SFIFO_RXUF_SHIFT, /*!< RXUF bit, sets if receive buffer underflow occurred */ +#endif +} uart_status_flag_t; + +/*! + * @brief UART interrupt configuration structure, default settings are 0 (disabled). + * + * This structure contains the settings for all of the UART interrupt configurations. + */ +typedef enum _uart_interrupt { +#if FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT + kUartIntLinBreakDetect = 0U << UART_SHIFT | UART_BDH_LBKDIE_SHIFT, /*!< LIN break detect. */ +#endif + kUartIntRxActiveEdge = 0U << UART_SHIFT | UART_BDH_RXEDGIE_SHIFT, /*!< RX Active Edge. */ + kUartIntTxDataRegEmpty = 1U << UART_SHIFT | UART_C2_TIE_SHIFT, /*!< Transmit data register empty. */ + kUartIntTxComplete = 1U << UART_SHIFT | UART_C2_TCIE_SHIFT, /*!< Transmission complete. */ + kUartIntRxDataRegFull = 1U << UART_SHIFT | UART_C2_RIE_SHIFT, /*!< Receiver data register full. */ + kUartIntIdleLine = 1U << UART_SHIFT | UART_C2_ILIE_SHIFT, /*!< Idle line. */ + kUartIntRxOverrun = 2U << UART_SHIFT | UART_C3_ORIE_SHIFT, /*!< Receiver Overrun. */ + kUartIntNoiseErrFlag = 2U << UART_SHIFT | UART_C3_NEIE_SHIFT, /*!< Noise error flag. */ + kUartIntFrameErrFlag = 2U << UART_SHIFT | UART_C3_FEIE_SHIFT, /*!< Framing error flag. */ + kUartIntParityErrFlag = 2U << UART_SHIFT | UART_C3_PEIE_SHIFT, /*!< Parity error flag. */ +#if FSL_FEATURE_UART_HAS_FIFO + kUartIntTxFifoOverflow = 3U << UART_SHIFT | UART_CFIFO_TXOFE_SHIFT, /*!< TX FIFO Overflow. */ + kUartIntRxFifoUnderflow = 3U << UART_SHIFT | UART_CFIFO_RXUFE_SHIFT, /*!< RX FIFO Underflow. */ +#endif +} uart_interrupt_t; + +/*! + * @brief UART ISO7816 specific interrupt configuration. + * + * This enum contains the settings for all of the UART ISO7816 feature specfic interrupt configurations. + */ +typedef enum _uart_iso7816_interrupt { + kUartIntIso7816RxThreasholdExceeded = 0U, /*!< Receive Threashold Exceeded. */ + kUartIntIso7816TxThresholdExceeded = 1U, /*!< TransmitThresholdExceeded. */ + kUartIntIso7816GuardTimerViolated = 2U, /*!< Guard Timer Violated. */ + kUartIntIso7816AtrDurationTimer = 3U, /*!< ATR Duration Timer. */ + kUartIntIso7816InitialCharDetected = 4U, /*!< Initial Character Detected. */ + kUartIntIso7816BlockWaitTimer = 5U, /*!< Block Wait Timer. */ + kUartIntIso7816CharWaitTimer = 6U, /*!< Character Wait Timer. */ + kUartIntIso7816WaitTimer = 7U, /*!< Wait Timer. */ + kUartIntIso7816All = 8U, /*<!All above. */ +} uart_iso7816_interrupt_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name UART Common Configurations + * @{ + */ + +/*! + * @brief Initializes the UART controller. + * + * This function initializes the module to a known state. + * + * @param base UART module base pointer. + */ +void UART_HAL_Init(UART_Type * base); + +/*! + * @brief Enables the UART transmitter. + * + * This function allows the user to enable the UART transmitter. + * + * @param base UART module base pointer. + */ +static inline void UART_HAL_EnableTransmitter(UART_Type * base) +{ + UART_BWR_C2_TE(base, 1U); +} + +/*! + * @brief Disables the UART transmitter. + * + * This function allows the user to disable the UART transmitter. + * + * @param base UART module base pointer. + */ +static inline void UART_HAL_DisableTransmitter(UART_Type * base) +{ + UART_BWR_C2_TE(base, 0U); +} + +/*! + * @brief Gets the UART transmitter enabled/disabled configuration setting. + * + * This function allows the user to get the setting of the UART transmitter. + * + * @param base UART module base pointer. + * @return The state of UART transmitter enable(true)/disable(false) setting. + */ +static inline bool UART_HAL_IsTransmitterEnabled(UART_Type * base) +{ + return (bool)UART_BRD_C2_TE(base); +} + +/*! + * @brief Enables the UART receiver. + * + * This function allows the user to enable the UART receiver. + * + * @param base UART module base pointer. + */ +static inline void UART_HAL_EnableReceiver(UART_Type * base) +{ + UART_BWR_C2_RE(base, 1U); +} + +/*! + * @brief Disables the UART receiver. + * + * This function allows the user to disable the UART receiver. + * + * @param base UART module base pointer. + */ +static inline void UART_HAL_DisableReceiver(UART_Type * base) +{ + UART_BWR_C2_RE(base, 0U); +} + +/*! + * @brief Gets the UART receiver enabled/disabled configuration setting. + * + * This function allows the user to get the setting of the UART receiver. + * + * @param base UART module base pointer. + * @return The state of UART receiver enable(true)/disable(false) setting. + */ +static inline bool UART_HAL_IsReceiverEnabled(UART_Type * base) +{ + return (bool)UART_BRD_C2_RE(base); +} + +/*! + * @brief Configures the UART baud rate. + * + * This function programs the UART baud rate to the desired value passed in by the user. The user + * must also pass in the module source clock so that the function can calculate the baud + * rate divisors to their appropriate values. + * In some UART bases it is required that the transmitter/receiver be disabled + * before calling this function. + * Generally this is applied to all UARTs to ensure safe operation. + * + * @param base UART module base pointer. + * @param sourceClockInHz UART source input clock in Hz. + * @param baudRate UART desired baud rate. + * @return An error code or kStatus_UART_Success + */ +uart_status_t UART_HAL_SetBaudRate(UART_Type * base, uint32_t sourceClockInHz, uint32_t baudRate); + +/*! + * @brief Sets the UART baud rate modulo divisor value. + * + * This function allows the user to program the baud rate divisor directly in situations + * where the divisor value is known. In this case, the user may not want to call the + * UART_HAL_SetBaudRate() function, as the divisor is already known. + * + * @param base UART module base pointer. + * @param baudRateDivisor The baud rate modulo division "SBR" value. + */ +void UART_HAL_SetBaudRateDivisor(UART_Type * base, uint16_t baudRateDivisor); + +#if FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT +/*! + * @brief Sets the UART baud rate fine adjust. (Note: Feature available on select + * UART bases used in conjunction with baud rate programming) + * + * This function, which programs the baud rate fine adjust, is used together with + * programming the baud rate modulo divisor in situations where these divisors value are known. + * In this case, the user may not want to call the UART_HAL_SetBaudRate() function, as the + * divisors are already known. + * + * @param base UART module base pointer. + * @param baudFineAdjust Value of 5-bit field used to add more timing resolution to average + * baud rate frequency is 1/32 increments. + */ +static inline void UART_HAL_SetBaudRateFineAdjust(UART_Type * base, uint8_t baudFineAdjust) +{ + assert(baudFineAdjust < 0x1F); + UART_BWR_C4_BRFA(base, baudFineAdjust); +} +#endif + +/*! + * @brief Configures the number of bits per character in the UART controller. + * + * This function allows the user to configure the number of bits per character according to the + * typedef uart_bit_count_per_char_t. + * + * @param base UART module base pointer. + * @param bitCountPerChar Number of bits per char (8, 9, or 10, depending on the UART base). + */ +static inline void UART_HAL_SetBitCountPerChar(UART_Type * base, + uart_bit_count_per_char_t bitCountPerChar) +{ + /* config 8- (M=0) or 9-bits (M=1) */ + UART_BWR_C1_M(base, bitCountPerChar); +} + +/*! + * @brief Configures the parity mode in the UART controller. + * + * This function allows the user to configure the parity mode of the UART controller to disable + * it or enable it for even parity or for odd parity. + * + * @param base UART module base pointer. + * @param parityMode Parity mode setting (enabled, disable, odd, even - see + * parity_mode_t struct). + */ +void UART_HAL_SetParityMode(UART_Type * base, uart_parity_mode_t parityMode); + +#if FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT +/*! + * @brief Configures the number of stop bits in the UART controller. + * + * This function allows the user to configure the number of stop bits in the UART controller + * to be one or two stop bits. + * + * @param base UART module base pointer. + * @param stopBitCount Number of stop bits setting (1 or 2 - see uart_stop_bit_count_t struct). + * @return An error code (an unsupported setting in some UARTs) or kStatus_UART_Success. + */ +static inline void UART_HAL_SetStopBitCount(UART_Type * base, uart_stop_bit_count_t stopBitCount) +{ + UART_BWR_BDH_SBNS(base, stopBitCount); +} +#endif + +/*! + * @brief Get UART tx/rx data register address. + * + * @param base UART module base pointer. + * @return UART tx/rx data register address. + */ +static inline uint32_t UART_HAL_GetDataRegAddr(UART_Type * base) +{ + return (uint32_t)(&UART_D_REG(base)); +} + +/*@}*/ + +/*! + * @name UART Interrupts and DMA + * @{ + */ + +/*! + * @brief Configures the UART module interrupts to enable/disable various interrupt sources. + * + * @param base UART module base pointer. + * @param interrupt UART interrupt configuration data. + * @param enable true: enable, false: disable. + */ +void UART_HAL_SetIntMode(UART_Type * base, uart_interrupt_t interrupt, bool enable); + +/*! + * @brief Returns whether the UART module interrupts is enabled/disabled. + * + * @param base UART module base pointer. + * @param interrupt UART interrupt configuration data. + * @return true: enable, false: disable. + */ +bool UART_HAL_GetIntMode(UART_Type * base, uart_interrupt_t interrupt); + +#if FSL_FEATURE_UART_HAS_DMA_SELECT +/*! + * @brief Enable or disable UART DMA request for Transmitter. + * + * This function allows the user to configure the receive data register full + * flag to generate a DMA request. + * + * @param base UART module base pointer. + * @param enable Transmit DMA request configuration setting (enable: true /disable: false). + */ +void UART_HAL_SetTxDmaCmd(UART_Type * base, bool enable); + +/*! + * @brief Gets the UART Transmit DMA request configuration setting. + * + * This function returns the configuration setting of the Transmit DMA request. + * + * @param base UART module base pointer. + * @return Transmit DMA request configuration setting (enable: true /disable: false). + */ +static inline bool UART_HAL_GetTxDmaCmd(UART_Type * base) +{ + return (!UART_BRD_C2_TCIE(base)) +#if FSL_FEATURE_UART_IS_SCI + && UART_BRD_C4_TDMAS(base) +#else + && UART_BRD_C5_TDMAS(base) +#endif + && UART_BRD_C2_TIE(base); +} + +/*! + * @brief Enable or disable UART DMA request for Receiver. + * + * This function allows the user to configure the receive data register full + * flag to generate a DMA request. + * + * @param base UART module base pointer. + * @param enable Receive DMA request configuration setting (enable: true/disable: false). + */ +void UART_HAL_SetRxDmaCmd(UART_Type * base, bool enable); + +/*! + * @brief Gets the UART Receive DMA request configuration setting. + * + * This function returns the configuration setting of the Receive DMA request. + * + * @param base UART module base pointer. + * @return Receive DMA request configuration setting (enable: true /disable: false). + */ +static inline bool UART_HAL_GetRxDmaCmd(UART_Type * base) +{ + return UART_BRD_C2_RIE(base) +#if FSL_FEATURE_UART_IS_SCI + && UART_BRD_C4_RDMAS(base); +#else + && UART_BRD_C5_RDMAS(base); +#endif +} + +#endif /* FSL_FEATURE_UART_HAS_DMA_SELECT */ + +/*@}*/ + +/*! + * @name UART Transfer Functions + * @{ + */ + +/*! + * @brief This function allows the user to send an 8-bit character from the UART data register. + * + * @param base UART module base pointer. + * @param data The data to send of size 8-bit. + */ +void UART_HAL_Putchar(UART_Type * base, uint8_t data); + +/*! + * @brief This function allows the user to send a 9-bit character from the UART data register. + * + * @param base UART module base pointer. + * @param data The data to send of size 9-bit. + */ +void UART_HAL_Putchar9(UART_Type * base, uint16_t data); + +/*! + * @brief This function gets a received 8-bit character from the UART data register. + * + * @param base UART module base pointer. + * @param readData The received data read from data register of size 8-bit. + */ +void UART_HAL_Getchar(UART_Type * base, uint8_t *readData); + +/*! + * @brief This function gets a received 9-bit character from the UART data register. + * + * @param base UART module base pointer. + * @param readData The received data read from data register of size 9-bit. + */ +void UART_HAL_Getchar9(UART_Type * base, uint16_t *readData); + +/*! + * @brief Send out multiple bytes of data using polling method. + * + * This function only supports 8-bit transaction. + * + * @param base UART module base pointer. + * @param txBuff The buffer pointer which saves the data to be sent. + * @param txSize Size of data to be sent in unit of byte. + */ +void UART_HAL_SendDataPolling(UART_Type * base, const uint8_t *txBuff, uint32_t txSize); + +/*! + * @brief Receive multiple bytes of data using polling method. + * + * This function only supports 8-bit transaction. + * + * @param base UART module base pointer. + * @param rxBuff The buffer pointer which saves the data to be received. + * @param rxSize Size of data need to be received in unit of byte. + * @return Whether the transaction is success or rx overrun. + */ +uart_status_t UART_HAL_ReceiveDataPolling(UART_Type * base, uint8_t *rxBuff, uint32_t rxSize); + +#if FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS +/*! + * @brief Configures the UART bit 10 (if enabled) or bit 9 (if disabled) as the parity bit in the + * serial transmission. + * + * This function configures bit 10 or bit 9 to be the parity bit. To configure bit 10 as the parity + * bit, the function sets UARTx_C4[M10]; it also sets UARTx_C1[M] and UARTx_C1[PE] as required. + * + * @param base UART module base pointer. + * @param enable The setting to enable (true), which configures bit 10 as the parity bit or to + * disable (false), which configures bit 9 as the parity bit in the serial + * transmission. + */ +static inline void UART_HAL_SetBit10AsParityBit(UART_Type * base, bool enable) +{ + /* to enable the parity bit as the tenth data bit, along with enabling UARTx_C4[M10] + * need to also enable parity and set UARTx_C1[M] bit + * assumed that the user has already set the appropriate bits */ + UART_BWR_C4_M10(base, enable); +} + +/*! + * @brief Gets the configuration of the UART bit 10 (if enabled) or bit 9 (if disabled) as the + * parity bit in the serial transmission. + * + * This function returns true if bit 10 is configured as the parity bit, otherwise it returns + * false if bit 9 is configured as the parity bit. + * + * @param base UART module base pointer. + * @return The configuration setting of bit 10 (true), or bit 9 (false) as the + * parity bit in the serial transmission. + */ +static inline bool UART_HAL_IsBit10SetAsParityBit(UART_Type * base) +{ + return UART_BRD_C4_M10(base); +} + +/*! + * @brief Determines whether the UART received data word was received with noise. + * + * This function returns true if the received data word was received with noise. Otherwise, + * it returns false indicating no noise was detected. + * + * @param base UART module base pointer. + * @return The status of the NOISY bit in the UART extended data register. + */ +static inline bool UART_HAL_IsCurrentDataWithNoise(UART_Type * base) +{ + return UART_BRD_ED_NOISY(base); +} + +/*! + * @brief Determines whether the UART received data word was received with a parity error. + * + * This function returns true if the received data word was received with a parity error. + * Otherwise, it returns false indicating no parity error was detected. + * + * @param base UART module base pointer. + * @return The status of the PARITYE (parity error) bit in the UART extended data register. + */ +static inline bool UART_HAL_IsCurrentDataWithParityError(UART_Type * base) +{ + return UART_BRD_ED_PARITYE(base); +} + +#endif /* FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS*/ + +/*@}*/ + +/*! + * @name UART Status Flags + * @{ + */ + +/*! + * @brief Gets all UART status flag states. + * + * @param base UART module base pointer. + * @param statusFlag Status flag name. + * @return Whether the current status flag is set(true) or not(false). + */ +bool UART_HAL_GetStatusFlag(UART_Type * base, uart_status_flag_t statusFlag); + +/*! + * @brief Clears an individual and specific UART status flag. + * + * This function allows the user to clear an individual and specific UART status flag. Refer to + * structure definition uart_status_flag_t for list of status bits. + * + * @param base UART module base pointer. + * @param statusFlag The desired UART status flag to clear. + * @return An error code or kStatus_UART_Success. + */ +uart_status_t UART_HAL_ClearStatusFlag(UART_Type * base, uart_status_flag_t statusFlag); + +/*@}*/ + +/*! + * @name UART FIFO Configurations + * @{ + */ + +#if FSL_FEATURE_UART_HAS_FIFO +/*! + * @brief Enables or disable the UART transmit FIFO. + * + * This function allows the user to enable or disable the UART transmit FIFO. + * It is required that the transmitter/receiver be disabled before calling this function + * when the FIFO is empty. + * Additionally, TXFLUSH and RXFLUSH commands should be issued after calling this function. + * + * @param base UART module base pointer. + * @param enable Enable or disable Tx FIFO. + * @return Error code if it is detected that the transmitter or receiver is enabled or + * kStatus_UART_Success. + */ +uart_status_t UART_HAL_SetTxFifoCmd(UART_Type * base, bool enable); + +/*! + * @brief Enables or disable the UART receive FIFO. + * + * This function allows the user to enable or disable the UART receive FIFO. + * It is required that the transmitter/receiver be disabled before calling this function + * when the FIFO is empty. + * Additionally, TXFLUSH and RXFLUSH commands should be issued after calling this function. + * + * @param base UART module base pointer. + * @param enable Enable or disable Rx FIFO. + * @return Error code if it is detected that the transmitter or receiver is enabled or + * kStatus_UART_Success. + */ +uart_status_t UART_HAL_SetRxFifoCmd(UART_Type * base, bool enable); + +/*! + * @brief Gets the size of the UART transmit FIFO. + * + * This function returns the size (number of entries) supported in the UART transmit FIFO for + * a particular module base. + * + * @param base UART module base pointer. + * @return The UART transmit FIFO size as follows: + * 0x0: 1 data word; 0x1: 4 data words; 0x2: 8 data words; 0x3: 16 data words + * 0x4: 32 data words; 0x5: 64 data words; 0x6: 128 data words; 0x7: reserved + */ +static inline uint8_t UART_HAL_GetTxFifoSize(UART_Type * base) +{ + return UART_BRD_PFIFO_TXFIFOSIZE(base); +} + +/*! + * @brief Gets the size of the UART receive FIFO. + * + * This function returns the size (number of entries) supported in the UART receive FIFO for + * a particular module base. + * + * @param base UART module base pointer. + * @return The receive FIFO size as follows: + * 0x0: 1 data word; 0x1: 4 data words; 0x2: 8 data words; 0x3: 16 data words + * 0x4: 32 data words; 0x5: 64 data words; 0x6: 128 data words; 0x7: reserved + */ +static inline uint8_t UART_HAL_GetRxFifoSize(UART_Type * base) +{ + return UART_BRD_PFIFO_RXFIFOSIZE(base); +} + +/*! + * @brief Flushes the UART transmit FIFO. + * + * This function allows the user to flush the UART transmit FIFO for a particular module base. + * Flushing the FIFO may result in data loss. + * It is recommended that the transmitter be disabled before calling this function. + * + * @param base UART module base pointer. + * @return Error code if it is detected that the transmitter or receiver is enabled or + * kStatus_UART_Success. + */ +uart_status_t UART_HAL_FlushTxFifo(UART_Type * base); + +/*! + * @brief Flushes the UART receive FIFO. + * + * This function allows the user to flush the UART receive FIFO for a particular module base. + * Flushing the FIFO may result in data loss. + * It is recommended that the receiver be disabled before calling this function. + * + * @param base UART module base pointer. + * @return Error code if it is detected that the transmitter or receiver is enabled or + * kStatus_UART_Success. + */ +uart_status_t UART_HAL_FlushRxFifo(UART_Type * base); + +/*! + * @brief Gets the UART transmit FIFO empty status state. + * + * The function returns the state of the transmit FIFO empty status state, but does not take into + * account data in the shift register. + * + * @param base UART module base pointer. + * @return The UART transmit FIFO empty status: true=empty; false=not-empty. + */ +static inline bool UART_HAL_IsTxFifoEmpty(UART_Type * base) +{ + return UART_BRD_SFIFO_TXEMPT(base); +} + +/*! + * @brief Gets the UART receive FIFO empty status state. + * + * The function returns the state of the receive FIFO empty status state, but does not take into + * account data in the shift register. + * + * @param base UART module base pointer. + * @return The UART receive FIFO empty status: true=empty; false=not-empty. + */ +static inline bool UART_HAL_IsRxFifoEmpty(UART_Type * base) +{ + return UART_BRD_SFIFO_RXEMPT(base); +} + +/*! + * @brief Sets the UART transmit FIFO watermark value. + * + * Programming the transmit watermark should be done when UART the transmitter is disabled + * and the value must be set less than the size obtained from UART_HAL_GetTxFifoSize. + * + * @param base UART module base pointer. + * @param watermark The UART transmit watermark value to be programmed. + * @return Error code if transmitter is enabled or kStatus_UART_Success. + */ +uart_status_t UART_HAL_SetTxFifoWatermark(UART_Type * base, uint8_t watermark); + +/*! + * @brief Gets the UART transmit FIFO watermark value. + * + * @param base UART module base pointer. + * @return The value currently programmed for the UART transmit watermark. + */ +static inline uint8_t UART_HAL_GetTxFifoWatermark(UART_Type * base) +{ + return UART_RD_TWFIFO(base); +} + +/*! + * @brief Gets the UART transmit FIFO data word count (number of words in the transmit FIFO). + * + * The function UART_HAL_GetTxDatawordCountInFifo excludes any data that may + * be in the UART transmit shift register + * + * @param base UART module base pointer. + * @return The number of data words currently in the UART transmit FIFO. + */ +static inline uint8_t UART_HAL_GetTxDatawordCountInFifo(UART_Type * base) +{ + return UART_RD_TCFIFO(base); +} + +/*! + * @brief Sets the UART receive FIFO watermark value. + * + * Programming the receive watermark should be done when the receiver is disabled + * and the value must be set less than the size obtained from UART_HAL_GetRxFifoSize and + * greater than zero. + * + * @param base UART module base pointer. + * @param watermark The UART receive watermark value to be programmed. + * @return Error code if receiver is enabled or kStatus_UART_Success. + */ +uart_status_t UART_HAL_SetRxFifoWatermark(UART_Type * base, uint8_t watermark); + +/*! + * @brief Gets the UART receive FIFO data word count (number of words in the receive FIFO). + * + * The function UART_HAL_GetRxDatawordCountInFifo excludes any data that may be + * in the receive shift register. + * + * @param base UART module base pointer. + * @return The number of data words currently in the UART receive FIFO. + */ +static inline uint8_t UART_HAL_GetRxDatawordCountInFifo(UART_Type * base) +{ + return UART_RD_RCFIFO(base); +} + +/*! + * @brief Gets the UART receive FIFO watermark value. + * + * @param base UART module base pointer. + * @return The value currently programmed for the UART receive watermark. + */ +static inline uint8_t UART_HAL_GetRxFifoWatermark(UART_Type * base) +{ + return UART_RD_RWFIFO(base); +} + +#endif /* FSL_FEATURE_UART_HAS_FIFO*/ + +/*! + * @name UART Special Feature Configurations + * @{ + */ + +#if FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION +/*! + * @brief Configures the UART to either operate or cease to operate in WAIT mode. + * + * The function configures the UART to either operate or cease to operate when WAIT mode is + * entered. + * + * @param base UART module base pointer. + * @param mode The UART WAIT mode operation - operates or ceases to operate in WAIT mode. + */ +static inline void UART_HAL_SetWaitModeOperation(UART_Type * base, uart_operation_config_t mode) +{ + /*In CPU wait mode: 0 - uart is enabled; 1 - uart is disabled */ + UART_BWR_C1_UARTSWAI(base, mode); +} + +/*! + * @brief Determines if the UART operates or ceases to operate in WAIT mode. + * + * This function returns kUartOperates if the UART has been configured to operate in WAIT mode. + * Else it returns KUartStops if the UART has been configured to cease-to-operate in WAIT mode. + * + * @param base UART module base pointer. + * @return The UART WAIT mode operation configuration, returns either kUartOperates or KUartStops. + */ +static inline uart_operation_config_t UART_HAL_GetWaitModeOperation(UART_Type * base) +{ + /*In CPU wait mode: 0 - uart is enabled; 1 - uart is disabled */ + return (uart_operation_config_t)UART_BRD_C1_UARTSWAI(base); +} +#endif /* FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION */ + +/*! + * @brief Configures the UART loopback operation. + * + * This function enables or disables the UART loopback operation. + * + * @param base UART module base pointer. + * @param enable The UART loopback mode configuration, either disabled (false) or enabled (true). + */ +static inline void UART_HAL_SetLoopCmd(UART_Type * base, bool enable) +{ + UART_BWR_C1_LOOPS(base, enable); +} + +/*! + * @brief Configures the UART single-wire operation. + * + * This function enables or disables the UART single-wire operation. + * In some UART bases it is required that the transmitter/receiver be disabled + * before calling this function. + * This may be applied to all UARTs to ensure safe operation. + * + * @param base UART module base pointer. + * @param source The UART single-wire mode configuration. + */ +static inline void UART_HAL_SetReceiverSource(UART_Type * base, uart_receiver_source_t source) +{ + UART_BWR_C1_RSRC(base, source); +} + +/*! + * @brief Configures the UART transmit direction while in single-wire mode. + * + * This function configures the transmitter direction when the UART is configured for single-wire + * operation. + * + * @param base UART module base pointer. + * @param direction The UART single-wire mode transmit direction configuration of type + * uart_singlewire_txdir_t (either kUartSinglewireTxdirIn or + * kUartSinglewireTxdirOut. + */ +static inline void UART_HAL_SetTransmitterDir(UART_Type * base, uart_singlewire_txdir_t direction) +{ + /* configure UART transmit direction (input or output) when in single-wire mode + * it is assumed UART is in single-wire mode. */ + UART_BWR_C3_TXDIR(base, direction); +} + +/*! + * @brief Places the UART receiver in standby mode. + * + * This function, when called, places the UART receiver into standby mode. + * In some UART bases, there are conditions that must be met before placing Rx in standby mode. + * Before placing UART in standby, determine if receiver is set to + * wake on idle, and if receiver is already in idle state. + * NOTE: RWU should only be set with C1[WAKE] = 0 (wakeup on idle) if the channel is currently + * not idle. + * This can be determined by the S2[RAF] flag. If set to wake up FROM an IDLE event and the channel + * is already idle, it is possible that the UART will discard data because data must be received + * (or a LIN break detect) after an IDLE is detected before IDLE is allowed to be reasserted. + * + * @param base UART module base pointer. + * @return Error code or kStatus_UART_Success. + */ +uart_status_t UART_HAL_PutReceiverInStandbyMode(UART_Type * base); + +/*! + * @brief Places the UART receiver in normal mode (disable standby mode operation). + * + * This function, when called, places the UART receiver into normal mode and out of + * standby mode. + * + * @param base UART module base pointer. + */ +static inline void UART_HAL_PutReceiverInNormalMode(UART_Type * base) +{ + UART_CLR_C2(base, UART_C2_RWU_MASK); +} + +/*! + * @brief Determines if the UART receiver is currently in standby mode. + * + * This function determines the state of the UART receiver. If it returns true, this means + * that the UART receiver is in standby mode; if it returns false, the UART receiver + * is in normal mode. + * + * @param base UART module base pointer. + * @return The UART receiver is in normal mode (false) or standby mode (true). + */ +static inline bool UART_HAL_IsReceiverInStandby(UART_Type * base) +{ + return UART_BRD_C2_RWU(base); +} + +/*! + * @brief Selects the UART receiver wakeup method (idle-line or address-mark) from standby mode. + * + * This function configures the wakeup method of the UART receiver from standby mode. The options + * are idle-line wake or address-mark wake. + * + * @param base UART module base pointer. + * @param method The UART receiver wakeup method options: kUartIdleLineWake - Idle-line wake or + * kUartAddrMarkWake - address-mark wake. + */ +static inline void UART_HAL_SetReceiverWakeupMethod(UART_Type * base, uart_wakeup_method_t method) +{ + UART_BWR_C1_WAKE(base, method); +} + +/*! + * @brief Gets the UART receiver wakeup method (idle-line or address-mark) from standby mode. + * + * This function returns how the UART receiver is configured to wake from standby mode. The + * wake method options that can be returned are kUartIdleLineWake or kUartAddrMarkWake. + * + * @param base UART module base pointer. + * @return The UART receiver wakeup from standby method, false: kUartIdleLineWake (idle-line wake) + * or true: kUartAddrMarkWake (address-mark wake). + */ +static inline uart_wakeup_method_t UART_HAL_GetReceiverWakeupMethod(UART_Type * base) +{ + return (uart_wakeup_method_t)UART_BRD_C1_WAKE(base); +} + +/*! + * @brief Configures the operation options of the UART idle line detect. + * + * This function allows the user to configure the UART idle-line detect operation. There are two + * separate operations for the user to configure, the idle line bit-count start and the receive + * wake up affect on IDLE status bit. The user will pass in a structure of type + * uart_idle_line_config_t. + * + * @param base UART module base pointer. + * @param idleLine Idle bit count start: 0 - after start bit (default), 1 - after stop bit + * @param rxWakeIdleDetect Receiver Wake Up Idle Detect. IDLE status bit operation during receive + * standby. Controls whether idle character that wakes up receiver will also set IDLE status + * bit. 0 - IDLE status bit doesn't get set (default), 1 - IDLE status bit gets set + */ +void UART_HAL_ConfigIdleLineDetect(UART_Type * base, uint8_t idleLine, uint8_t rxWakeIdleDetect); + +/*! + * @brief Configures the UART break character transmit length. + * + * This function allows the user to configure the UART break character transmit length. Refer to + * the typedef uart_break_char_length_t for setting options. + * In some UART bases it is required that the transmitter be disabled before calling + * this function. This may be applied to all UARTs to ensure safe operation. + * + * @param base UART module base pointer. + * @param length The UART break character length setting of type uart_break_char_length_t, either a + * minimum 10-bit times or a minimum 13-bit times. + */ +static inline void UART_HAL_SetBreakCharTransmitLength(UART_Type * base, + uart_break_char_length_t length) +{ + /* Configure BRK13 - Break Character transmit length configuration + * UART break character length setting: + * 0 - minimum 10-bit times (default), + * 1 - minimum 13-bit times */ + UART_BWR_S2_BRK13(base, length); +} + +#if FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT +/*! + * @brief Configures the UART break character detect length. + * + * This function allows the user to configure the UART break character detect length. Refer to + * the typedef uart_break_char_length_t for setting options. + * + * @param base UART module base pointer. + * @param length The UART break character length setting of type uart_break_char_length_t, either a + * minimum 10-bit times or a minimum 13-bit times. + */ +static inline void UART_HAL_SetBreakCharDetectLength(UART_Type * base, uart_break_char_length_t length) +{ + /* Configure LBKDE - Break Character detect length configuration + * UART break character length setting: + * 0 - minimum 10-bit times (default), + * 1 - minimum 13-bit times */ + UART_BWR_S2_LBKDE(base, length); +} +#endif /* FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT */ + +/*! + * @brief Configures the UART transmit send break character operation. + * + * This function allows the user to queue a UART break character to send. If true is passed into + * the function, then a break character is queued for transmission. A break character will + * continuously be queued until this function is called again when a false is passed into this + * function. + * + * @param base UART module base pointer. + * @param enable If false, the UART normal/queue break character setting is disabled, which + * configures the UART for normal transmitter operation. If true, a break + * character is queued for transmission. + */ +static inline void UART_HAL_SetBreakCharCmd(UART_Type * base, bool enable) +{ + UART_BWR_C2_SBK(base, enable); +} + +/*! + * @brief Configures the UART match address mode control operation. (Note: Feature available on + * select UART bases) + * + * The function allows the user to configure the UART match address control operation. The user + * has the option to enable the match address mode and to program the match address value. There + * are two match address modes, each with its own enable and programmable match address value. + * + * @param base UART module base pointer. + * @param matchAddrMode1 If true, this enables match address mode 1 (MAEN1), where false disables. + * @param matchAddrMode2 If true, this enables match address mode 2 (MAEN2), where false disables. + * @param matchAddrValue1 The match address value to program for match address mode 1. + * @param matchAddrValue2 The match address value to program for match address mode 2. + */ +void UART_HAL_SetMatchAddress(UART_Type * base, bool matchAddrMode1, bool matchAddrMode2, + uint8_t matchAddrValue1, uint8_t matchAddrValue2); + +#if FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT +/*! + * @brief Configures the UART to send data MSB first + * (Note: Feature available on select UART bases) + * + * The function allows the user to configure the UART to send data MSB first or LSB first. + * In some UART bases it is required that the transmitter/receiver be disabled + * before calling this function. + * This may be applied to all UARTs to ensure safe operation. + * + * @param base UART module base pointer. + * @param enable This configures send MSB first mode configuration. If true, the data is sent MSB + * first; if false, it is sent LSB first. + */ +static inline void UART_HAL_SetSendMsbFirstCmd(UART_Type * base, bool enable) +{ + UART_BWR_S2_MSBF(base, enable); +} +#endif + +#if FSL_FEATURE_UART_HAS_MODEM_SUPPORT +/*! + * @brief Enables the UART receiver request-to-send functionality. + * + * This function allows the user to enable the UART receiver request-to-send (RTS) functionality. + * By enabling, it allows the RTS output to control the CTS input of the transmitting device to + * prevent receiver overrun. RTS is deasserted if the number of characters in the receiver data + * register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the + * number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. + * Do not set both RXRTSE and TXRTSE. + * + * @param base UART module base pointer. + * @param enable Enable or disable receiver rts. + */ +static inline void UART_HAL_SetReceiverRtsCmd(UART_Type * base, bool enable) +{ + UART_BWR_MODEM_RXRTSE(base, enable); +} + +/*! + * @brief Enables the UART transmitter request-to-send functionality. + * + * This function allows the user to enable the UART transmitter request-to-send (RTS) functionality. + * When enabled, it allows the UART to control the RTS assertion before and after a transmission + * such that when a character is placed into an empty transmitter data buffer, RTS + * asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all + * characters in the transmitter data buffer and shift register are completely sent, including + * the last stop bit. + * + * @param base UART module base pointer. + * @param enable Enable or disable transmitter RTS. + */ +static inline void UART_HAL_SetTransmitterRtsCmd(UART_Type * base, bool enable) +{ + UART_BWR_MODEM_TXRTSE(base, enable); +} + +/*! + * @brief Configures the UART transmitter RTS polarity. + * + * This function allows the user configure the transmitter RTS polarity to be either active low + * or active high. + * + * @param base UART module base pointer. + * @param polarity The UART transmitter RTS polarity setting (false - active low, + * true - active high). + */ +static inline void UART_HAL_SetTransmitterRtsPolarityMode(UART_Type * base, bool polarity) +{ + UART_BWR_MODEM_TXRTSPOL(base, polarity); +} + +/*! + * @brief Enables the UART transmitter clear-to-send functionality. + * + * This function allows the user to enable the UART transmitter clear-to-send (CTS) functionality. + * When enabled, the transmitter checks the state of CTS each time it is ready to send a character. + * If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in + * the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a + * character is being sent do not affect its transmission. + * + * @param base UART module base pointer. + * @param enable Enable or disable transmitter CTS. + */ +static inline void UART_HAL_SetTransmitterCtsCmd(UART_Type * base, bool enable) +{ + UART_BWR_MODEM_TXCTSE(base, enable); +} + +#endif /* FSL_FEATURE_UART_HAS_MODEM_SUPPORT*/ + +#if FSL_FEATURE_UART_HAS_IR_SUPPORT +/*! + * @brief Configures the UART infrared operation. + * + * The function allows the user to enable or disable the UART infrared (IR) operation + * and to configure the IR pulse width. + * + * @param base UART module base pointer. + * @param enable Enable (true) or disable (false) the infrared operation. + * @param pulseWidth The UART transmit narrow pulse width setting of type uart_ir_tx_pulsewidth_t. + */ +void UART_HAL_SetInfraredOperation(UART_Type * base, bool enable, + uart_ir_tx_pulsewidth_t pulseWidth); +#endif /* FSL_FEATURE_UART_HAS_IR_SUPPORT*/ + +/*@}*/ + +/*! + * @name UART ISO7816 Configurations + * @{ + */ + +#if FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT +/*! + * @brief Enables UART ISO7816 feature. + * + * This function enables the ISO7816 feature in the UART for + * a particular module base. + * + * @param base UART module base pointer. + */ +static inline void UART_HAL_EnableISO7816(UART_Type * base) +{ + UART_BWR_C7816_ISO_7816E(base, 1U); +} + +/*! + * @brief Disables UART ISO7816 feature. + * + * This function disables the ISO7816 feature in the UART for + * a particular module base. + * + * @param base UART module base pointer. + */ +static inline void UART_HAL_DisableISO7816(UART_Type * base) +{ + UART_BWR_C7816_ISO_7816E(base, 0U); +} + +/*! + * @brief Gets the UART module ISO7816 feature enabled/disabled configuration setting. + * + * This function allows the user to get the setting of the UART ISO7816 feature settings. + * + * @param base UART module base pointer. + * @return The state of UART module ISO7816 feature enable(true)/disable(false) setting. + */ +static inline bool UART_HAL_IsISO7816Enabled(UART_Type * base) +{ + return (bool)UART_BRD_C7816_ISO_7816E(base); +} + +/*! + * @brief Enables/Disables UART ISO7816 module ONACK generation feature. + * + * This function enables/disables the ONACK generation in ISO7816 module in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @param onack = kUartIso7816OnackEnable to enable ONACK generation, + * = kUartIso7816Onackdisable to disable ONACK generation + */ +static inline void UART_HAL_ConfigureNackOnOverflow(UART_Type * base, uart_iso7816_onack_config_t onack) +{ + UART_BWR_C7816_ONACK(base, onack); +} + +/*! + * @brief Gets the UART module ISO7816 module ONACK generation feature enabled/disabled configuration + * setting. + * + * This function allows the user to get the setting of the UART ISO7816 ONACK generaton feature settings. + * + * @param base UART module base pointer. + * @return The state of UART module ISO7816 ONACK feature enable(true)/disable(false) setting. + */ +static inline bool UART_HAL_Is6NackOnOverflowEnabled(UART_Type * base) +{ + return (bool)UART_BRD_C7816_ONACK(base); +} + +/*! + * @brief Enables/Disables UART ISO7816 module ANACK generation feature. + * + * This function enables the ANACK generation in ISO7816 module in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @param anack = kUartIso7816AnackEnable to enable ANACK generation, + * = kUartIso7816AnackDisable to disable ANACK generation + */ +static inline void UART_HAL_ConfigureNackOnError(UART_Type * base, uart_iso7816_anack_config_t anack) +{ + UART_BWR_C7816_ANACK(base, anack); +} + +/*! + * @brief Gets the UART module ISO7816 module ANACK generation feature enabled/disabled configuration + * setting. + * + * This function allows the user to get the setting of the UART ISO7816 ONACK generaton feature settings. + * + * @param base UART module base pointer. + * @return The state of UART module ISO7816 ANACK feature enable(true)/disable(false) setting. + */ +static inline bool UART_HAL_Is6NackOnOnErrorEnabled(UART_Type * base) +{ + return (bool)UART_BRD_C7816_ANACK(base); +} + +/*! + * @brief Enables/Disables UART ISO7816 module Initail character detection feature. + * + * This function enables/disables the Initail character detection in ISO7816 module in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @param initd = kUartIso7816InitdEnable, to enable initial character detection, + * = kUartIso7816InitdDisable, to disable initial character detection, + */ +static inline void UART_HAL_ConfigureInitialCharacterDetection(UART_Type * base, uart_iso7816_initd_config_t initd) +{ + UART_BWR_C7816_INIT(base, initd); +} + +/*! + * @brief Gets the UART module ISO7816 module Initail character detection feature enabled/disabled + * configuration setting. + * + * This function allows the user to get the setting of the UART ISO7816 Initail character detection + * feature settings. + * + * @param base UART module base pointer. + * @return The state of UART module ISO7816 Initail character detection feature enable(true)/disable(false) + * setting. + * + */ +static inline bool UART_HAL_IsInitialCharacterDetectionEnabled(UART_Type * base) +{ + return (bool)UART_BRD_C7816_INIT(base); +} + +/*! + * @brief Sets treansfer protocol type for UART ISO7816 module. + * + * This function sets the transfer protocol type in ISO7816 module in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @param transferType Transfer protocol type = kUartIso7816TransfertType0 or, kUartIso7816TransfertType1. + */ +static inline void UART_HAL_SetTransferProtocolType(UART_Type * base, uart_iso7816_transfer_protocoltype_t transferType) +{ + UART_BWR_C7816_TTYPE(base, transferType); +} + +/*! + * @brief Gets treansfer protocol type for UART ISO7816 module. + * + * This function gets the transfer protocol type in ISO7816 module in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @return The current settings of transfer Transfer protocol type. + */ +static inline uart_iso7816_transfer_protocoltype_t UART_HAL_GetTransferProtocolType(UART_Type * base) +{ + return (uart_iso7816_transfer_protocoltype_t)UART_BRD_C7816_TTYPE(base); +} + +/*! + * @brief Configures the UART module ISO7816 feature specific interrupts to + * enable/disable various interrupt sources. + * + * @param base UART module base pointer. + * @param interrupt UART ISO7816 feature specific interrupt configuration data. + * @param enable true: enable, false: disable. + */ +void UART_HAL_SetISO7816IntMode(UART_Type * base, uart_iso7816_interrupt_t interrupt, bool enable); + +/*! + * @brief Returns whether the UART module ISO7816 feature specific interrupts + * is enabled/disabled. + * + * @param base UART module base pointer. + * @param interrupt UART ISO7816 feature specific interrupt configuration data. + * @return true: enable, false: disable. + */ +bool UART_HAL_GetISO7816IntMode(UART_Type * base, uart_iso7816_interrupt_t interrupt); + +/*! + * @brief Clears the UART module ISO7816 feature specific interrupts status bits + * + * @param base UART module base pointer. + * @param interrupt UART ISO7816 feature specific interrupt configuration data. + */ +void UART_HAL_ClearISO7816InterruptStatus(UART_Type * base, uart_iso7816_interrupt_t interrupt); + +/*! + * @brief Returns whether the UART module ISO7816 feature specific interrupt status + * has been set or not. + * + * @param base UART module base pointer. + * @param interrupt UART ISO7816 feature specific interrupt configuration data. + * @return true, false. + */ +bool UART_HAL_GetISO7816InterruptStatus(UART_Type * base, uart_iso7816_interrupt_t interrupt); + +/*! + * @brief Sets the basic Elementaty Time Unit of UART instance in ISO7816 mode. + * + * @param base UART module base pointer. + * @param sourceClockInHz Module source clock in Hz. + * @param sCClock Smart card clock in Hz. + * @param Fi Smart card frequency multiplier. + * @param Di Smart card baud rate divider. + * @returns kStatus_UART_BaudRateCalculationError or kStatus_UART_Success + */ +uart_status_t UART_HAL_SetISO7816Etu(UART_Type * base, uint32_t sourceClockInHz, uint32_t sCClock, uint16_t Fi, uint8_t Di); + +/*! + * @brief Resets UART ISO7816 specific Wait Timer + * + * @param base UART module base pointer. + */ +void UART_HAL_ResetISO7816WaitTimer(UART_Type * base); + +/*! + * @brief Resets UART ISO7816 specific Character Wait Timer + * + * @param base UART module base pointer. + */ +void UART_HAL_ResetISO7816CharacterWaitTimer(UART_Type * base); + +/*! + * @brief Resets UART ISO7816 specific Block Wait Timer + * + * @param base UART module base pointer. + */ +void UART_HAL_ResetISO7816BlockWaitTimer(UART_Type * base); + +#if FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT +/*! + * @brief Sets a value to Wait Time Multiplier. + * + * This function sets a value to the Wait Timer Multiplier in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @param wtx value to set to UART module Wait Time Multiplier. + */ +static inline void UART_HAL_SetWaitTimeMultipllier(UART_Type * base, uint8_t wtx) +{ + UART_WR_WP7816(base, wtx); +} + +/*! + * @brief Gets the current value of Wait Time Multiplier. + * + * This function gets the current value of the Wait Timer Multiplier in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @return current value of the UART module Wait Time Multiplier. + */ +static inline uint8_t UART_HAL_GetWaitTimeMultipllier(UART_Type * base) +{ + return UART_RD_WP7816(base); +} + +/*! + * @brief Resets UART ISO7816 specific Block Wait Timer + * + * @param base UART module base pointer. + * @param mWtx Wait time multiplier. + */ +void UART_HAL_ResetWaitTimeMultipllier(UART_Type * base, uint8_t mWtx); +#endif + +/*! + * @brief Sets a value to Guard Band Integer. + * + * This function sets a value to the Guard Band Integer in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @param gtn value to set to UART module Guard Band Integer. + */ +static inline void UART_HAL_SetGuardBandInteger(UART_Type * base, uint8_t gtn) +{ + UART_WR_WN7816(base, gtn); +} + +/*! + * @brief Gets the current value of Guard Band Integer. + * + * This function gets the current value of the Guard Band Integer in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @return + */ +static inline uint8_t UART_HAL_GetGuardBandInteger(UART_Type * base) +{ + return UART_RD_WN7816(base); +} + +/*! + * @brief Sets a value to FD Multiplier. + * + * This function sets a value to the FD Multiplier in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @param gtfd value to set to UART module Guard Band Integer. + */ +static inline void UART_HAL_SetFDMultiplier(UART_Type * base, uint8_t gtfd) +{ + UART_WR_WF7816(base, gtfd); +} + +/*! + * @brief Gets the current value of FD Multiplier. + * + * This function gets the current value of the FD Multiplier in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @return current value of the UART module FD Multiplier. + */ +static inline uint8_t UART_HAL_GetFDMultiplier(UART_Type * base) +{ + return UART_RD_WF7816(base); +} + +/*! + * @brief Sets a value to Transmit NACK Threshold. + * + * This function sets a value to the Transmit NACK Threshold in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @param txThreshold value to set to UART module Transmit NACK Threshold. + */ +static inline void UART_HAL_SetTxNACKThreshold(UART_Type * base, uint8_t txThreshold) +{ + UART_BWR_ET7816_TXTHRESHOLD(base, txThreshold); +} + +/*! + * @brief Gets the current value of Transmit NACK Threshold. + * + * This function gets the current value of the Transmit NACK Threshold in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @return current value of the UART module Transmit NACK Threshold. + */ +static inline uint8_t UART_HAL_GetTxNACKThreshold(UART_Type * base) +{ + return UART_BRD_ET7816_TXTHRESHOLD(base); +} + +/*! + * @brief Sets a value to Receive NACK Threshold. + * + * This function sets a value to the Receive NACK Threshold in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @param rxThreshold value to set to UART module Receive NACK Threshold. + */ +static inline void UART_HAL_SetRxNACKThreshold(UART_Type * base, uint8_t rxThreshold) +{ + UART_BWR_ET7816_RXTHRESHOLD(base, rxThreshold); +} + +/*! + * @brief Gets the current value of Receive NACK Threshold. + * + * This function gets the current value of the Receive NACK Threshold in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @return current value of the UART module Receive NACK Threshold. + */ +static inline uint8_t UART_HAL_GetRxNACKThreshold(UART_Type * base) +{ + return UART_BRD_ET7816_RXTHRESHOLD(base); +} + +/*! + * @brief Sets a value to Transmit Length in T=1 transfer protocol. + * + * This function sets a value to the Transmit Length field in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @param tLen value to set to UART module Transmit Length field. + */ +static inline void UART_HAL_SetTLen(UART_Type * base, uint8_t tLen) +{ + UART_WR_TL7816(base, tLen); +} + +/*! + * @brief Gets the current value of Transmit Length field . + * + * This function gets the current value of the Transmit Length field in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @return current value of the UART module Transmit Length field. + */ +static inline uint8_t UART_HAL_GetTLen(UART_Type * base) +{ + return UART_RD_TL7816(base); +} + +#if FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT +/*! + * @brief Sets a value to ATR Duration Timer. + * + * This function sets a value to the ATR Duration Timer in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @param atrDuration value to set to UART module ATR Duration Timer. + */ +static inline void UART_HAL_SetAtrDurationTimer(UART_Type * base, uint16_t atrDuration) +{ + UART_WR_AP7816A_T0(base, (uint8_t)(atrDuration >> 8)); + UART_WR_AP7816B_T0(base, (uint8_t)atrDuration); +} + +/*! + * @brief Gets the current value of ATR Duration Timer. + * + * This function gets the current value of the ATR Duration Timer in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @return current value of the UART module ATR Duration Timer. + */ +static inline uint16_t UART_HAL_GetAtrDurationTimer(UART_Type * base) +{ + return (uint16_t)((uint16_t)((uint16_t)UART_RD_AP7816A_T0(base) << 8) | UART_RD_AP7816B_T0(base)); +} +#endif + +#if FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT +/*! + * @brief Sets a value to Work Wait Time Integer. + * + * This function sets a value to the Work Wait Time Integer in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @param wi value to set to UART module Work Wait Time Integer. + */ +static inline void UART_HAL_SetWorkWaitTimeInteger(UART_Type * base, uint16_t wi) +{ + UART_WR_WP7816A_T0(base, (uint8_t)(wi >> 8)); + UART_WR_WP7816B_T0(base, (uint8_t)wi); +} +#else +/*! + * @brief Sets a value to Work Wait Time Integer. + * + * This function sets a value to the Work Wait Time Integer in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @param wi value to set to UART module Work Wait Time Integer. + */ +static inline void UART_HAL_SetWorkWaitTimeInteger(UART_Type * base, uint8_t wi) +{ + UART_WR_WP7816T0(base, wi); +} +#endif + +#if FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT +/*! + * @brief Gets the current value of Work Wait Time Integer. + * + * This function gets the current value of the Work Wait Time Integer in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @return current value of the UART module Work Wait Time Integer. + */ +static inline uint16_t UART_HAL_GetWorkWaitTimeInteger(UART_Type * base) +{ + return (uint16_t)(((uint16_t)(UART_RD_WP7816A_T0(base) >> 8)) | UART_RD_WP7816B_T0(base)); +} +#else +/*! + * @brief Gets the current value of Work Wait Time Integer. + * + * This function gets the current value of the Work Wait Time Integer in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @return current value of the UART module Work Wait Time Integer. + */ +static inline uint8_t UART_HAL_GetWorkWaitTimeInteger(UART_Type * base) +{ + return UART_RD_WP7816T0(base); +} +#endif + +/*! + * @brief Sets a value to Character Wait Time Integer. + * + * This function sets a value to the Character Wait Time Integer in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @param cwi1 value used to set to UART module Character Wait Time. + * @param cwi2 value used to set to UART module Character Wait Time. + */ +static inline void UART_HAL_SetCharacterWaitTimeInteger(UART_Type * base, uint8_t cwi1, uint8_t cwi2) +{ +#if FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT + UART_BWR_WGP7816_T1_CWI1(base, cwi1); + UART_BWR_WP7816C_T1_CWI2(base, cwi2); +#else + UART_BWR_WP7816T1_CWI(base, (uint8_t)(cwi1 & 0xFU)); +#endif +} + +/*! + * @brief Gets the current value of Character Wait Time Integer. + * + * This function gets the current value of the Character Wait Time Integer in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @param ptrCwi1 pointer to hold return value of cwi1 parameter. + * @param ptrCwi2 pointer to hold return value of cwi2 parameter. + */ +static inline void UART_HAL_GetCharacterWaitTimeInteger(UART_Type * base, uint8_t *ptrCwi1, uint8_t *ptrCwi2) +{ + assert(ptrCwi1 == NULL); + assert(ptrCwi2 == NULL); + +#if FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT + *ptrCwi1 = UART_BRD_WGP7816_T1_CWI1(base); + *ptrCwi2 = UART_BRD_WP7816C_T1_CWI2(base); +#else + *ptrCwi1 = UART_BRD_WP7816T1_CWI(base); +#endif +} + +#if FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT +/*! + * @brief Sets a value to Block Wait Time Integer. + * + * This function sets a value to the Block Wait Time Integer in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @param bwi value to set to UART module Block Wait Time Integer. + */ +static inline void UART_HAL_SetBlockWaitTimeInteger(UART_Type * base, uint16_t bwi) +{ + UART_WR_WP7816A_T1(base, (uint8_t)(bwi >> 8)); + UART_WR_WP7816B_T1(base, (uint8_t)bwi); +} +#else +/*! + * @brief Sets a value to Block Wait Time Integer. + * + * This function sets a value to the Block Wait Time Integer in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @param bwi value to set to UART module Block Wait Time Integer. + */ +static inline void UART_HAL_SetBlockWaitTimeInteger(UART_Type * base, uint8_t bwi) +{ + UART_WR_WP7816T1(base, (uint8_t)(bwi & 0xFU)); +} +#endif + +#if FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT +/*! + * @brief Gets the current value of Block Wait Time Integer. + * + * This function gets the current value of the Block Wait Time Integer in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @return current value of the UART module Block Wait Time Integer. + */ +static inline uint16_t UART_HAL_GetBlockWaitTimeInteger(UART_Type * base) +{ + return (uint16_t)((uint16_t)(UART_RD_WP7816A_T1(base) >> 8)| UART_RD_WP7816B_T1(base)); +} +#else +/*! + * @brief Gets the current value of Block Wait Time Integer. + * + * This function gets the current value of the Block Wait Time Integer in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @return current value of the UART module Block Wait Time Integer. + */ +static inline uint8_t UART_HAL_GetBlockWaitTimeInteger(UART_Type * base) +{ + return (uint8_t)(UART_RD_WP7816T1(base) & 0xFU); +} +#endif + +#if FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT +/*! + * @brief Sets a value to Block Guard Time Integer. + * + * This function sets a value to the Block Guard Time Integer in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @param bgi value to set to UART module Block Guard Time Integer. + */ +static inline void UART_HAL_SetBlockGuardTimeInteger(UART_Type * base, uint8_t bgi) +{ + UART_BWR_WGP7816_T1_BGI(base, bgi); +} + +/*! + * @brief Gets the current value of Block Guard Time Integer. + * + * This function gets the current value of the Block Guard Time Integer in the UART for + * a particular module base. + * + * @param base UART module base pointer. + * @return current value of the UART module Block Guard Time Integer. + */ +static inline uint8_t UART_HAL_GetBlockGuardTimeInteger(UART_Type * base) +{ + return UART_BRD_WGP7816_T1_BGI(base); +} +#endif + +#endif /* FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT */ +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __FSL_UART_HAL_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_vref_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_vref_hal.h new file mode 100755 index 0000000..5e9ba8a --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_vref_hal.h @@ -0,0 +1,329 @@ +/* + * Copyright (c) 2014, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_VREF_HAL_H__ +#define __FSL_VREF_HAL_H__ + +#include <assert.h> +#include <stdint.h> +#include <stdbool.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_VREF_COUNT + +/*! @addtogroup vref_hal*/ +/*! @{*/ + +/*! @file*/ + +/*!***************************************************************************** + * Definitions + ******************************************************************************/ +#if FSL_FEATURE_VREF_HAS_LOW_REFERENCE + +/*!< Those macros below defined to support SoC family which have have VREFL (0.4V) reference */ +#define VREF_BWR_TRM_CHOPEN VREF_BWR_VREFH_TRM_CHOPEN +#define VREF_BWR_TRM_TRIM VREF_BWR_VREFH_TRM_TRIM +#define VREF_BRD_TRM_TRIM VREF_BRD_VREFH_TRM_TRIM +#define VREF_BWR_SC_VREFEN VREF_BWR_VREFH_SC_VREFEN +#define VREF_BWR_SC_REGEN VREF_BWR_VREFH_SC_REGEN +#define VREF_BRD_SC_VREFST VREF_BRD_VREFH_SC_VREFST +#define VREF_BWR_SC_ICOMPEN VREF_BWR_VREFH_SC_ICOMPEN +#define VREF_BWR_SC_MODE_LV VREF_BWR_VREFH_SC_MODE_LV +#define VREF_BRD_SC_MODE_LV VREF_BRD_VREFH_SC_MODE_LV + +#endif + +/*! @brief VREF status return codes */ +typedef enum _vref_status +{ + kStatus_VREF_Success = 0x0U, /*!< Success. */ + kStatus_VREF_InvalidArgument = 0x1U, /*!< Invalid argument existed. */ + kStatus_VREF_Failed = 0x2U /*!< Execution failed. */ +} vref_status_t; + +/*! + * @brief VREF modes. + */ + +#if FSL_FEATURE_VREF_MODE_LV_TYPE + +typedef enum _vref_buffer_mode +{ + kVrefModeBandgapOnly = 0x0U, /*!< Bandgap on only, for stabilization and startup */ + kVrefModeHighPowerBuffer = 0x1U, /*!< High power buffer mode enabled */ + kVrefModeLowPowerBuffer = 0x2U /*!< Low power buffer mode enabled */ +} vref_buffer_mode_t; + +#else + +typedef enum _vref_buffer_mode +{ + kVrefModeBandgapOnly = 0x0U, /*!< Bandgap on only. For stabilization and startup */ + kVrefModeTightRegulationBuffer = 0x2U /*!< Tight regulation buffer enabled */ +} vref_buffer_mode_t; + +#endif /* FSL_FEATURE_VREF_MODE_LV_TYPE */ + +#if FSL_FEATURE_VREF_HAS_LOW_REFERENCE + +typedef enum _vref_voltage_reference +{ + kVrefReferenceInternal = 0x0U, /*!< Internal voltage reference */ + kVrefReferenceExternal = 0x1U /*!< External voltage reference */ +} vref_voltage_reference_t; + +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ + +/*! @brief The description structure for the VREF module. + * @internal gui name="VREF configuration" id="vrefCfg" + */ +typedef struct VrefUserConfig +{ +#if FSL_FEATURE_VREF_HAS_CHOP_OSC + bool chopOscEnable; /*!< Chop oscillator enable @internal gui name="Chop oscillator" id="chopOscEnable" */ +#endif + uint8_t trimValue; /*!< Trim bits @internal gui name="Trim value" id="trimValue" */ + bool regulatorEnable; /*!< Enable regulator @internal gui name="Regulator" id="regulatorEnable" */ +#if FSL_FEATURE_VREF_HAS_COMPENSATION + bool soccEnable; /*!< Enable Second order curvature compensation @internal gui name="Second order curvature compensation" id="soccEnable" */ +#endif + vref_buffer_mode_t bufferMode; /*!< Buffer mode selection @internal gui name="Buffer mode selection" id="bufferMode" */ +} vref_user_config_t; + +/*!***************************************************************************** + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! @name VREF related feature APIs*/ + +/*! + * @brief Initialize VREF module to default state. + * + * @param base VREF module base number. + */ +void VREF_HAL_Init(VREF_Type * base); + +/*! + * @brief Configure VREF module to known state. + * + * @param base VREF module base number. + * @param userConfigPtr Pointer to the initialization structure. See the "vref_user_config_t". + */ +void VREF_HAL_Configure(VREF_Type * base, const vref_user_config_t *userConfigPtr); + +/*! + * @brief Enable VREF module + * + * @param base VREF module base number. + */ +static inline void VREF_HAL_Enable(VREF_Type * base) +{ + VREF_BWR_SC_VREFEN(base, true); +} + +/*! + * @brief Disable VREF module + * + * @param base VREF module base number. + */ +static inline void VREF_HAL_Disable(VREF_Type * base) +{ + VREF_BWR_SC_VREFEN(base, false); +} + +/*! + * @brief Set VREF internal regulator to Enable. + * + * Cannot be enabled in very low-power modes! + * @param base VREF module base number. + * @param enable Enables or disables internal regulator + * - true : Internal regulator enable + * - false: Internal regulator disable + */ +static inline void VREF_HAL_SetInternalRegulatorCmd(VREF_Type * base, bool enable) +{ + VREF_BWR_SC_REGEN(base, enable); +} + +/*! + * @brief Set trim value for voltage reference. + * + * @param base VREF module base number. + * @param trimValue Value of trim register to set output reference voltage (max 0x3F (6-bit)). + */ +static inline void VREF_HAL_SetTrimVal(VREF_Type * base, uint8_t trimValue) +{ + assert(trimValue <= 0x3F); + VREF_BWR_TRM_TRIM(base, trimValue); +} + +/*! + * @brief Read value of trim meaning output voltage. + * + * @param base VREF module base number. + * + * @return Six-bit value of trim setting. + */ +static inline uint8_t VREF_HAL_GetTrimVal(VREF_Type * base) +{ + return VREF_BRD_TRM_TRIM(base); +} + +/*! + * @brief Wait to internal voltage stable. + * + * @param base VREF module base number. + */ + +static inline void VREF_HAL_WaitVoltageStable(VREF_Type * base) +{ + while ((bool)VREF_BRD_SC_VREFST(base) != true) {} +} + +/*! + * @brief Set buffer mode + * + * @param base VREF module base number. + * @param mode Defines mode to be set. + * - kVrefModeBandgapOnly : Set Bandgap on only + * - kVrefModeHighPowerBuffer : Set High power buffer mode + * - kVrefModeLowPowerBuffer : Set Low power buffer mode + * - kVrefModeTightRegulationBuffer: Set Tight regulation buffer mode + */ +static inline void VREF_HAL_SetBufferMode(VREF_Type * base, vref_buffer_mode_t mode) +{ +#if FSL_FEATURE_VREF_MODE_LV_TYPE + assert(mode <= kVrefModeLowPowerBuffer); +#else + assert(mode <= kVrefModeTightRegulationBuffer); +#endif + VREF_BWR_SC_MODE_LV(base, mode); +} + +#if FSL_FEATURE_VREF_HAS_COMPENSATION +/*! + * @brief Second order curvature compensation enable. + * + * @param base VREF module base number. + * @param enable Enables or disables second order curvature compensation. + * - true : Second order curvature compensation enabled + * - false: Second order curvature compensation disabled + */ +static inline void VREF_HAL_SetSecondOrderCurvatureCompensationCmd(VREF_Type * base, bool enable) +{ + VREF_BWR_SC_ICOMPEN(base, enable); +} +#endif /* FSL_FEATURE_VREF_HAS_COMPENSATION */ + +#if FSL_FEATURE_VREF_HAS_CHOP_OSC +/*! + * @brief Chop oscillator enable. + * + * @param base VREF module base number. + * @param enable Enables or disables chop oscillator + * - true : Chop oscillator enable + * - false: Chop oscillator disable + */ +static inline void VREF_HAL_SetChopOscillatorCmd(VREF_Type * base, bool enable) +{ + VREF_BWR_TRM_CHOPEN(base, enable); +} +#endif /* FSL_FEATURE_VREF_HAS_CHOP_OSC */ + +#if FSL_FEATURE_VREF_HAS_LOW_REFERENCE +/*! + * @brief Select voltage reference + * + * @param base VREF module base number. + * @param ref Defines reference to be set. + * - kVrefReferenceInternal: Select internal reference + * - kVrefReferenceExternal: Select external reference + */ + +static inline void VREF_HAL_SetVoltageReference(VREF_Type * base, vref_voltage_reference_t ref) +{ + VREF_BWR_VREFL_TRM_VREFL_SEL(base, ref); +} + +/*! + * @brief Set VREFL (0.4 V) reference buffer. + * + * @param base VREF module base number. + * @param enable Enables or disables VREFL (0.4 V) reference buffer + * - true : Enable VREFL (0.4 V) reference buffer + * - false: Disable VREFL (0.4 V) reference buffer + */ +static inline void VREF_HAL_SetLowReference(VREF_Type * base, bool enable) +{ + VREF_BWR_VREFL_TRM_VREFL_EN(base, enable); +} + +/*! + * @brief Set trim value for low voltage reference. + * + * @param base VREF module base number. + * @param trimValue Value of trim register to set output low reference voltage (max 0x07 (3-bit) ). + */ +static inline void VREF_HAL_SetLowReferenceTrimVal(VREF_Type * base, uint8_t trimValue) +{ + assert(trimValue <= 0x07); + VREF_BWR_VREFL_TRM_VREFL_TRIM(base, trimValue); +} + +/*! + * @brief Read value of trim meaning output voltage. + * + * @param base VREF module base number. + * + * @return Three-bit value of trim setting. + */ +static inline uint8_t VREF_HAL_GetLowReferenceTrimVal(VREF_Type * base) +{ + return VREF_BRD_VREFL_TRM_VREFL_TRIM(base); +} +#endif /* FSL_FEATURE_VREF_HAS_LOW_REFERENCE */ + +/*@}*/ + + #if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif +#endif /* __FSL_VREF_HAL_H__*/ +/******************************************************************************* +* EOF +*******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_wdog_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_wdog_hal.h new file mode 100755 index 0000000..c65847d --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_wdog_hal.h @@ -0,0 +1,330 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __FSL_WDOG_HAL_H__ +#define __FSL_WDOG_HAL_H__ + +#include <assert.h> +#include <stdint.h> +#include <stdbool.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_WDOG_COUNT + +/*! + * @addtogroup wdog_hal + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @brief Descriptes wdog clock source structure */ +typedef enum _wdog_clk_src +{ + kWdogLpoClkSrc = 0U, /*!< wdog clock sourced from LPO @internal gui name="LPO clock" */ + kWdogAlternateClkSrc = 1U /*!< wdog clock sourced from alternate clock source @internal gui name="Bus clock" */ +}wdog_clk_src_t; + +/*! @brief Descriptes wdog work mode structure */ +typedef struct _wdog_work_mode +{ + bool kWdogEnableInWaitMode; /*!< Enables or disables wdog in wait mode */ + bool kWdogEnableInStopMode; /*!< Enables or disables wdog in stop mode */ + bool kWdogEnableInDebugMode; /*!< Enables or disables wdog in debug mode */ +}wdog_work_mode_t; + +/*! @brief Descripts the selection of the clock prescaler */ +typedef enum _wdog_clk_prescaler { + kWdogClkPrescalerDivide1 = 0x0U, /*!< Divided by 1 @internal gui name="1" */ + kWdogClkPrescalerDivide2 = 0x1U, /*!< Divided by 2 @internal gui name="2" */ + kWdogClkPrescalerDivide3 = 0x2U, /*!< Divided by 3 @internal gui name="3" */ + kWdogClkPrescalerDivide4 = 0x3U, /*!< Divided by 4 @internal gui name="4" */ + kWdogClkPrescalerDivide5 = 0x4U, /*!< Divided by 5 @internal gui name="5" */ + kWdogClkPrescalerDivide6 = 0x5U, /*!< Divided by 6 @internal gui name="6" */ + kWdogClkPrescalerDivide7 = 0x6U, /*!< Divided by 7 @internal gui name="7" */ + kWdogClkPrescalerDivide8 = 0x7U /*!< Divided by 8 @internal gui name="8" */ +} wdog_clk_prescaler_t; + +/*! @brief Descripts wdog configuration structure + @internal gui name="Basic configuration" id="wdogCfg" + */ +typedef struct _wdog_config +{ + bool wdogEnable; /*!< Enables or disables wdog @internal gui name="Watchdog" id="Watchdog" */ + wdog_clk_src_t clkSrc; /*!< Clock source select @internal gui name="Clock source" id="ClockSource" */ + wdog_clk_prescaler_t prescaler; /*!< Clock prescaler value @internal gui name="Clock prescaler" id="ClockPrescaler" */ + wdog_work_mode_t workMode; /*!< Configures wdog work mode in debug stop and wait mode @internal gui name="Work mode" id="WorkMode" */ + bool updateEnable; /*!< Update write-once register enable @internal gui name="Update write-once register" id="UpdateReg" */ + bool intEnable; /*!< Enables or disables wdog interrupt @internal gui name="Interrupt" id="Interrupt" */ + bool winEnable; /*!< Enables or disables wdog window mode @internal gui name="Window mode" id="WindowMode" */ + uint32_t windowValue; /*!< Window value @internal gui name="Window value" id="WindowValue" */ + uint32_t timeoutValue; /*!< Timeout value @internal gui name="Timeout value" id="TimeoutValue" */ +}wdog_config_t; + +/*! @brief wdog status return codes.*/ +typedef enum _wdog_status { + kStatus_WDOG_Success = 0x0U, /*!< WDOG operation Succeed */ + kStatus_WDOG_Fail = 0x1U, /*!< WDOG operation Failed */ + kStatus_WDOG_NotInitlialized = 0x2U, /*!< WDOG is not initialized yet */ + kStatus_WDOG_NullArgument = 0x3U, /*!< Argument is NULL */ +}wdog_status_t; + +/******************************************************************************* + * API + *******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Watchdog HAL. + * @{ + */ + +/*! + * @brief Enables the Watchdog module. + * + * This function enables the WDOG. + * Make sure that the WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that + * the WDOG_STCTRLH register has not been written in this WCT while this function is called. + * + * @param base The WDOG peripheral base address + */ +static inline void WDOG_HAL_Enable(WDOG_Type * base) +{ + WDOG_BWR_STCTRLH_WDOGEN(base, 1U); +} + +/*! + * @brief Disables the Watchdog module. + * + * This function disables the WDOG. + * Make sure that the WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that + * the WDOG_STCTRLH register has not been written in this WCT while this function is called. + * + * @param base The WDOG peripheral base address + */ +static inline void WDOG_HAL_Disable(WDOG_Type * base) +{ + WDOG_BWR_STCTRLH_WDOGEN(base, 0U); +} + +/*! + * @brief Checks whether the WDOG is enabled. + * + * This function checks whether the WDOG is enabled. + * + * @param base The WDOG peripheral base address + * @return false means WDOG is disabled, true means WODG is enabled. + * + */ +static inline bool WDOG_HAL_IsEnable(WDOG_Type * base) +{ + return (bool)WDOG_BRD_STCTRLH_WDOGEN(base); +} + +/*! + * @brief Sets the WDOG common configure. + * + * This function is used to set the WDOG common configure. + * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock, the WCT window is still open and + * the WDOG_STCTRLH register has not been written in this WCT while this function is called. + * Make sure that the WDOG_STCTRLH.ALLOWUPDATE is 1 which means that the register update is enabled. + * The common configuration is controlled by the WDOG_STCTRLH. This is a write-once register and this interface + * is used to set all field of the WDOG_STCTRLH registers at the same time. + * If only one field needs to be set, the API can be used. These API write to the WDOG_STCTRLH register: + * #WDOG_HAL_Enable,#WDOG_HAL_Disable,#WDOG_HAL_SetIntCmd,#WDOG_HAL_SetClockSourceMode,#WDOG_HAL_SetWindowModeCmd, + * #WDOG_HAL_SetRegisterUpdateCmd,#WDOG_HAL_SetWorkInDebugModeCmd,#WDOG_HAL_SetWorkInStopModeCmd, + * #WDOG_HAL_SetWorkInWaitModeCmd + * + * @param base The WDOG peripheral base address + * @param configPtr The common configure of the WDOG + */ +void WDOG_HAL_SetConfig(WDOG_Type * base, const wdog_config_t *configPtr); + +/*! + * @brief Enables and disables the Watchdog interrupt. + * + * This function enables or disables the WDOG interrupt. + * Make sure that the WDOG registers are unlocked by the WDOG_HAL_Unlock, that the WCT window is still open and that + * the WDOG_STCTRLH register has not been written in this WCT while this function is called. + * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled. + * + * @param base The WDOG peripheral base address + * @param enable false means disable watchdog interrupt and true means enable watchdog interrupt. + */ +static inline void WDOG_HAL_SetIntCmd(WDOG_Type * base, bool enable) +{ + WDOG_BWR_STCTRLH_IRQRSTEN(base, enable); +} + +/*! + * @brief Gets the Watchdog interrupt status. + * + * This function gets the WDOG interrupt flag. + * + * @param base The WDOG peripheral base address + * @return Watchdog interrupt status, false means interrupt not asserted, true means interrupt asserted. + */ +static inline bool WDOG_HAL_GetIntFlag(WDOG_Type * base) +{ + return (bool)WDOG_BRD_STCTRLL_INTFLG(base); +} + +/*! + * @brief Clears the Watchdog interrupt flag. + * + * This function clears the WDOG interrupt flag. + * + * @param base The WDOG peripheral base address + */ +static inline void WDOG_HAL_ClearIntStatusFlag(WDOG_Type * base) +{ + WDOG_BWR_STCTRLL_INTFLG(base, 1U); +} + +/*! + * @brief Set the Watchdog timeout value. + * + * This function sets the WDOG_TOVAL value. + * It should be ensured that the time-out value for the Watchdog is always greater than + * 2xWCT time + 20 bus clock cycles. + * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock , that the WCT window is still open and that + * this API has not been called in this WCT while this function is called. + * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled. + * + * @param base The WDOG peripheral base address + * @param timeoutCount watchdog timeout value, count of watchdog clock tick. + */ +static inline void WDOG_HAL_SetTimeoutValue(WDOG_Type * base, uint32_t timeoutCount) +{ + WDOG_WR_TOVALH(base, (uint16_t)((timeoutCount >> 16U) & 0xFFFFU)); + WDOG_WR_TOVALL(base, (uint16_t)((timeoutCount) & 0xFFFFU)); +} + +/*! + * @brief Gets the Watchdog timer output. + * + * This function gets the WDOG_TMROUT value. + * + * @param base The WDOG peripheral base address + * @return Current value of watchdog timer counter. + */ +static inline uint32_t WDOG_HAL_GetTimerOutputValue(WDOG_Type * base) +{ + return (uint32_t)((((uint32_t)(WDOG_RD_TMROUTH(base))) << 16U) | (WDOG_RD_TMROUTL(base))); +} + +/*! + * @brief Sets the Watchdog window value. + * + * This function sets the WDOG_WIN value. + * Make sure WDOG registers are unlocked by the WDOG_HAL_Unlock , that the WCT window is still open and that + * this API has not been called in this WCT while this function is called. + * Make sure WDOG_STCTRLH.ALLOWUPDATE is 1 which means register update is enabled. + * + * @param base The WDOG peripheral base address + * @param windowValue watchdog window value. + */ +static inline void WDOG_HAL_SetWindowValue(WDOG_Type * base, uint32_t windowValue) +{ + WDOG_WR_WINH(base, (uint16_t)((windowValue>>16U) & 0xFFFFU)); + WDOG_WR_WINL(base, (uint16_t)((windowValue) & 0xFFFFU)); +} + +/*! + * @brief Unlocks the Watchdog register written. + * + * This function unlocks the WDOG register written. + * This function must be called before any configuration is set because watchdog register + * will be locked automatically after a WCT(256 bus cycles). + * + * @param base The WDOG peripheral base address + */ +static inline void WDOG_HAL_Unlock(WDOG_Type * base) +{ + WDOG_WR_UNLOCK(base, 0xC520U); + WDOG_WR_UNLOCK(base, 0xD928U); +} + +/*! + * @brief Refreshes the Watchdog timer. + * + * This function feeds the WDOG. + * This function should be called before watchdog timer is in timeout. Otherwise, a reset is asserted. + * + * @param base The WDOG peripheral base address + */ +static inline void WDOG_HAL_Refresh(WDOG_Type * base) +{ + WDOG_WR_REFRESH(base, 0xA602U); + WDOG_WR_REFRESH(base, 0xB480U); +} + +/*! + * @brief Resets the chip using the Watchdog. + * + * This function resets the chip using WDOG. + * + * @param base The WDOG peripheral base address + */ +static inline void WDOG_HAL_ResetSystem(WDOG_Type * base) +{ + WDOG_WR_REFRESH(base, 0xA602U); + WDOG_WR_REFRESH(base, 0); + while(1) + { + } +} + +/*! + * @brief Restores the WDOG module to reset value. + * + * This function restores the WDOG module to reset value. + * + * @param base The WDOG peripheral base address + */ +void WDOG_HAL_Init(WDOG_Type * base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif +#endif /* __FSL_WDOG_HAL_H__*/ +/******************************************************************************* + * EOF + *******************************************************************************/ + diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_xbar_hal.h b/KSDK_1.2.0/platform/hal/inc/fsl_xbar_hal.h new file mode 100755 index 0000000..d2a695d --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_xbar_hal.h @@ -0,0 +1,445 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#if !defined(__FSL_XBAR_HAL_H__) +#define __FSL_XBAR_HAL_H__ + +#include <assert.h> +#include <stdbool.h> +#include "fsl_device_registers.h" +#if FSL_FEATURE_SOC_XBAR_COUNT + +/*! + * @addtogroup xbar_hal + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! + * @brief XBAR active edge for detection + */ +typedef enum _xbar_active_edge_detect +{ + kXbarEdgeNone = 0U, /*!< Edge detection status bit never asserts. */ + kXbarEdgeRising = 1U, /*!< Edge detection status bit asserts on rising edges. */ + kXbarEdgeFalling = 2U, /*!< Edge detection status bit asserts on falling edges. */ + kXbarEdgeRisingAndFalling = 3U /*!< Edge detection status bit asserts on rising and falling edges. */ +}xbar_active_edge_t; + +/*! + * @brief Defines XBAR status return codes. + */ +typedef enum _xbar_status +{ + kStatus_XBAR_Success = 0U, /*!< Success */ + kStatus_XBAR_InvalidArgument = 1U, /*!< Invalid argument existed */ + kStatus_XBAR_Initialized = 2U, /*!< Xbar has been already initialized */ + kStatus_XBAR_Failed = 3U /*!< Execution failed */ +} xbar_status_t; + +#if defined FSL_FEATURE_XBAR_HAS_SINGLE_MODULE +#define XBARA_Type XBAR_Type +#define XBARA_SELx_ADDR(x, n) XBAR_SELx_ADDR(x, n) +#define XBARA_CTRLx_ADDR(x, n) XBAR_CTRLx_ADDR(x, n) +#define XBARA_WR_SELx_SELx(x, n, v) XBAR_WR_SELx_SELx(x, n, v) +#define XBARA_RD_SELx_SELx(x, n) XBAR_RD_SELx_SELx(x, n) +#define XBARA_WR_CTRLx_DENx(x, n, v) XBAR_WR_CTRLx_DENx(x, n, v) +#define XBARA_RD_CTRLx_DENx(x, n) XBAR_RD_CTRLx_DENx(x, n) +#define XBARA_WR_CTRLx_IENx(x, n, v) XBAR_WR_CTRLx_IENx(x, n, v) +#define XBARA_RD_CTRLx_IENx(x, n) XBAR_RD_CTRLx_IENx(x, n) +#define XBARA_WR_CTRLx_EDGEx(x, n, v) XBAR_WR_CTRLx_EDGEx(x, n, v) +#define XBARA_RD_CTRLx_EDGEx(x, n) XBAR_RD_CTRLx_EDGEx(x, n) +#define XBARA_CLR_CTRLx_STSx(x, n) XBAR_CLR_CTRLx_STSx(x, n) +#define XBARA_RD_CTRLx_STSx(x, n) XBAR_RD_CTRLx_STSx(x, n) +#define FSL_FEATURE_XBARA_INTERRUPT_COUNT FSL_FEATURE_XBAR_INTERRUPT_COUNT +#define FSL_FEATURE_XBARA_MODULE_OUTPUTS FSL_FEATURE_XBAR_MODULE_OUTPUTS +#define FSL_FEATURE_XBARA_MODULE_INPUTS FSL_FEATURE_XBAR_MODULE_INPUTS +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initializes the XBARA module to the reset state. + * + * @param baseAddr Register base address for XBAR module. + */ +void XBARA_HAL_Init(XBARA_Type * baseAddr); + +/*! + * @brief Selects which of the shared inputs XBARA_IN[*] is muxed to selected output XBARA_OUT[*]. + * + * This function selects which of the shared inputs XBARA_IN[*] is muxed to selected output XBARA_OUT[*]. + * + * @param baseAddr Register base address for XBARA module. + * @param input Input to be muxed to selected XBARA_OUT[*] output. + * @param outIndex Selected output XBARA_OUT[*]. + */ +static inline void XBARA_HAL_SetOutSel(XBARA_Type * baseAddr, uint32_t outIndex, uint32_t input) +{ + assert(outIndex <= FSL_FEATURE_XBARA_MODULE_OUTPUTS); + XBARA_WR_SELx_SELx(baseAddr, outIndex, input); +} + +/*! + * @brief Gets input XBARA_IN[*] muxed to selected output XBARA_OUT[*]. + * + * This function gets input XBARA_IN[*] muxed to selected output XBARA_OUT[*]. + * + * @param baseAddr Register base address for XBAR module. + * @param outIndex Selected XBARA_OUT[*] output. + * @return Input XBARA_IN[*] muxed to selected XBARA_OUT[*] output. + */ +static inline uint32_t XBARA_HAL_GetOutSel(XBARA_Type * baseAddr, uint32_t outIndex) +{ + assert(outIndex <= FSL_FEATURE_XBARA_MODULE_OUTPUTS); + return (uint32_t)XBARA_RD_SELx_SELx(baseAddr, outIndex); +} + +/*! + * @brief Sets the DMA function on the corresponding XBARA_OUT[*] output. + * + * This function sets the DMA function on the corresponding XBARA_OUT[*]. When the interrupt is + * enabled, the output INT_REQn reflects the value STSn. When the interrupt is disabled, INT_REQn + * remains low. The interrupt request is cleared by writing a 1 to STSn. + * + * @param baseAddr Register base address for XBARA module. + * @param outIndex Selected XBARA_OUT[*] output. + * @param enable Bool value for enable or disable DMA request. + */ +static inline void XBARA_HAL_SetDMAOutCmd(XBARA_Type * baseAddr, uint32_t outIndex, bool enable) +{ + assert(outIndex < FSL_FEATURE_XBARA_INTERRUPT_COUNT); + XBARA_WR_CTRLx_DENx(baseAddr, outIndex, enable); +} + +/*! + * @brief Sets the interrupt function on the corresponding XBARA_OUT[*] output. + * + * This function sets the interrupt function on the corresponding XBARA_OUT[*]. When enabled, DMA_REQn + * presents the value STSn. When disabled, the DMA_REQn output remains low. + * + * @param baseAddr Register base address for XBARA module. + * @param outIndex Selected XBARA_OUT[*] output. + * @param enable Bool value for enable or disable interrupt. + */ +static inline void XBARA_HAL_SetIntOutCmd(XBARA_Type * baseAddr, uint32_t outIndex, bool enable) +{ + assert(outIndex < FSL_FEATURE_XBARA_INTERRUPT_COUNT); + XBARA_WR_CTRLx_IENx(baseAddr, outIndex, enable); +} + +/*! + * @brief Checks whether the DMA function is enabled or disabled on the corresponding XBARA_OUT[*] output. + * + * @param baseAddr Register base address for XBARA module. + * @param outIndex Selected XBARA_OUT[*] output. + * @return DMA function is enabled (true) or disabled (false). + */ +static inline bool XBARA_HAL_GetDMAOutCmd(XBARA_Type * baseAddr, uint32_t outIndex) +{ + assert(outIndex < FSL_FEATURE_XBARA_INTERRUPT_COUNT); + return XBARA_RD_CTRLx_DENx(baseAddr, outIndex); +} + +/*! + * @brief Checks whether the interrupt function is enabled or disabled on the corresponding XBARA_OUT[*] output. + * + * @param baseAddr Register base address for XBARA module. + * @param outIndex Selected XBARA_OUT[*] output. + * @return Interrupt function is enabled (true) or disabled (false). + */ +static inline bool XBARA_HAL_GetIntOutCmd(XBARA_Type * baseAddr, uint32_t outIndex) +{ + assert(outIndex < FSL_FEATURE_XBARA_INTERRUPT_COUNT); + return XBARA_RD_CTRLx_IENx(baseAddr, outIndex); +} + +/*! + * @brief Selects which edges on the corresponding XBARA_OUT[*] output cause STSn to assert. + * + * This function selects which edges on the corresponding XBARA_OUT[*] output cause STSn to assert. + * + * @param baseAddr Register base address for XBAR module. + * @param outIndex Selected XBARA_OUT[*] output. + * @param edge Active edge for edge detection. + */ +static inline void XBARA_HAL_SetOutActiveEdge(XBARA_Type * baseAddr, uint32_t outIndex, xbar_active_edge_t edge) +{ + assert(outIndex < FSL_FEATURE_XBARA_INTERRUPT_COUNT); + XBARA_WR_CTRLx_EDGEx(baseAddr, outIndex, edge); +} + +/*! + * @brief Gets which edges on the corresponding XBARA_OUT[*] output cause STSn to assert. + * + * This function gets which edges on the corresponding XBARA_OUT[*] output cause STSn to assert. + * + * @param baseAddr Register base address for XBARA module. + * @param outIndex Selected XBARA_OUT[*] output. + * @return Active edge for edge detection on corresponding XBARA_OUT[*] output. + */ +static inline xbar_active_edge_t XBARA_HAL_GetOutActiveEdge(XBARA_Type * baseAddr, uint32_t outIndex) +{ + assert(outIndex < FSL_FEATURE_XBARA_INTERRUPT_COUNT); + return (xbar_active_edge_t) XBARA_RD_CTRLx_EDGEx(baseAddr, outIndex); +} + +/*! + * @brief Clears the edge detection status for the corresponding XBARA_OUT[*] output. + * + * @param baseAddr Register base address for XBARA module. + * @param outIndex Selected XBARA_OUT[*] output. + */ +static inline void XBARA_HAL_ClearEdgeDetectionStatus(XBARA_Type * baseAddr, uint32_t outIndex) +{ + assert(outIndex < FSL_FEATURE_XBARA_INTERRUPT_COUNT); + XBARA_CLR_CTRLx_STSx(baseAddr, outIndex); +} + +/*! + * @brief Gets the edge detection status for the corresponding XBARA_OUT[*] output. + * + * @param baseAddr Register base address for XBARA module. + * @param outIndex Selected XBARA_OUT[*] output. + * @return Active edge detected (true) or not yet detected (false) on corresponind XBARA_OUT[*] output. + */ +static inline bool XBARA_HAL_GetEdgeDetectionStatus(XBARA_Type * baseAddr, uint32_t outIndex) +{ + assert(outIndex < FSL_FEATURE_XBARA_INTERRUPT_COUNT); + return XBARA_RD_CTRLx_STSx(baseAddr, outIndex); +} + +#if !defined FSL_FEATURE_XBAR_HAS_SINGLE_MODULE + +/*! + * @brief Initializes the XBARB module to the reset state. + * + * @param baseAddr Register base address for XBARB module. + */ +void XBARB_HAL_Init(XBARB_Type * baseAddr); + +/*! + * @brief Selects which of the shared inputs XBARB_IN[*] is muxed to selected output XBARB_OUT[*] . + * + * This function selects which of the shared inputs XBARB_IN[*] is muxed + * to selected output XBARB_OUT[*] + * + * @param baseAddr Register base address for XBARB module. + * @param outIndex Selected XBARB_OUT[*] output. + * @param input Input to be muxed to selected XBARB_OUT[*] output. + */ +static inline void XBARB_HAL_SetOutSel(XBARB_Type * baseAddr, uint32_t outIndex, uint32_t input) +{ + assert(outIndex < FSL_FEATURE_XBARB_MODULE_OUTPUTS); + XBARB_WR_SELx_SELx(baseAddr, outIndex, input); +} + +/*! + * @brief Gets input XBARB_IN[*] muxed to selected output XBARB_OUT[*] . + * + * This function gets input XBARB_IN[*] muxed to selected output XBARB_OUT[*] + * + * @param baseAddr Register base address for XBARB module. + * @param outIndex Selected XBARB_OUT[*] output. + * @return Input XBARB_IN[*] muxed to selected XBARB_OUT[*] output. + */ +static inline uint32_t XBARB_HAL_GetOutSel(XBARB_Type * baseAddr, uint32_t outIndex) +{ + assert(outIndex < FSL_FEATURE_XBARB_MODULE_OUTPUTS); + return (uint32_t)XBARB_RD_SELx_SELx(baseAddr, outIndex); +} +#else +/*! + * @brief Initializes the XBAR module to the reset state. + * + * @param baseAddr Register base address for XBAR module. + */ +static inline void XBAR_HAL_Init(XBAR_Type * baseAddr) +{ + XBARA_HAL_Init(baseAddr); +} + +/*! + * @brief Selects which of the shared inputs XBAR_IN[*] is muxed to selected output XBAR_OUT[*]. + * + * This function selects which of the shared inputs XBAR_IN[*] is muxed to selected output XBAR_OUT[*]. + * + * @param baseAddr Register base address for XBAR module. + * @param input Input to be muxed to selected XBAR_OUT[*] output. + * @param outIndex Selected output XBAR_OUT[*]. + */ +static inline void XBAR_HAL_SetOutSel(XBAR_Type * baseAddr, uint32_t outIndex, uint32_t input) +{ + XBARA_HAL_SetOutSel(baseAddr, outIndex, input); +} + +/*! + * @brief Gets input XBAR_IN[*] muxed to selected output XBAR_OUT[*]. + * + * This function gets input XBAR_IN[*] muxed to selected output XBAR_OUT[*]. + * + * @param baseAddr Register base address for XBAR module. + * @param outIndex Selected XBAR_OUT[*] output. + * @return Input XBARA_IN[*] muxed to selected XBAR_OUT[*] output. + */ +static inline uint32_t XBAR_HAL_GetOutSel(XBAR_Type * baseAddr, uint32_t outIndex) +{ + return XBARA_HAL_GetOutSel(baseAddr, outIndex); +} + +/*! + * @brief Sets the DMA function on the corresponding XBARA_OUT[*] output. + * + * This function sets the DMA function on the corresponding XBARA_OUT[*]. When the interrupt is + * enabled, the output INT_REQn reflects the value STSn. When the interrupt is disabled, INT_REQn + * remains low. The interrupt request is cleared by writing a 1 to STSn. + * + * @param baseAddr Register base address for XBARA module. + * @param outIndex Selected XBARA_OUT[*] output. + * @param enable Bool value for enable or disable DMA request. + */ +static inline void XBAR_HAL_SetDMAOutCmd(XBAR_Type * baseAddr, uint32_t outIndex, bool enable) +{ + XBARA_HAL_SetDMAOutCmd(baseAddr, outIndex, enable); +} + +/*! + * @brief Sets the interrupt function on the corresponding XBAR_OUT[*] output. + * + * This function sets the interrupt function on the corresponding XBAR_OUT[*]. When enabled, DMA_REQn + * presents the value STSn. When disabled, the DMA_REQn output remains low. + * + * @param baseAddr Register base address for XBAR module. + * @param outIndex Selected XBAR_OUT[*] output. + * @param enable Bool value for enable or disable interrupt. + */ +static inline void XBAR_HAL_SetIntOutCmd(XBAR_Type * baseAddr, uint32_t outIndex, bool enable) +{ + XBARA_HAL_SetIntOutCmd(baseAddr, outIndex, enable); +} + +/*! + * @brief Checks whether the DMA function is enabled or disabled on the corresponding XBAR_OUT[*] output. + * + * @param baseAddr Register base address for XBAR module. + * @param outIndex Selected XBAR_OUT[*] output. + * @return DMA function is enabled (true) or disabled (false). + */ +static inline bool XBAR_HAL_GetDMAOutCmd(XBAR_Type * baseAddr, uint32_t outIndex) +{ + return XBARA_HAL_GetDMAOutCmd(baseAddr, outIndex); +} + +/*! + * @brief Checks whether the interrupt function is enabled or disabled on the corresponding XBAR_OUT[*] output. + * + * @param baseAddr Register base address for XBAR module. + * @param outIndex Selected XBAR_OUT[*] output. + * @return Interrupt function is enabled (true) or disabled (false). + */ +static inline bool XBAR_HAL_GetIntOutCmd(XBAR_Type * baseAddr, uint32_t outIndex) +{ + return XBARA_HAL_GetIntOutCmd(baseAddr, outIndex); +} + +/*! + * @brief Selects which edges on the corresponding XBAR_OUT[*] output cause STSn to assert. + * + * This function selects which edges on the corresponding XBAR_OUT[*] output cause STSn to assert. + * + * @param baseAddr Register base address for XBAR module. + * @param outIndex Selected XBAR_OUT[*] output. + * @param edge Active edge for edge detection. + */ +static inline void XBAR_HAL_SetOutActiveEdge(XBAR_Type * baseAddr, uint32_t outIndex, xbar_active_edge_t edge) +{ + XBARA_HAL_SetOutActiveEdge(baseAddr, outIndex, edge); +} + +/*! + * @brief Gets which edges on the corresponding XBAR_OUT[*] output cause STSn to assert. + * + * This function gets which edges on the corresponding XBAR_OUT[*] output cause STSn to assert. + * + * @param baseAddr Register base address for XBAR module. + * @param outIndex Selected XBAR_OUT[*] output. + * @return Active edge for edge detection on corresponding XBAR_OUT[*] output. + */ +static inline xbar_active_edge_t XBAR_HAL_GetOutActiveEdge(XBAR_Type * baseAddr, uint32_t outIndex) +{ + return XBARA_HAL_GetOutActiveEdge(baseAddr, outIndex); +} + +/*! + * @brief Clears the edge detection status for the corresponding XBAR_OUT[*] output. + * + * @param baseAddr Register base address for XBAR module. + * @param outIndex Selected XBAR_OUT[*] output. + */ +static inline void XBAR_HAL_ClearEdgeDetectionStatus(XBAR_Type * baseAddr, uint32_t outIndex) +{ + XBARA_HAL_ClearEdgeDetectionStatus(baseAddr, outIndex); +} + +/*! + * @brief Gets the edge detection status for the corresponding XBAR_OUT[*] output. + * + * @param baseAddr Register base address for XBAR module. + * @param outIndex Selected XBAR_OUT[*] output. + * @return Active edge detected (true) or not yet detected (false) on corresponind XBAR_OUT[*] output. + */ +static inline bool XBAR_HAL_GetEdgeDetectionStatus(XBAR_Type * baseAddr, uint32_t outIndex) +{ + return XBARA_HAL_GetEdgeDetectionStatus(baseAddr, outIndex); +} + +#endif/* FSL_FEATURE_XBAR_HAS_SINGLE_MODULE */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif +#endif /* __FSL_XBAR_HAL_H__*/ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/KSDK_1.2.0/platform/hal/inc/fsl_xbar_signals.h b/KSDK_1.2.0/platform/hal/inc/fsl_xbar_signals.h new file mode 100755 index 0000000..12d01a7 --- /dev/null +++ b/KSDK_1.2.0/platform/hal/inc/fsl_xbar_signals.h @@ -0,0 +1,1083 @@ +/* +** ################################################################### +** Version: rev. 1.0, 2014-05-14 +** Build: b150317 +** +** Abstract: +** Chip specific module features. +** +** Copyright (c) 2014 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2014-05-14) +** Customer release. +** +** ################################################################### +*/ + +#if !defined(__FSL_XBAR_SIGNALS_H__) +#define __FSL_XBAR_SIGNALS_H__ + + +typedef enum _xbar_input_signal { +#if defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F64VLH15) + kXbaraInputVSS = 0|0x100U, /*!< Logic zero output assigned to XBARA_IN0 input. */ + kXbaraInputVDD = 1|0x100U, /*!< Logic one output assigned to XBARA_IN1 input. */ + kXbaraInputXBARIN2 = 2|0x100U, /*!< XBARIN2 input pin output assigned to XBARA_IN2 input. */ + kXbaraInputXBARIN3 = 3|0x100U, /*!< XBARIN3 input pin output assigned to XBARA_IN3 input. */ + kXbaraInputXBARIN4 = 4|0x100U, /*!< XBARIN4 input pin output assigned to XBARA_IN4 input. */ + kXbaraInputXBARIN5 = 5|0x100U, /*!< XBARIN5 input pin output assigned to XBARA_IN5 input. */ + kXbaraInputXBARIN6 = 6|0x100U, /*!< XBARIN6 input pin output assigned to XBARA_IN6 input. */ + kXbaraInputXBARIN7 = 7|0x100U, /*!< XBARIN7 input pin output assigned to XBARA_IN7 input. */ + kXbaraInputXBARIN8 = 8|0x100U, /*!< XBARIN8 input pin output assigned to XBARA_IN8 input. */ + kXbaraInputXBARIN9 = 9|0x100U, /*!< XBARIN9 input pin output assigned to XBARA_IN9 input. */ + kXbaraInputXBARIN10 = 10|0x100U, /*!< XBARIN10 input pin output assigned to XBARA_IN10 input. */ + kXbaraInputXBARIN11 = 11|0x100U, /*!< XBARIN11 input pin output assigned to XBARA_IN11 input. */ + kXbaraInputCMP0_output = 12|0x100U, /*!< CMP0 Output output assigned to XBARA_IN12 input. */ + kXbaraInputCMP1_output = 13|0x100U, /*!< CMP1 Output output assigned to XBARA_IN13 input. */ + kXbaraInputCMP2_output = 14|0x100U, /*!< CMP2 Output output assigned to XBARA_IN14 input. */ + kXbaraInputCMP3_output = 15|0x100U, /*!< CMP3 Output output assigned to XBARA_IN15 input. */ + kXbaraInputFTM0_match = 16|0x100U, /*!< FTM0 all channels output compare ORed together output assigned to XBARA_IN16 input. */ + kXbaraInputFTM0_EXTRIG = 17|0x100U, /*!< FTM0 all channels counter init ORed together output assigned to XBARA_IN17 input. */ + kXbaraInputRESERVED18 = 18|0x100U, /*!< XBARA_IN18 input is reserved. */ + kXbaraInputRESERVED19 = 19|0x100U, /*!< XBARA_IN19 input is reserved. */ + kXbaraInputRESERVED20 = 20|0x100U, /*!< XBARA_IN20 input is reserved. */ + kXbaraInputRESERVED21 = 21|0x100U, /*!< XBARA_IN21 input is reserved. */ + kXbaraInputRESERVED22 = 22|0x100U, /*!< XBARA_IN22 input is reserved. */ + kXbaraInputRESERVED23 = 23|0x100U, /*!< XBARA_IN23 input is reserved. */ + kXbaraInputRESERVED24 = 24|0x100U, /*!< XBARA_IN24 input is reserved. */ + kXbaraInputRESERVED25 = 25|0x100U, /*!< XBARA_IN25 input is reserved. */ + kXbaraInputRESERVED26 = 26|0x100U, /*!< XBARA_IN26 input is reserved. */ + kXbaraInputRESERVED27 = 27|0x100U, /*!< XBARA_IN27 input is reserved. */ + kXbaraInputRESERVED28 = 28|0x100U, /*!< XBARA_IN28 input is reserved. */ + kXbaraInputPDB0_CH0_Output = 29|0x100U, /*!< PDB0 channel 0 output trigger output assigned to XBARA_IN29 input. */ + kXbaraInputRESERVED30 = 30|0x100U, /*!< XBARA_IN30 input is reserved. */ + kXbaraInputPDB1_CH0_Output = 31|0x100U, /*!< PDB1 channel 0 output trigger output assigned to XBARA_IN31 input. */ + kXbaraInputRESERVED32 = 32|0x100U, /*!< XBARA_IN32 input is reserved. */ + kXbaraInputADCA_ES = 33|0x100U, /*!< ADC converter A end of scan output assigned to XBARA_IN33 input. */ + kXbaraInputRESERVED34 = 34|0x100U, /*!< XBARA_IN34 input is reserved. */ + kXbaraInputADCB_ES = 35|0x100U, /*!< ADC converter B end of scan output assigned to XBARA_IN35 input. */ + kXbaraInputFTM1_match = 36|0x100U, /*!< FTM1 all channels output compare ORed together output assigned to XBARA_IN36 input. */ + kXbaraInputFTM1_EXTRIG = 37|0x100U, /*!< FTM1 all channels counter init ORed together output assigned to XBARA_IN37 input. */ + kXbaraInputDMA_CH0_done = 38|0x100U, /*!< DMA channel 0 done output assigned to XBARA_IN38 input. */ + kXbaraInputDMA_CH1_done = 39|0x100U, /*!< DMA channel 1 done output assigned to XBARA_IN39 input. */ + kXbaraInputDMA_CH6_done = 40|0x100U, /*!< DMA channel 6 done output assigned to XBARA_IN40 input. */ + kXbaraInputDMA_CH7_done = 41|0x100U, /*!< DMA channel 7 done output assigned to XBARA_IN41 input. */ + kXbaraInputPIT_trigger_0 = 42|0x100U, /*!< PIT trigger 0 output assigned to XBARA_IN42 input. */ + kXbaraInputPIT_trigger_1 = 43|0x100U, /*!< PIT trigger 1 output assigned to XBARA_IN43 input. */ + kXbaraInputRESERVED44 = 44|0x100U, /*!< XBARA_IN44 input is reserved. */ + kXbaraInputENC_CMP_pos_match = 45|0x100U, /*!< ENC compare trigger and position match output assigned to XBARA_IN45 input. */ + kXbaraInputAND_OR_INVERT_0 = 46|0x100U, /*!< AOI output 0 output assigned to XBARA_IN46 input. */ + kXbaraInputAND_OR_INVERT_1 = 47|0x100U, /*!< AOI output 1 output assigned to XBARA_IN47 input. */ + kXbaraInputAND_OR_INVERT_2 = 48|0x100U, /*!< AOI output 2 output assigned to XBARA_IN48 input. */ + kXbaraInputAND_OR_INVERT_3 = 49|0x100U, /*!< AOI output 3 output assigned to XBARA_IN49 input. */ + kXbaraInputPIT_trigger_2 = 50|0x100U, /*!< PIT trigger 2 output assigned to XBARA_IN50 input. */ + kXbaraInputPIT_trigger_3 = 51|0x100U, /*!< PIT trigger 3 output assigned to XBARA_IN51 input. */ + kXbarbInputCMP0_output = 0|0x200U, /*!< CMP0 Output output assigned to XBARB_IN0 input. */ + kXbarbInputCMP1_output = 1|0x200U, /*!< CMP1 Output output assigned to XBARB_IN1 input. */ + kXbarbInputCMP2_output = 2|0x200U, /*!< CMP2 Output output assigned to XBARB_IN2 input. */ + kXbarbInputCMP3_output = 3|0x200U, /*!< CMP3 Output output assigned to XBARB_IN3 input. */ + kXbarbInputFTM0_match = 4|0x200U, /*!< FTM0 all channels output compare ORed together output assigned to XBARB_IN4 input. */ + kXbarbInputFTM0_EXTRIG = 5|0x200U, /*!< FTM0 all channels counter init ORed together output assigned to XBARB_IN5 input. */ + kXbarbInputRESERVED6 = 6|0x200U, /*!< XBARB_IN6 input is reserved. */ + kXbarbInputRESERVED7 = 7|0x200U, /*!< XBARB_IN7 input is reserved. */ + kXbarbInputRESERVED8 = 8|0x200U, /*!< XBARB_IN8 input is reserved. */ + kXbarbInputRESERVED9 = 9|0x200U, /*!< XBARB_IN9 input is reserved. */ + kXbarbInputRESERVED10 = 10|0x200U, /*!< XBARB_IN10 input is reserved. */ + kXbarbInputRESERVED11 = 11|0x200U, /*!< XBARB_IN11 input is reserved. */ + kXbarbInputPDB0_CH0_Output = 12|0x200U, /*!< PDB0 channel 0 output trigger output assigned to XBARB_IN12 input. */ + kXbarbInputADCA_ES = 13|0x200U, /*!< ADC converter A end of scan output assigned to XBARB_IN13 input. */ + kXbarbInputXBARIN2 = 14|0x200U, /*!< XBARIN2 input pin output assigned to XBARB_IN14 input. */ + kXbarbInputXBARIN3 = 15|0x200U, /*!< XBARIN3 input pin output assigned to XBARB_IN15 input. */ + kXbarbInputFTM1_match = 16|0x200U, /*!< FTM1 all channels output compare ORed together output assigned to XBARB_IN16 input. */ + kXbarbInputFTM1_EXTRIG = 17|0x200U, /*!< FTM1 all channels counter init ORed together output assigned to XBARB_IN17 input. */ + kXbarbInputDMA_CH0_done = 18|0x200U, /*!< DMA channel 0 done output assigned to XBARB_IN18 input. */ + kXbarbInputDMA_CH1_done = 19|0x200U, /*!< DMA channel 1 done output assigned to XBARB_IN19 input. */ + kXbarbInputXBARIN10 = 20|0x200U, /*!< XBARIN10 input pin output assigned to XBARB_IN20 input. */ + kXbarbInputXBARIN11 = 21|0x200U, /*!< XBARIN11 input pin output assigned to XBARB_IN21 input. */ + kXbarbInputDMA_CH6_done = 22|0x200U, /*!< DMA channel 6 done output assigned to XBARB_IN22 input. */ + kXbarbInputDMA_CH7_done = 23|0x200U, /*!< DMA channel 7 done output assigned to XBARB_IN23 input. */ + kXbarbInputPIT_trigger_0 = 24|0x200U, /*!< PIT trigger 0 output assigned to XBARB_IN24 input. */ + kXbarbInputPIT_trigger_1 = 25|0x200U, /*!< PIT trigger 1 output assigned to XBARB_IN25 input. */ + kXbarbInputPDB1_CH0_Output = 26|0x200U, /*!< PDB1 channel 0 output trigger output assigned to XBARB_IN26 input. */ + kXbarbInputADCB_ES = 27|0x200U, /*!< ADC converter B end of scan output assigned to XBARB_IN27 input. */ +#elif defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLL15) + kXbaraInputVSS = 0|0x100U, /*!< Logic zero output assigned to XBARA_IN0 input. */ + kXbaraInputVDD = 1|0x100U, /*!< Logic one output assigned to XBARA_IN1 input. */ + kXbaraInputXBARIN2 = 2|0x100U, /*!< XBARIN2 input pin output assigned to XBARA_IN2 input. */ + kXbaraInputXBARIN3 = 3|0x100U, /*!< XBARIN3 input pin output assigned to XBARA_IN3 input. */ + kXbaraInputXBARIN4 = 4|0x100U, /*!< XBARIN4 input pin output assigned to XBARA_IN4 input. */ + kXbaraInputXBARIN5 = 5|0x100U, /*!< XBARIN5 input pin output assigned to XBARA_IN5 input. */ + kXbaraInputXBARIN6 = 6|0x100U, /*!< XBARIN6 input pin output assigned to XBARA_IN6 input. */ + kXbaraInputXBARIN7 = 7|0x100U, /*!< XBARIN7 input pin output assigned to XBARA_IN7 input. */ + kXbaraInputXBARIN8 = 8|0x100U, /*!< XBARIN8 input pin output assigned to XBARA_IN8 input. */ + kXbaraInputXBARIN9 = 9|0x100U, /*!< XBARIN9 input pin output assigned to XBARA_IN9 input. */ + kXbaraInputXBARIN10 = 10|0x100U, /*!< XBARIN10 input pin output assigned to XBARA_IN10 input. */ + kXbaraInputXBARIN11 = 11|0x100U, /*!< XBARIN11 input pin output assigned to XBARA_IN11 input. */ + kXbaraInputCMP0_output = 12|0x100U, /*!< CMP0 Output output assigned to XBARA_IN12 input. */ + kXbaraInputCMP1_output = 13|0x100U, /*!< CMP1 Output output assigned to XBARA_IN13 input. */ + kXbaraInputCMP2_output = 14|0x100U, /*!< CMP2 Output output assigned to XBARA_IN14 input. */ + kXbaraInputCMP3_output = 15|0x100U, /*!< CMP3 Output output assigned to XBARA_IN15 input. */ + kXbaraInputFTM0_match = 16|0x100U, /*!< FTM0 all channels output compare ORed together output assigned to XBARA_IN16 input. */ + kXbaraInputFTM0_EXTRIG = 17|0x100U, /*!< FTM0 all channels counter init ORed together output assigned to XBARA_IN17 input. */ + kXbaraInputFTM3_match = 18|0x100U, /*!< FTM3 all channels output compare ORed together output assigned to XBARA_IN18 input. */ + kXbaraInputFTM3_EXTRIG = 19|0x100U, /*!< FTM3 all channels counter init ORed together output assigned to XBARA_IN19 input. */ + kXbaraInputRESERVED20 = 20|0x100U, /*!< XBARA_IN20 input is reserved. */ + kXbaraInputRESERVED21 = 21|0x100U, /*!< XBARA_IN21 input is reserved. */ + kXbaraInputRESERVED22 = 22|0x100U, /*!< XBARA_IN22 input is reserved. */ + kXbaraInputRESERVED23 = 23|0x100U, /*!< XBARA_IN23 input is reserved. */ + kXbaraInputRESERVED24 = 24|0x100U, /*!< XBARA_IN24 input is reserved. */ + kXbaraInputRESERVED25 = 25|0x100U, /*!< XBARA_IN25 input is reserved. */ + kXbaraInputRESERVED26 = 26|0x100U, /*!< XBARA_IN26 input is reserved. */ + kXbaraInputRESERVED27 = 27|0x100U, /*!< XBARA_IN27 input is reserved. */ + kXbaraInputRESERVED28 = 28|0x100U, /*!< XBARA_IN28 input is reserved. */ + kXbaraInputPDB0_CH0_Output = 29|0x100U, /*!< PDB0 channel 0 output trigger output assigned to XBARA_IN29 input. */ + kXbaraInputRESERVED30 = 30|0x100U, /*!< XBARA_IN30 input is reserved. */ + kXbaraInputPDB1_CH0_Output = 31|0x100U, /*!< PDB1 channel 0 output trigger output assigned to XBARA_IN31 input. */ + kXbaraInputRESERVED32 = 32|0x100U, /*!< XBARA_IN32 input is reserved. */ + kXbaraInputADCA_ES = 33|0x100U, /*!< ADC converter A end of scan output assigned to XBARA_IN33 input. */ + kXbaraInputRESERVED34 = 34|0x100U, /*!< XBARA_IN34 input is reserved. */ + kXbaraInputADCB_ES = 35|0x100U, /*!< ADC converter B end of scan output assigned to XBARA_IN35 input. */ + kXbaraInputFTM1_match = 36|0x100U, /*!< FTM1 all channels output compare ORed together output assigned to XBARA_IN36 input. */ + kXbaraInputFTM1_EXTRIG = 37|0x100U, /*!< FTM1 all channels counter init ORed together output assigned to XBARA_IN37 input. */ + kXbaraInputDMA_CH0_done = 38|0x100U, /*!< DMA channel 0 done output assigned to XBARA_IN38 input. */ + kXbaraInputDMA_CH1_done = 39|0x100U, /*!< DMA channel 1 done output assigned to XBARA_IN39 input. */ + kXbaraInputDMA_CH6_done = 40|0x100U, /*!< DMA channel 6 done output assigned to XBARA_IN40 input. */ + kXbaraInputDMA_CH7_done = 41|0x100U, /*!< DMA channel 7 done output assigned to XBARA_IN41 input. */ + kXbaraInputPIT_trigger_0 = 42|0x100U, /*!< PIT trigger 0 output assigned to XBARA_IN42 input. */ + kXbaraInputPIT_trigger_1 = 43|0x100U, /*!< PIT trigger 1 output assigned to XBARA_IN43 input. */ + kXbaraInputRESERVED44 = 44|0x100U, /*!< XBARA_IN44 input is reserved. */ + kXbaraInputENC_CMP_pos_match = 45|0x100U, /*!< ENC compare trigger and position match output assigned to XBARA_IN45 input. */ + kXbaraInputAND_OR_INVERT_0 = 46|0x100U, /*!< AOI output 0 output assigned to XBARA_IN46 input. */ + kXbaraInputAND_OR_INVERT_1 = 47|0x100U, /*!< AOI output 1 output assigned to XBARA_IN47 input. */ + kXbaraInputAND_OR_INVERT_2 = 48|0x100U, /*!< AOI output 2 output assigned to XBARA_IN48 input. */ + kXbaraInputAND_OR_INVERT_3 = 49|0x100U, /*!< AOI output 3 output assigned to XBARA_IN49 input. */ + kXbaraInputPIT_trigger_2 = 50|0x100U, /*!< PIT trigger 2 output assigned to XBARA_IN50 input. */ + kXbaraInputPIT_trigger_3 = 51|0x100U, /*!< PIT trigger 3 output assigned to XBARA_IN51 input. */ + kXbarbInputCMP0_output = 0|0x200U, /*!< CMP0 Output output assigned to XBARB_IN0 input. */ + kXbarbInputCMP1_output = 1|0x200U, /*!< CMP1 Output output assigned to XBARB_IN1 input. */ + kXbarbInputCMP2_output = 2|0x200U, /*!< CMP2 Output output assigned to XBARB_IN2 input. */ + kXbarbInputCMP3_output = 3|0x200U, /*!< CMP3 Output output assigned to XBARB_IN3 input. */ + kXbarbInputFTM0_match = 4|0x200U, /*!< FTM0 all channels output compare ORed together output assigned to XBARB_IN4 input. */ + kXbarbInputFTM0_EXTRIG = 5|0x200U, /*!< FTM0 all channels counter init ORed together output assigned to XBARB_IN5 input. */ + kXbarbInputFTM3_match = 6|0x200U, /*!< FTM3 all channels output compare ORed together output assigned to XBARB_IN6 input. */ + kXbarbInputFTM3_EXTRIG = 7|0x200U, /*!< FTM3 all channels counter init ORed together output assigned to XBARB_IN7 input. */ + kXbarbInputRESERVED8 = 8|0x200U, /*!< XBARB_IN8 input is reserved. */ + kXbarbInputRESERVED9 = 9|0x200U, /*!< XBARB_IN9 input is reserved. */ + kXbarbInputRESERVED10 = 10|0x200U, /*!< XBARB_IN10 input is reserved. */ + kXbarbInputRESERVED11 = 11|0x200U, /*!< XBARB_IN11 input is reserved. */ + kXbarbInputPDB0_CH0_Output = 12|0x200U, /*!< PDB0 channel 0 output trigger output assigned to XBARB_IN12 input. */ + kXbarbInputADCA_ES = 13|0x200U, /*!< ADC converter A end of scan output assigned to XBARB_IN13 input. */ + kXbarbInputXBARIN2 = 14|0x200U, /*!< XBARIN2 input pin output assigned to XBARB_IN14 input. */ + kXbarbInputXBARIN3 = 15|0x200U, /*!< XBARIN3 input pin output assigned to XBARB_IN15 input. */ + kXbarbInputFTM1_match = 16|0x200U, /*!< FTM1 all channels output compare ORed together output assigned to XBARB_IN16 input. */ + kXbarbInputFTM1_EXTRIG = 17|0x200U, /*!< FTM1 all channels counter init ORed together output assigned to XBARB_IN17 input. */ + kXbarbInputDMA_CH0_done = 18|0x200U, /*!< DMA channel 0 done output assigned to XBARB_IN18 input. */ + kXbarbInputDMA_CH1_done = 19|0x200U, /*!< DMA channel 1 done output assigned to XBARB_IN19 input. */ + kXbarbInputXBARIN10 = 20|0x200U, /*!< XBARIN10 input pin output assigned to XBARB_IN20 input. */ + kXbarbInputXBARIN11 = 21|0x200U, /*!< XBARIN11 input pin output assigned to XBARB_IN21 input. */ + kXbarbInputDMA_CH6_done = 22|0x200U, /*!< DMA channel 6 done output assigned to XBARB_IN22 input. */ + kXbarbInputDMA_CH7_done = 23|0x200U, /*!< DMA channel 7 done output assigned to XBARB_IN23 input. */ + kXbarbInputPIT_trigger_0 = 24|0x200U, /*!< PIT trigger 0 output assigned to XBARB_IN24 input. */ + kXbarbInputPIT_trigger_1 = 25|0x200U, /*!< PIT trigger 1 output assigned to XBARB_IN25 input. */ + kXbarbInputPDB1_CH0_Output = 26|0x200U, /*!< PDB1 channel 0 output trigger output assigned to XBARB_IN26 input. */ + kXbarbInputADCB_ES = 27|0x200U, /*!< ADC converter B end of scan output assigned to XBARB_IN27 input. */ +#elif defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || defined(CPU_MKV44F128VLH15) || \ + defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) + kXbaraInputVSS = 0|0x100U, /*!< Logic zero output assigned to XBARA_IN0 input. */ + kXbaraInputVDD = 1|0x100U, /*!< Logic one output assigned to XBARA_IN1 input. */ + kXbaraInputXBARIN2 = 2|0x100U, /*!< XBARIN2 input pin output assigned to XBARA_IN2 input. */ + kXbaraInputXBARIN3 = 3|0x100U, /*!< XBARIN3 input pin output assigned to XBARA_IN3 input. */ + kXbaraInputXBARIN4 = 4|0x100U, /*!< XBARIN4 input pin output assigned to XBARA_IN4 input. */ + kXbaraInputXBARIN5 = 5|0x100U, /*!< XBARIN5 input pin output assigned to XBARA_IN5 input. */ + kXbaraInputXBARIN6 = 6|0x100U, /*!< XBARIN6 input pin output assigned to XBARA_IN6 input. */ + kXbaraInputXBARIN7 = 7|0x100U, /*!< XBARIN7 input pin output assigned to XBARA_IN7 input. */ + kXbaraInputXBARIN8 = 8|0x100U, /*!< XBARIN8 input pin output assigned to XBARA_IN8 input. */ + kXbaraInputXBARIN9 = 9|0x100U, /*!< XBARIN9 input pin output assigned to XBARA_IN9 input. */ + kXbaraInputXBARIN10 = 10|0x100U, /*!< XBARIN10 input pin output assigned to XBARA_IN10 input. */ + kXbaraInputXBARIN11 = 11|0x100U, /*!< XBARIN11 input pin output assigned to XBARA_IN11 input. */ + kXbaraInputCMP0_output = 12|0x100U, /*!< CMP0 Output output assigned to XBARA_IN12 input. */ + kXbaraInputCMP1_output = 13|0x100U, /*!< CMP1 Output output assigned to XBARA_IN13 input. */ + kXbaraInputCMP2_output = 14|0x100U, /*!< CMP2 Output output assigned to XBARA_IN14 input. */ + kXbaraInputCMP3_output = 15|0x100U, /*!< CMP3 Output output assigned to XBARA_IN15 input. */ + kXbaraInputRESERVED16 = 16|0x100U, /*!< XBARA_IN16 input is reserved. */ + kXbaraInputRESERVED17 = 17|0x100U, /*!< XBARA_IN17 input is reserved. */ + kXbaraInputRESERVED18 = 18|0x100U, /*!< XBARA_IN18 input is reserved. */ + kXbaraInputRESERVED19 = 19|0x100U, /*!< XBARA_IN19 input is reserved. */ + kXbaraInputPWM0_TRG0 = 20|0x100U, /*!< PWMA channel 0 trigger 0 output assigned to XBARA_IN20 input. */ + kXbaraInputPWM0_TRG1 = 21|0x100U, /*!< PWMA channel 0 trigger 1 output assigned to XBARA_IN21 input. */ + kXbaraInputPWM1_TRG0 = 22|0x100U, /*!< PWMA channel 1 trigger 0 output assigned to XBARA_IN22 input. */ + kXbaraInputPWM1_TRG1 = 23|0x100U, /*!< PWMA channel 1 trigger 1 output assigned to XBARA_IN23 input. */ + kXbaraInputPWM2_TRG0 = 24|0x100U, /*!< PWMA channel 2 trigger 0 output assigned to XBARA_IN24 input. */ + kXbaraInputPWM2_TRG1 = 25|0x100U, /*!< PWMA channel 2 trigger 1 output assigned to XBARA_IN25 input. */ + kXbaraInputPWM3_TRG0 = 26|0x100U, /*!< PWMA channel 3 trigger 0 output assigned to XBARA_IN26 input. */ + kXbaraInputPWM3_TRG1 = 27|0x100U, /*!< PWMA channel 3 trigger 1 output assigned to XBARA_IN27 input. */ + kXbaraInputRESERVED28 = 28|0x100U, /*!< XBARA_IN28 input is reserved. */ + kXbaraInputPDB0_CH0_Output = 29|0x100U, /*!< PDB0 channel 0 output trigger output assigned to XBARA_IN29 input. */ + kXbaraInputRESERVED30 = 30|0x100U, /*!< XBARA_IN30 input is reserved. */ + kXbaraInputPDB1_CH0_Output = 31|0x100U, /*!< PDB1 channel 0 output trigger output assigned to XBARA_IN31 input. */ + kXbaraInputRESERVED32 = 32|0x100U, /*!< XBARA_IN32 input is reserved. */ + kXbaraInputADCA_ES = 33|0x100U, /*!< ADC converter A end of scan output assigned to XBARA_IN33 input. */ + kXbaraInputRESERVED34 = 34|0x100U, /*!< XBARA_IN34 input is reserved. */ + kXbaraInputADCB_ES = 35|0x100U, /*!< ADC converter B end of scan output assigned to XBARA_IN35 input. */ + kXbaraInputRESERVED36 = 36|0x100U, /*!< XBARA_IN36 input is reserved. */ + kXbaraInputRESERVED37 = 37|0x100U, /*!< XBARA_IN37 input is reserved. */ + kXbaraInputDMA_CH0_done = 38|0x100U, /*!< DMA channel 0 done output assigned to XBARA_IN38 input. */ + kXbaraInputDMA_CH1_done = 39|0x100U, /*!< DMA channel 1 done output assigned to XBARA_IN39 input. */ + kXbaraInputDMA_CH6_done = 40|0x100U, /*!< DMA channel 6 done output assigned to XBARA_IN40 input. */ + kXbaraInputDMA_CH7_done = 41|0x100U, /*!< DMA channel 7 done output assigned to XBARA_IN41 input. */ + kXbaraInputPIT_trigger_0 = 42|0x100U, /*!< PIT trigger 0 output assigned to XBARA_IN42 input. */ + kXbaraInputPIT_trigger_1 = 43|0x100U, /*!< PIT trigger 1 output assigned to XBARA_IN43 input. */ + kXbaraInputRESERVED44 = 44|0x100U, /*!< XBARA_IN44 input is reserved. */ + kXbaraInputENC_CMP_pos_match = 45|0x100U, /*!< ENC compare trigger and position match output assigned to XBARA_IN45 input. */ + kXbaraInputAND_OR_INVERT_0 = 46|0x100U, /*!< AOI output 0 output assigned to XBARA_IN46 input. */ + kXbaraInputAND_OR_INVERT_1 = 47|0x100U, /*!< AOI output 1 output assigned to XBARA_IN47 input. */ + kXbaraInputAND_OR_INVERT_2 = 48|0x100U, /*!< AOI output 2 output assigned to XBARA_IN48 input. */ + kXbaraInputAND_OR_INVERT_3 = 49|0x100U, /*!< AOI output 3 output assigned to XBARA_IN49 input. */ + kXbaraInputPIT_trigger_2 = 50|0x100U, /*!< PIT trigger 2 output assigned to XBARA_IN50 input. */ + kXbaraInputPIT_trigger_3 = 51|0x100U, /*!< PIT trigger 3 output assigned to XBARA_IN51 input. */ + kXbarbInputCMP0_output = 0|0x200U, /*!< CMP0 Output output assigned to XBARB_IN0 input. */ + kXbarbInputCMP1_output = 1|0x200U, /*!< CMP1 Output output assigned to XBARB_IN1 input. */ + kXbarbInputCMP2_output = 2|0x200U, /*!< CMP2 Output output assigned to XBARB_IN2 input. */ + kXbarbInputCMP3_output = 3|0x200U, /*!< CMP3 Output output assigned to XBARB_IN3 input. */ + kXbarbInputRESERVED4 = 4|0x200U, /*!< XBARB_IN4 input is reserved. */ + kXbarbInputRESERVED5 = 5|0x200U, /*!< XBARB_IN5 input is reserved. */ + kXbarbInputRESERVED6 = 6|0x200U, /*!< XBARB_IN6 input is reserved. */ + kXbarbInputRESERVED7 = 7|0x200U, /*!< XBARB_IN7 input is reserved. */ + kXbarbInputPWM0_TRG0_or_PWM0_TRG1 = 8|0x200U, /*!< PWMA channel 0 trigger 0 or trigger 1 output assigned to XBARB_IN8 input. */ + kXbarbInputPWM1_TRG0_or_PWM1_TRG1 = 9|0x200U, /*!< PWMA channel 1 trigger 0 or trigger 1 output assigned to XBARB_IN9 input. */ + kXbarbInputPWM2_TRG0_or_PWM2_TRG1 = 10|0x200U, /*!< PWMA channel 2 trigger 0 or trigger 1 output assigned to XBARB_IN10 input. */ + kXbarbInputPWM3_TRG0_or_PWM3_TRG1 = 11|0x200U, /*!< PWMA channel 3 trigger 0 or trigger 1 output assigned to XBARB_IN11 input. */ + kXbarbInputPDB0_CH0_Output = 12|0x200U, /*!< PDB0 channel 0 output trigger output assigned to XBARB_IN12 input. */ + kXbarbInputADCA_ES = 13|0x200U, /*!< ADC converter A end of scan output assigned to XBARB_IN13 input. */ + kXbarbInputXBARIN2 = 14|0x200U, /*!< XBARIN2 input pin output assigned to XBARB_IN14 input. */ + kXbarbInputXBARIN3 = 15|0x200U, /*!< XBARIN3 input pin output assigned to XBARB_IN15 input. */ + kXbarbInputRESERVED16 = 16|0x200U, /*!< XBARB_IN16 input is reserved. */ + kXbarbInputRESERVED17 = 17|0x200U, /*!< XBARB_IN17 input is reserved. */ + kXbarbInputDMA_CH0_done = 18|0x200U, /*!< DMA channel 0 done output assigned to XBARB_IN18 input. */ + kXbarbInputDMA_CH1_done = 19|0x200U, /*!< DMA channel 1 done output assigned to XBARB_IN19 input. */ + kXbarbInputXBARIN10 = 20|0x200U, /*!< XBARIN10 input pin output assigned to XBARB_IN20 input. */ + kXbarbInputXBARIN11 = 21|0x200U, /*!< XBARIN11 input pin output assigned to XBARB_IN21 input. */ + kXbarbInputDMA_CH6_done = 22|0x200U, /*!< DMA channel 6 done output assigned to XBARB_IN22 input. */ + kXbarbInputDMA_CH7_done = 23|0x200U, /*!< DMA channel 7 done output assigned to XBARB_IN23 input. */ + kXbarbInputPIT_trigger_0 = 24|0x200U, /*!< PIT trigger 0 output assigned to XBARB_IN24 input. */ + kXbarbInputPIT_trigger_1 = 25|0x200U, /*!< PIT trigger 1 output assigned to XBARB_IN25 input. */ + kXbarbInputPDB1_CH0_Output = 26|0x200U, /*!< PDB1 channel 0 output trigger output assigned to XBARB_IN26 input. */ + kXbarbInputADCB_ES = 27|0x200U, /*!< ADC converter B end of scan output assigned to XBARB_IN27 input. */ +#elif defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F256VLH15) + kXbaraInputVSS = 0|0x100U, /*!< Logic zero output assigned to XBARA_IN0 input. */ + kXbaraInputVDD = 1|0x100U, /*!< Logic one output assigned to XBARA_IN1 input. */ + kXbaraInputXBARIN2 = 2|0x100U, /*!< XBARIN2 input pin output assigned to XBARA_IN2 input. */ + kXbaraInputXBARIN3 = 3|0x100U, /*!< XBARIN3 input pin output assigned to XBARA_IN3 input. */ + kXbaraInputXBARIN4 = 4|0x100U, /*!< XBARIN4 input pin output assigned to XBARA_IN4 input. */ + kXbaraInputXBARIN5 = 5|0x100U, /*!< XBARIN5 input pin output assigned to XBARA_IN5 input. */ + kXbaraInputXBARIN6 = 6|0x100U, /*!< XBARIN6 input pin output assigned to XBARA_IN6 input. */ + kXbaraInputXBARIN7 = 7|0x100U, /*!< XBARIN7 input pin output assigned to XBARA_IN7 input. */ + kXbaraInputXBARIN8 = 8|0x100U, /*!< XBARIN8 input pin output assigned to XBARA_IN8 input. */ + kXbaraInputXBARIN9 = 9|0x100U, /*!< XBARIN9 input pin output assigned to XBARA_IN9 input. */ + kXbaraInputXBARIN10 = 10|0x100U, /*!< XBARIN10 input pin output assigned to XBARA_IN10 input. */ + kXbaraInputXBARIN11 = 11|0x100U, /*!< XBARIN11 input pin output assigned to XBARA_IN11 input. */ + kXbaraInputCMP0_output = 12|0x100U, /*!< CMP0 Output output assigned to XBARA_IN12 input. */ + kXbaraInputCMP1_output = 13|0x100U, /*!< CMP1 Output output assigned to XBARA_IN13 input. */ + kXbaraInputCMP2_output = 14|0x100U, /*!< CMP2 Output output assigned to XBARA_IN14 input. */ + kXbaraInputCMP3_output = 15|0x100U, /*!< CMP3 Output output assigned to XBARA_IN15 input. */ + kXbaraInputFTM0_match = 16|0x100U, /*!< FTM0 all channels output compare ORed together output assigned to XBARA_IN16 input. */ + kXbaraInputFTM0_EXTRIG = 17|0x100U, /*!< FTM0 all channels counter init ORed together output assigned to XBARA_IN17 input. */ + kXbaraInputRESERVED18 = 18|0x100U, /*!< XBARA_IN18 input is reserved. */ + kXbaraInputRESERVED19 = 19|0x100U, /*!< XBARA_IN19 input is reserved. */ + kXbaraInputPWM0_TRG0 = 20|0x100U, /*!< PWMA channel 0 trigger 0 output assigned to XBARA_IN20 input. */ + kXbaraInputPWM0_TRG1 = 21|0x100U, /*!< PWMA channel 0 trigger 1 output assigned to XBARA_IN21 input. */ + kXbaraInputPWM1_TRG0 = 22|0x100U, /*!< PWMA channel 1 trigger 0 output assigned to XBARA_IN22 input. */ + kXbaraInputPWM1_TRG1 = 23|0x100U, /*!< PWMA channel 1 trigger 1 output assigned to XBARA_IN23 input. */ + kXbaraInputPWM2_TRG0 = 24|0x100U, /*!< PWMA channel 2 trigger 0 output assigned to XBARA_IN24 input. */ + kXbaraInputPWM2_TRG1 = 25|0x100U, /*!< PWMA channel 2 trigger 1 output assigned to XBARA_IN25 input. */ + kXbaraInputPWM3_TRG0 = 26|0x100U, /*!< PWMA channel 3 trigger 0 output assigned to XBARA_IN26 input. */ + kXbaraInputPWM3_TRG1 = 27|0x100U, /*!< PWMA channel 3 trigger 1 output assigned to XBARA_IN27 input. */ + kXbaraInputRESERVED28 = 28|0x100U, /*!< XBARA_IN28 input is reserved. */ + kXbaraInputPDB0_CH0_Output = 29|0x100U, /*!< PDB0 channel 0 output trigger output assigned to XBARA_IN29 input. */ + kXbaraInputRESERVED30 = 30|0x100U, /*!< XBARA_IN30 input is reserved. */ + kXbaraInputPDB1_CH0_Output = 31|0x100U, /*!< PDB1 channel 0 output trigger output assigned to XBARA_IN31 input. */ + kXbaraInputRESERVED32 = 32|0x100U, /*!< XBARA_IN32 input is reserved. */ + kXbaraInputADCA_ES = 33|0x100U, /*!< ADC converter A end of scan output assigned to XBARA_IN33 input. */ + kXbaraInputRESERVED34 = 34|0x100U, /*!< XBARA_IN34 input is reserved. */ + kXbaraInputADCB_ES = 35|0x100U, /*!< ADC converter B end of scan output assigned to XBARA_IN35 input. */ + kXbaraInputFTM1_match = 36|0x100U, /*!< FTM1 all channels output compare ORed together output assigned to XBARA_IN36 input. */ + kXbaraInputFTM1_EXTRIG = 37|0x100U, /*!< FTM1 all channels counter init ORed together output assigned to XBARA_IN37 input. */ + kXbaraInputDMA_CH0_done = 38|0x100U, /*!< DMA channel 0 done output assigned to XBARA_IN38 input. */ + kXbaraInputDMA_CH1_done = 39|0x100U, /*!< DMA channel 1 done output assigned to XBARA_IN39 input. */ + kXbaraInputDMA_CH6_done = 40|0x100U, /*!< DMA channel 6 done output assigned to XBARA_IN40 input. */ + kXbaraInputDMA_CH7_done = 41|0x100U, /*!< DMA channel 7 done output assigned to XBARA_IN41 input. */ + kXbaraInputPIT_trigger_0 = 42|0x100U, /*!< PIT trigger 0 output assigned to XBARA_IN42 input. */ + kXbaraInputPIT_trigger_1 = 43|0x100U, /*!< PIT trigger 1 output assigned to XBARA_IN43 input. */ + kXbaraInputRESERVED44 = 44|0x100U, /*!< XBARA_IN44 input is reserved. */ + kXbaraInputENC_CMP_pos_match = 45|0x100U, /*!< ENC compare trigger and position match output assigned to XBARA_IN45 input. */ + kXbaraInputAND_OR_INVERT_0 = 46|0x100U, /*!< AOI output 0 output assigned to XBARA_IN46 input. */ + kXbaraInputAND_OR_INVERT_1 = 47|0x100U, /*!< AOI output 1 output assigned to XBARA_IN47 input. */ + kXbaraInputAND_OR_INVERT_2 = 48|0x100U, /*!< AOI output 2 output assigned to XBARA_IN48 input. */ + kXbaraInputAND_OR_INVERT_3 = 49|0x100U, /*!< AOI output 3 output assigned to XBARA_IN49 input. */ + kXbaraInputPIT_trigger_2 = 50|0x100U, /*!< PIT trigger 2 output assigned to XBARA_IN50 input. */ + kXbaraInputPIT_trigger_3 = 51|0x100U, /*!< PIT trigger 3 output assigned to XBARA_IN51 input. */ + kXbarbInputCMP0_output = 0|0x200U, /*!< CMP0 Output output assigned to XBARB_IN0 input. */ + kXbarbInputCMP1_output = 1|0x200U, /*!< CMP1 Output output assigned to XBARB_IN1 input. */ + kXbarbInputCMP2_output = 2|0x200U, /*!< CMP2 Output output assigned to XBARB_IN2 input. */ + kXbarbInputCMP3_output = 3|0x200U, /*!< CMP3 Output output assigned to XBARB_IN3 input. */ + kXbarbInputFTM0_match = 4|0x200U, /*!< FTM0 all channels output compare ORed together output assigned to XBARB_IN4 input. */ + kXbarbInputFTM0_EXTRIG = 5|0x200U, /*!< FTM0 all channels counter init ORed together output assigned to XBARB_IN5 input. */ + kXbarbInputRESERVED6 = 6|0x200U, /*!< XBARB_IN6 input is reserved. */ + kXbarbInputRESERVED7 = 7|0x200U, /*!< XBARB_IN7 input is reserved. */ + kXbarbInputPWM0_TRG0_or_PWM0_TRG1 = 8|0x200U, /*!< PWMA channel 0 trigger 0 or trigger 1 output assigned to XBARB_IN8 input. */ + kXbarbInputPWM1_TRG0_or_PWM1_TRG1 = 9|0x200U, /*!< PWMA channel 1 trigger 0 or trigger 1 output assigned to XBARB_IN9 input. */ + kXbarbInputPWM2_TRG0_or_PWM2_TRG1 = 10|0x200U, /*!< PWMA channel 2 trigger 0 or trigger 1 output assigned to XBARB_IN10 input. */ + kXbarbInputPWM3_TRG0_or_PWM3_TRG1 = 11|0x200U, /*!< PWMA channel 3 trigger 0 or trigger 1 output assigned to XBARB_IN11 input. */ + kXbarbInputPDB0_CH0_Output = 12|0x200U, /*!< PDB0 channel 0 output trigger output assigned to XBARB_IN12 input. */ + kXbarbInputADCA_ES = 13|0x200U, /*!< ADC converter A end of scan output assigned to XBARB_IN13 input. */ + kXbarbInputXBARIN2 = 14|0x200U, /*!< XBARIN2 input pin output assigned to XBARB_IN14 input. */ + kXbarbInputXBARIN3 = 15|0x200U, /*!< XBARIN3 input pin output assigned to XBARB_IN15 input. */ + kXbarbInputFTM1_match = 16|0x200U, /*!< FTM1 all channels output compare ORed together output assigned to XBARB_IN16 input. */ + kXbarbInputFTM1_EXTRIG = 17|0x200U, /*!< FTM1 all channels counter init ORed together output assigned to XBARB_IN17 input. */ + kXbarbInputDMA_CH0_done = 18|0x200U, /*!< DMA channel 0 done output assigned to XBARB_IN18 input. */ + kXbarbInputDMA_CH1_done = 19|0x200U, /*!< DMA channel 1 done output assigned to XBARB_IN19 input. */ + kXbarbInputXBARIN10 = 20|0x200U, /*!< XBARIN10 input pin output assigned to XBARB_IN20 input. */ + kXbarbInputXBARIN11 = 21|0x200U, /*!< XBARIN11 input pin output assigned to XBARB_IN21 input. */ + kXbarbInputDMA_CH6_done = 22|0x200U, /*!< DMA channel 6 done output assigned to XBARB_IN22 input. */ + kXbarbInputDMA_CH7_done = 23|0x200U, /*!< DMA channel 7 done output assigned to XBARB_IN23 input. */ + kXbarbInputPIT_trigger_0 = 24|0x200U, /*!< PIT trigger 0 output assigned to XBARB_IN24 input. */ + kXbarbInputPIT_trigger_1 = 25|0x200U, /*!< PIT trigger 1 output assigned to XBARB_IN25 input. */ + kXbarbInputPDB1_CH0_Output = 26|0x200U, /*!< PDB1 channel 0 output trigger output assigned to XBARB_IN26 input. */ + kXbarbInputADCB_ES = 27|0x200U, /*!< ADC converter B end of scan output assigned to XBARB_IN27 input. */ +#elif defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLL15) + kXbaraInputVSS = 0|0x100U, /*!< Logic zero output assigned to XBARA_IN0 input. */ + kXbaraInputVDD = 1|0x100U, /*!< Logic one output assigned to XBARA_IN1 input. */ + kXbaraInputXBARIN2 = 2|0x100U, /*!< XBARIN2 input pin output assigned to XBARA_IN2 input. */ + kXbaraInputXBARIN3 = 3|0x100U, /*!< XBARIN3 input pin output assigned to XBARA_IN3 input. */ + kXbaraInputXBARIN4 = 4|0x100U, /*!< XBARIN4 input pin output assigned to XBARA_IN4 input. */ + kXbaraInputXBARIN5 = 5|0x100U, /*!< XBARIN5 input pin output assigned to XBARA_IN5 input. */ + kXbaraInputXBARIN6 = 6|0x100U, /*!< XBARIN6 input pin output assigned to XBARA_IN6 input. */ + kXbaraInputXBARIN7 = 7|0x100U, /*!< XBARIN7 input pin output assigned to XBARA_IN7 input. */ + kXbaraInputXBARIN8 = 8|0x100U, /*!< XBARIN8 input pin output assigned to XBARA_IN8 input. */ + kXbaraInputXBARIN9 = 9|0x100U, /*!< XBARIN9 input pin output assigned to XBARA_IN9 input. */ + kXbaraInputXBARIN10 = 10|0x100U, /*!< XBARIN10 input pin output assigned to XBARA_IN10 input. */ + kXbaraInputXBARIN11 = 11|0x100U, /*!< XBARIN11 input pin output assigned to XBARA_IN11 input. */ + kXbaraInputCMP0_output = 12|0x100U, /*!< CMP0 Output output assigned to XBARA_IN12 input. */ + kXbaraInputCMP1_output = 13|0x100U, /*!< CMP1 Output output assigned to XBARA_IN13 input. */ + kXbaraInputCMP2_output = 14|0x100U, /*!< CMP2 Output output assigned to XBARA_IN14 input. */ + kXbaraInputCMP3_output = 15|0x100U, /*!< CMP3 Output output assigned to XBARA_IN15 input. */ + kXbaraInputFTM0_match = 16|0x100U, /*!< FTM0 all channels output compare ORed together output assigned to XBARA_IN16 input. */ + kXbaraInputFTM0_EXTRIG = 17|0x100U, /*!< FTM0 all channels counter init ORed together output assigned to XBARA_IN17 input. */ + kXbaraInputFTM3_match = 18|0x100U, /*!< FTM3 all channels output compare ORed together output assigned to XBARA_IN18 input. */ + kXbaraInputFTM3_EXTRIG = 19|0x100U, /*!< FTM3 all channels counter init ORed together output assigned to XBARA_IN19 input. */ + kXbaraInputPWM0_TRG0 = 20|0x100U, /*!< PWMA channel 0 trigger 0 output assigned to XBARA_IN20 input. */ + kXbaraInputPWM0_TRG1 = 21|0x100U, /*!< PWMA channel 0 trigger 1 output assigned to XBARA_IN21 input. */ + kXbaraInputPWM1_TRG0 = 22|0x100U, /*!< PWMA channel 1 trigger 0 output assigned to XBARA_IN22 input. */ + kXbaraInputPWM1_TRG1 = 23|0x100U, /*!< PWMA channel 1 trigger 1 output assigned to XBARA_IN23 input. */ + kXbaraInputPWM2_TRG0 = 24|0x100U, /*!< PWMA channel 2 trigger 0 output assigned to XBARA_IN24 input. */ + kXbaraInputPWM2_TRG1 = 25|0x100U, /*!< PWMA channel 2 trigger 1 output assigned to XBARA_IN25 input. */ + kXbaraInputPWM3_TRG0 = 26|0x100U, /*!< PWMA channel 3 trigger 0 output assigned to XBARA_IN26 input. */ + kXbaraInputPWM3_TRG1 = 27|0x100U, /*!< PWMA channel 3 trigger 1 output assigned to XBARA_IN27 input. */ + kXbaraInputRESERVED28 = 28|0x100U, /*!< XBARA_IN28 input is reserved. */ + kXbaraInputPDB0_CH0_Output = 29|0x100U, /*!< PDB0 channel 0 output trigger output assigned to XBARA_IN29 input. */ + kXbaraInputRESERVED30 = 30|0x100U, /*!< XBARA_IN30 input is reserved. */ + kXbaraInputPDB1_CH0_Output = 31|0x100U, /*!< PDB1 channel 0 output trigger output assigned to XBARA_IN31 input. */ + kXbaraInputRESERVED32 = 32|0x100U, /*!< XBARA_IN32 input is reserved. */ + kXbaraInputADCA_ES = 33|0x100U, /*!< ADC converter A end of scan output assigned to XBARA_IN33 input. */ + kXbaraInputRESERVED34 = 34|0x100U, /*!< XBARA_IN34 input is reserved. */ + kXbaraInputADCB_ES = 35|0x100U, /*!< ADC converter B end of scan output assigned to XBARA_IN35 input. */ + kXbaraInputFTM1_match = 36|0x100U, /*!< FTM1 all channels output compare ORed together output assigned to XBARA_IN36 input. */ + kXbaraInputFTM1_EXTRIG = 37|0x100U, /*!< FTM1 all channels counter init ORed together output assigned to XBARA_IN37 input. */ + kXbaraInputDMA_CH0_done = 38|0x100U, /*!< DMA channel 0 done output assigned to XBARA_IN38 input. */ + kXbaraInputDMA_CH1_done = 39|0x100U, /*!< DMA channel 1 done output assigned to XBARA_IN39 input. */ + kXbaraInputDMA_CH6_done = 40|0x100U, /*!< DMA channel 6 done output assigned to XBARA_IN40 input. */ + kXbaraInputDMA_CH7_done = 41|0x100U, /*!< DMA channel 7 done output assigned to XBARA_IN41 input. */ + kXbaraInputPIT_trigger_0 = 42|0x100U, /*!< PIT trigger 0 output assigned to XBARA_IN42 input. */ + kXbaraInputPIT_trigger_1 = 43|0x100U, /*!< PIT trigger 1 output assigned to XBARA_IN43 input. */ + kXbaraInputRESERVED44 = 44|0x100U, /*!< XBARA_IN44 input is reserved. */ + kXbaraInputENC_CMP_pos_match = 45|0x100U, /*!< ENC compare trigger and position match output assigned to XBARA_IN45 input. */ + kXbaraInputAND_OR_INVERT_0 = 46|0x100U, /*!< AOI output 0 output assigned to XBARA_IN46 input. */ + kXbaraInputAND_OR_INVERT_1 = 47|0x100U, /*!< AOI output 1 output assigned to XBARA_IN47 input. */ + kXbaraInputAND_OR_INVERT_2 = 48|0x100U, /*!< AOI output 2 output assigned to XBARA_IN48 input. */ + kXbaraInputAND_OR_INVERT_3 = 49|0x100U, /*!< AOI output 3 output assigned to XBARA_IN49 input. */ + kXbaraInputPIT_trigger_2 = 50|0x100U, /*!< PIT trigger 2 output assigned to XBARA_IN50 input. */ + kXbaraInputPIT_trigger_3 = 51|0x100U, /*!< PIT trigger 3 output assigned to XBARA_IN51 input. */ + kXbarbInputCMP0_output = 0|0x200U, /*!< CMP0 Output output assigned to XBARB_IN0 input. */ + kXbarbInputCMP1_output = 1|0x200U, /*!< CMP1 Output output assigned to XBARB_IN1 input. */ + kXbarbInputCMP2_output = 2|0x200U, /*!< CMP2 Output output assigned to XBARB_IN2 input. */ + kXbarbInputCMP3_output = 3|0x200U, /*!< CMP3 Output output assigned to XBARB_IN3 input. */ + kXbarbInputFTM0_match = 4|0x200U, /*!< FTM0 all channels output compare ORed together output assigned to XBARB_IN4 input. */ + kXbarbInputFTM0_EXTRIG = 5|0x200U, /*!< FTM0 all channels counter init ORed together output assigned to XBARB_IN5 input. */ + kXbarbInputFTM3_match = 6|0x200U, /*!< FTM3 all channels output compare ORed together output assigned to XBARB_IN6 input. */ + kXbarbInputFTM3_EXTRIG = 7|0x200U, /*!< FTM3 all channels counter init ORed together output assigned to XBARB_IN7 input. */ + kXbarbInputPWM0_TRG0_or_PWM0_TRG1 = 8|0x200U, /*!< PWMA channel 0 trigger 0 or trigger 1 output assigned to XBARB_IN8 input. */ + kXbarbInputPWM1_TRG0_or_PWM1_TRG1 = 9|0x200U, /*!< PWMA channel 1 trigger 0 or trigger 1 output assigned to XBARB_IN9 input. */ + kXbarbInputPWM2_TRG0_or_PWM2_TRG1 = 10|0x200U, /*!< PWMA channel 2 trigger 0 or trigger 1 output assigned to XBARB_IN10 input. */ + kXbarbInputPWM3_TRG0_or_PWM3_TRG1 = 11|0x200U, /*!< PWMA channel 3 trigger 0 or trigger 1 output assigned to XBARB_IN11 input. */ + kXbarbInputPDB0_CH0_Output = 12|0x200U, /*!< PDB0 channel 0 output trigger output assigned to XBARB_IN12 input. */ + kXbarbInputADCA_ES = 13|0x200U, /*!< ADC converter A end of scan output assigned to XBARB_IN13 input. */ + kXbarbInputXBARIN2 = 14|0x200U, /*!< XBARIN2 input pin output assigned to XBARB_IN14 input. */ + kXbarbInputXBARIN3 = 15|0x200U, /*!< XBARIN3 input pin output assigned to XBARB_IN15 input. */ + kXbarbInputFTM1_match = 16|0x200U, /*!< FTM1 all channels output compare ORed together output assigned to XBARB_IN16 input. */ + kXbarbInputFTM1_EXTRIG = 17|0x200U, /*!< FTM1 all channels counter init ORed together output assigned to XBARB_IN17 input. */ + kXbarbInputDMA_CH0_done = 18|0x200U, /*!< DMA channel 0 done output assigned to XBARB_IN18 input. */ + kXbarbInputDMA_CH1_done = 19|0x200U, /*!< DMA channel 1 done output assigned to XBARB_IN19 input. */ + kXbarbInputXBARIN10 = 20|0x200U, /*!< XBARIN10 input pin output assigned to XBARB_IN20 input. */ + kXbarbInputXBARIN11 = 21|0x200U, /*!< XBARIN11 input pin output assigned to XBARB_IN21 input. */ + kXbarbInputDMA_CH6_done = 22|0x200U, /*!< DMA channel 6 done output assigned to XBARB_IN22 input. */ + kXbarbInputDMA_CH7_done = 23|0x200U, /*!< DMA channel 7 done output assigned to XBARB_IN23 input. */ + kXbarbInputPIT_trigger_0 = 24|0x200U, /*!< PIT trigger 0 output assigned to XBARB_IN24 input. */ + kXbarbInputPIT_trigger_1 = 25|0x200U, /*!< PIT trigger 1 output assigned to XBARB_IN25 input. */ + kXbarbInputPDB1_CH0_Output = 26|0x200U, /*!< PDB1 channel 0 output trigger output assigned to XBARB_IN26 input. */ + kXbarbInputADCB_ES = 27|0x200U, /*!< ADC converter B end of scan output assigned to XBARB_IN27 input. */ +#else + #error "No valid CPU defined!" +#endif +} xbar_input_signal_t; + +typedef enum _xbar_output_signal { +#if defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F64VLH15) + kXbaraOutputDMAMUX18 = 0|0x100U, /*!< XBARA_OUT0 output assigned to DMAMUX slot 18 */ + kXbaraOutputDMAMUX19 = 1|0x100U, /*!< XBARA_OUT1 output assigned to DMAMUX slot 19 */ + kXbaraOutputDMAMUX20 = 2|0x100U, /*!< XBARA_OUT2 output assigned to DMAMUX slot 20 */ + kXbaraOutputDMAMUX21 = 3|0x100U, /*!< XBARA_OUT3 output assigned to DMAMUX slot 21 */ + kXbaraOutputXB_OUT4 = 4|0x100U, /*!< XBARA_OUT4 output assigned to XBAROUT4 output pin */ + kXbaraOutputXB_OUT5 = 5|0x100U, /*!< XBARA_OUT5 output assigned to XBAROUT5 output pin */ + kXbaraOutputXB_OUT6 = 6|0x100U, /*!< XBARA_OUT6 output assigned to XBAROUT6 output pin */ + kXbaraOutputXB_OUT7 = 7|0x100U, /*!< XBARA_OUT7 output assigned to XBAROUT7 output pin */ + kXbaraOutputXB_OUT8 = 8|0x100U, /*!< XBARA_OUT8 output assigned to XBAROUT8 output pin */ + kXbaraOutputXB_OUT9 = 9|0x100U, /*!< XBARA_OUT9 output assigned to XBAROUT9 output pin */ + kXbaraOutputXB_OUT10 = 10|0x100U, /*!< XBARA_OUT10 output assigned to XBAROUT10 output pin */ + kXbaraOutputXB_OUT11 = 11|0x100U, /*!< XBARA_OUT11 output assigned to XBAROUT11 output pin */ + kXbaraOutputADCA_TRIG = 12|0x100U, /*!< XBARA_OUT12 output assigned to ADC converter A trigger */ + kXbaraOutputADCB_TRIG = 13|0x100U, /*!< XBARA_OUT13 output assigned to ADC converter B trigger */ + kXbaraOutputRESERVED14 = 14|0x100U, /*!< XBARA_OUT14 output is reserved. */ + kXbaraOutputRESERVED15 = 15|0x100U, /*!< XBARA_OUT15 output is reserved. */ + kXbaraOutputCMP0 = 16|0x100U, /*!< XBARA_OUT16 output assigned to CMP0 window/sample */ + kXbaraOutputCMP1 = 17|0x100U, /*!< XBARA_OUT17 output assigned to CMP1 window/sample */ + kXbaraOutputCMP2 = 18|0x100U, /*!< XBARA_OUT18 output assigned to CMP2 window/sample */ + kXbaraOutputCMP3 = 19|0x100U, /*!< XBARA_OUT19 output assigned to CMP3 window/sample */ + kXbaraOutputRESERVED20 = 20|0x100U, /*!< XBARA_OUT20 output is reserved. */ + kXbaraOutputRESERVED21 = 21|0x100U, /*!< XBARA_OUT21 output is reserved. */ + kXbaraOutputRESERVED22 = 22|0x100U, /*!< XBARA_OUT22 output is reserved. */ + kXbaraOutputRESERVED23 = 23|0x100U, /*!< XBARA_OUT23 output is reserved. */ + kXbaraOutputRESERVED24 = 24|0x100U, /*!< XBARA_OUT24 output is reserved. */ + kXbaraOutputRESERVED25 = 25|0x100U, /*!< XBARA_OUT25 output is reserved. */ + kXbaraOutputRESERVED26 = 26|0x100U, /*!< XBARA_OUT26 output is reserved. */ + kXbaraOutputRESERVED27 = 27|0x100U, /*!< XBARA_OUT27 output is reserved. */ + kXbaraOutputRESERVED28 = 28|0x100U, /*!< XBARA_OUT28 output is reserved. */ + kXbaraOutputRESERVED29 = 29|0x100U, /*!< XBARA_OUT29 output is reserved. */ + kXbaraOutputRESERVED30 = 30|0x100U, /*!< XBARA_OUT30 output is reserved. */ + kXbaraOutputRESERVED31 = 31|0x100U, /*!< XBARA_OUT31 output is reserved. */ + kXbaraOutputRESERVED32 = 32|0x100U, /*!< XBARA_OUT32 output is reserved. */ + kXbaraOutputRESERVED33 = 33|0x100U, /*!< XBARA_OUT33 output is reserved. */ + kXbaraOutputFTM0_TRIG2 = 34|0x100U, /*!< XBARA_OUT34 output assigned to FTM0 hardware trigger 2 */ + kXbaraOutputFTM1_TRIG2 = 35|0x100U, /*!< XBARA_OUT35 output assigned to FTM1 hardware trigger 2 */ + kXbaraOutputRESERVED36 = 36|0x100U, /*!< XBARA_OUT36 output is reserved. */ + kXbaraOutputRESERVED37 = 37|0x100U, /*!< XBARA_OUT37 output is reserved. */ + kXbaraOutputPDB0_IN_CH_12 = 38|0x100U, /*!< XBARA_OUT38 output assigned to PDB0 trigger option 12 */ + kXbaraOutputRESERVED39 = 39|0x100U, /*!< XBARA_OUT39 output is reserved. */ + kXbaraOutputRESERVED40 = 40|0x100U, /*!< XBARA_OUT40 output is reserved. */ + kXbaraOutputPDB1_IN_CH_12 = 41|0x100U, /*!< XBARA_OUT41 output assigned to PDB1 trigger option 12 */ + kXbaraOutputSIM_XOR_FTM1_CH1_FTM1_CH2 = 42|0x100U, /*!< XBARA_OUT42 output assigned to SIM XOR of FTM1_CH1 and FTM1_CH0 pins and XBARA output 42 */ + kXbaraOutputRESERVED43 = 43|0x100U, /*!< XBARA_OUT43 output is reserved. */ + kXbaraOutputENC_PHA = 44|0x100U, /*!< XBARA_OUT44 output assigned to ENC quadrature waveform phase A */ + kXbaraOutputENC_PHB = 45|0x100U, /*!< XBARA_OUT45 output assigned to ENC quadrature waveform phase B */ + kXbaraOutputENC_INDEX = 46|0x100U, /*!< XBARA_OUT46 output assigned to ENC refresh/reload */ + kXbaraOutputENC_HOME = 47|0x100U, /*!< XBARA_OUT47 output assigned to ENC home position */ + kXbaraOutputENC_CAP_Trigger = 48|0x100U, /*!< XBARA_OUT48 output assigned to ENC clear/snapshot */ + kXbaraOutputFTM0_FAULT3 = 49|0x100U, /*!< XBARA_OUT49 output assigned to FTM0 fault 3 */ + kXbaraOutputFTM1_FAULT1 = 50|0x100U, /*!< XBARA_OUT50 output assigned to FTM1 fault 1 */ + kXbaraOutputRESERVED51 = 51|0x100U, /*!< XBARA_OUT51 output is reserved. */ + kXbaraOutputRESERVED52 = 52|0x100U, /*!< XBARA_OUT52 output is reserved. */ + kXbaraOutputRESERVED53 = 53|0x100U, /*!< XBARA_OUT53 output is reserved. */ + kXbaraOutputRESERVED54 = 54|0x100U, /*!< XBARA_OUT54 output is reserved. */ + kXbaraOutputRESERVED55 = 55|0x100U, /*!< XBARA_OUT55 output is reserved. */ + kXbaraOutputRESERVED56 = 56|0x100U, /*!< XBARA_OUT56 output is reserved. */ + kXbaraOutputRESERVED57 = 57|0x100U, /*!< XBARA_OUT57 output is reserved. */ + kXbaraOutputEWM_IN = 58|0x100U, /*!< XBARA_OUT58 output assigned to EWM input */ + kXbarbOutputAOI_IN0 = 0|0x200U, /*!< XBARB_OUT0 output assigned to AOI input0 */ + kXbarbOutputAOI_IN1 = 1|0x200U, /*!< XBARB_OUT1 output assigned to AOI input1 */ + kXbarbOutputAOI_IN2 = 2|0x200U, /*!< XBARB_OUT2 output assigned to AOI input2 */ + kXbarbOutputAOI_IN3 = 3|0x200U, /*!< XBARB_OUT3 output assigned to AOI input3 */ + kXbarbOutputAOI_IN4 = 4|0x200U, /*!< XBARB_OUT4 output assigned to AOI input4 */ + kXbarbOutputAOI_IN5 = 5|0x200U, /*!< XBARB_OUT5 output assigned to AOI input5 */ + kXbarbOutputAOI_IN6 = 6|0x200U, /*!< XBARB_OUT6 output assigned to AOI input6 */ + kXbarbOutputAOI_IN7 = 7|0x200U, /*!< XBARB_OUT7 output assigned to AOI input7 */ + kXbarbOutputAOI_IN8 = 8|0x200U, /*!< XBARB_OUT8 output assigned to AOI input8 */ + kXbarbOutputAOI_IN9 = 9|0x200U, /*!< XBARB_OUT9 output assigned to AOI input9 */ + kXbarbOutputAOI_IN10 = 10|0x200U, /*!< XBARB_OUT10 output assigned to AOI input10 */ + kXbarbOutputAOI_IN11 = 11|0x200U, /*!< XBARB_OUT11 output assigned to AOI input11 */ + kXbarbOutputAOI_IN12 = 12|0x200U, /*!< XBARB_OUT12 output assigned to AOI input12 */ + kXbarbOutputAOI_IN13 = 13|0x200U, /*!< XBARB_OUT13 output assigned to AOI input13 */ + kXbarbOutputAOI_IN14 = 14|0x200U, /*!< XBARB_OUT14 output assigned to AOI input14 */ + kXbarbOutputAOI_IN15 = 15|0x200U, /*!< XBARB_OUT15 output assigned to AOI input15 */ +#elif defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLL15) + kXbaraOutputDMAMUX18 = 0|0x100U, /*!< XBARA_OUT0 output assigned to DMAMUX slot 18 */ + kXbaraOutputDMAMUX19 = 1|0x100U, /*!< XBARA_OUT1 output assigned to DMAMUX slot 19 */ + kXbaraOutputDMAMUX20 = 2|0x100U, /*!< XBARA_OUT2 output assigned to DMAMUX slot 20 */ + kXbaraOutputDMAMUX21 = 3|0x100U, /*!< XBARA_OUT3 output assigned to DMAMUX slot 21 */ + kXbaraOutputXB_OUT4 = 4|0x100U, /*!< XBARA_OUT4 output assigned to XBAROUT4 output pin */ + kXbaraOutputXB_OUT5 = 5|0x100U, /*!< XBARA_OUT5 output assigned to XBAROUT5 output pin */ + kXbaraOutputXB_OUT6 = 6|0x100U, /*!< XBARA_OUT6 output assigned to XBAROUT6 output pin */ + kXbaraOutputXB_OUT7 = 7|0x100U, /*!< XBARA_OUT7 output assigned to XBAROUT7 output pin */ + kXbaraOutputXB_OUT8 = 8|0x100U, /*!< XBARA_OUT8 output assigned to XBAROUT8 output pin */ + kXbaraOutputXB_OUT9 = 9|0x100U, /*!< XBARA_OUT9 output assigned to XBAROUT9 output pin */ + kXbaraOutputXB_OUT10 = 10|0x100U, /*!< XBARA_OUT10 output assigned to XBAROUT10 output pin */ + kXbaraOutputXB_OUT11 = 11|0x100U, /*!< XBARA_OUT11 output assigned to XBAROUT11 output pin */ + kXbaraOutputADCA_TRIG = 12|0x100U, /*!< XBARA_OUT12 output assigned to ADC converter A trigger */ + kXbaraOutputADCB_TRIG = 13|0x100U, /*!< XBARA_OUT13 output assigned to ADC converter B trigger */ + kXbaraOutputRESERVED14 = 14|0x100U, /*!< XBARA_OUT14 output is reserved. */ + kXbaraOutputRESERVED15 = 15|0x100U, /*!< XBARA_OUT15 output is reserved. */ + kXbaraOutputCMP0 = 16|0x100U, /*!< XBARA_OUT16 output assigned to CMP0 window/sample */ + kXbaraOutputCMP1 = 17|0x100U, /*!< XBARA_OUT17 output assigned to CMP1 window/sample */ + kXbaraOutputCMP2 = 18|0x100U, /*!< XBARA_OUT18 output assigned to CMP2 window/sample */ + kXbaraOutputCMP3 = 19|0x100U, /*!< XBARA_OUT19 output assigned to CMP3 window/sample */ + kXbaraOutputRESERVED20 = 20|0x100U, /*!< XBARA_OUT20 output is reserved. */ + kXbaraOutputRESERVED21 = 21|0x100U, /*!< XBARA_OUT21 output is reserved. */ + kXbaraOutputRESERVED22 = 22|0x100U, /*!< XBARA_OUT22 output is reserved. */ + kXbaraOutputRESERVED23 = 23|0x100U, /*!< XBARA_OUT23 output is reserved. */ + kXbaraOutputRESERVED24 = 24|0x100U, /*!< XBARA_OUT24 output is reserved. */ + kXbaraOutputRESERVED25 = 25|0x100U, /*!< XBARA_OUT25 output is reserved. */ + kXbaraOutputRESERVED26 = 26|0x100U, /*!< XBARA_OUT26 output is reserved. */ + kXbaraOutputRESERVED27 = 27|0x100U, /*!< XBARA_OUT27 output is reserved. */ + kXbaraOutputRESERVED28 = 28|0x100U, /*!< XBARA_OUT28 output is reserved. */ + kXbaraOutputRESERVED29 = 29|0x100U, /*!< XBARA_OUT29 output is reserved. */ + kXbaraOutputRESERVED30 = 30|0x100U, /*!< XBARA_OUT30 output is reserved. */ + kXbaraOutputRESERVED31 = 31|0x100U, /*!< XBARA_OUT31 output is reserved. */ + kXbaraOutputRESERVED32 = 32|0x100U, /*!< XBARA_OUT32 output is reserved. */ + kXbaraOutputRESERVED33 = 33|0x100U, /*!< XBARA_OUT33 output is reserved. */ + kXbaraOutputFTM0_TRIG2 = 34|0x100U, /*!< XBARA_OUT34 output assigned to FTM0 hardware trigger 2 */ + kXbaraOutputFTM1_TRIG2 = 35|0x100U, /*!< XBARA_OUT35 output assigned to FTM1 hardware trigger 2 */ + kXbaraOutputRESERVED36 = 36|0x100U, /*!< XBARA_OUT36 output is reserved. */ + kXbaraOutputFTM3_TRIG2 = 37|0x100U, /*!< XBARA_OUT37 output assigned to FTM3 hardware trigger 2 */ + kXbaraOutputPDB0_IN_CH_12 = 38|0x100U, /*!< XBARA_OUT38 output assigned to PDB0 trigger option 12 */ + kXbaraOutputRESERVED39 = 39|0x100U, /*!< XBARA_OUT39 output is reserved. */ + kXbaraOutputRESERVED40 = 40|0x100U, /*!< XBARA_OUT40 output is reserved. */ + kXbaraOutputPDB1_IN_CH_12 = 41|0x100U, /*!< XBARA_OUT41 output assigned to PDB1 trigger option 12 */ + kXbaraOutputSIM_XOR_FTM1_CH1_FTM1_CH2 = 42|0x100U, /*!< XBARA_OUT42 output assigned to SIM XOR of FTM1_CH1 and FTM1_CH0 pins and XBARA output 42 */ + kXbaraOutputRESERVED43 = 43|0x100U, /*!< XBARA_OUT43 output is reserved. */ + kXbaraOutputENC_PHA = 44|0x100U, /*!< XBARA_OUT44 output assigned to ENC quadrature waveform phase A */ + kXbaraOutputENC_PHB = 45|0x100U, /*!< XBARA_OUT45 output assigned to ENC quadrature waveform phase B */ + kXbaraOutputENC_INDEX = 46|0x100U, /*!< XBARA_OUT46 output assigned to ENC refresh/reload */ + kXbaraOutputENC_HOME = 47|0x100U, /*!< XBARA_OUT47 output assigned to ENC home position */ + kXbaraOutputENC_CAP_Trigger = 48|0x100U, /*!< XBARA_OUT48 output assigned to ENC clear/snapshot */ + kXbaraOutputFTM0_FAULT3 = 49|0x100U, /*!< XBARA_OUT49 output assigned to FTM0 fault 3 */ + kXbaraOutputFTM1_FAULT1 = 50|0x100U, /*!< XBARA_OUT50 output assigned to FTM1 fault 1 */ + kXbaraOutputRESERVED51 = 51|0x100U, /*!< XBARA_OUT51 output is reserved. */ + kXbaraOutputFTM3_FAULT3 = 52|0x100U, /*!< XBARA_OUT52 output assigned to FTM3 fault 3 */ + kXbaraOutputRESERVED53 = 53|0x100U, /*!< XBARA_OUT53 output is reserved. */ + kXbaraOutputRESERVED54 = 54|0x100U, /*!< XBARA_OUT54 output is reserved. */ + kXbaraOutputRESERVED55 = 55|0x100U, /*!< XBARA_OUT55 output is reserved. */ + kXbaraOutputRESERVED56 = 56|0x100U, /*!< XBARA_OUT56 output is reserved. */ + kXbaraOutputRESERVED57 = 57|0x100U, /*!< XBARA_OUT57 output is reserved. */ + kXbaraOutputEWM_IN = 58|0x100U, /*!< XBARA_OUT58 output assigned to EWM input */ + kXbarbOutputAOI_IN0 = 0|0x200U, /*!< XBARB_OUT0 output assigned to AOI input0 */ + kXbarbOutputAOI_IN1 = 1|0x200U, /*!< XBARB_OUT1 output assigned to AOI input1 */ + kXbarbOutputAOI_IN2 = 2|0x200U, /*!< XBARB_OUT2 output assigned to AOI input2 */ + kXbarbOutputAOI_IN3 = 3|0x200U, /*!< XBARB_OUT3 output assigned to AOI input3 */ + kXbarbOutputAOI_IN4 = 4|0x200U, /*!< XBARB_OUT4 output assigned to AOI input4 */ + kXbarbOutputAOI_IN5 = 5|0x200U, /*!< XBARB_OUT5 output assigned to AOI input5 */ + kXbarbOutputAOI_IN6 = 6|0x200U, /*!< XBARB_OUT6 output assigned to AOI input6 */ + kXbarbOutputAOI_IN7 = 7|0x200U, /*!< XBARB_OUT7 output assigned to AOI input7 */ + kXbarbOutputAOI_IN8 = 8|0x200U, /*!< XBARB_OUT8 output assigned to AOI input8 */ + kXbarbOutputAOI_IN9 = 9|0x200U, /*!< XBARB_OUT9 output assigned to AOI input9 */ + kXbarbOutputAOI_IN10 = 10|0x200U, /*!< XBARB_OUT10 output assigned to AOI input10 */ + kXbarbOutputAOI_IN11 = 11|0x200U, /*!< XBARB_OUT11 output assigned to AOI input11 */ + kXbarbOutputAOI_IN12 = 12|0x200U, /*!< XBARB_OUT12 output assigned to AOI input12 */ + kXbarbOutputAOI_IN13 = 13|0x200U, /*!< XBARB_OUT13 output assigned to AOI input13 */ + kXbarbOutputAOI_IN14 = 14|0x200U, /*!< XBARB_OUT14 output assigned to AOI input14 */ + kXbarbOutputAOI_IN15 = 15|0x200U, /*!< XBARB_OUT15 output assigned to AOI input15 */ +#elif defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) + kXbaraOutputDMAMUX18 = 0|0x100U, /*!< XBARA_OUT0 output assigned to DMAMUX slot 18 */ + kXbaraOutputDMAMUX19 = 1|0x100U, /*!< XBARA_OUT1 output assigned to DMAMUX slot 19 */ + kXbaraOutputDMAMUX20 = 2|0x100U, /*!< XBARA_OUT2 output assigned to DMAMUX slot 20 */ + kXbaraOutputDMAMUX21 = 3|0x100U, /*!< XBARA_OUT3 output assigned to DMAMUX slot 21 */ + kXbaraOutputXB_OUT4 = 4|0x100U, /*!< XBARA_OUT4 output assigned to XBAROUT4 output pin */ + kXbaraOutputXB_OUT5 = 5|0x100U, /*!< XBARA_OUT5 output assigned to XBAROUT5 output pin */ + kXbaraOutputXB_OUT6 = 6|0x100U, /*!< XBARA_OUT6 output assigned to XBAROUT6 output pin */ + kXbaraOutputXB_OUT7 = 7|0x100U, /*!< XBARA_OUT7 output assigned to XBAROUT7 output pin */ + kXbaraOutputXB_OUT8 = 8|0x100U, /*!< XBARA_OUT8 output assigned to XBAROUT8 output pin */ + kXbaraOutputXB_OUT9 = 9|0x100U, /*!< XBARA_OUT9 output assigned to XBAROUT9 output pin */ + kXbaraOutputXB_OUT10 = 10|0x100U, /*!< XBARA_OUT10 output assigned to XBAROUT10 output pin */ + kXbaraOutputXB_OUT11 = 11|0x100U, /*!< XBARA_OUT11 output assigned to XBAROUT11 output pin */ + kXbaraOutputADCA_TRIG = 12|0x100U, /*!< XBARA_OUT12 output assigned to ADC converter A trigger */ + kXbaraOutputADCB_TRIG = 13|0x100U, /*!< XBARA_OUT13 output assigned to ADC converter B trigger */ + kXbaraOutputRESERVED14 = 14|0x100U, /*!< XBARA_OUT14 output is reserved. */ + kXbaraOutputRESERVED15 = 15|0x100U, /*!< XBARA_OUT15 output is reserved. */ + kXbaraOutputCMP0 = 16|0x100U, /*!< XBARA_OUT16 output assigned to CMP0 window/sample */ + kXbaraOutputCMP1 = 17|0x100U, /*!< XBARA_OUT17 output assigned to CMP1 window/sample */ + kXbaraOutputCMP2 = 18|0x100U, /*!< XBARA_OUT18 output assigned to CMP2 window/sample */ + kXbaraOutputCMP3 = 19|0x100U, /*!< XBARA_OUT19 output assigned to CMP3 window/sample */ + kXbaraOutputPWMA0_EXTA = 20|0x100U, /*!< XBARA_OUT20 output assigned to PWMA channel 0 external control A */ + kXbaraOutputPWMA1_EXTA = 21|0x100U, /*!< XBARA_OUT21 output assigned to PWMA channel 1 external control A */ + kXbaraOutputPWMA2_EXTA = 22|0x100U, /*!< XBARA_OUT22 output assigned to PWMA channel 2 external control A */ + kXbaraOutputPWMA3_EXTA = 23|0x100U, /*!< XBARA_OUT23 output assigned to PWMA channel 3 external control A */ + kXbaraOutputPWMA0_EXT_SYNC = 24|0x100U, /*!< XBARA_OUT24 output assigned to PWMA channel 0 external synchronization */ + kXbaraOutputPWMA1_EXT_SYNC = 25|0x100U, /*!< XBARA_OUT25 output assigned to PWMA channel 1 external synchronization */ + kXbaraOutputPWMA2_EXT_SYNC = 26|0x100U, /*!< XBARA_OUT26 output assigned to PWMA channel 2 external synchronization */ + kXbaraOutputPWMA3_EXT_SYNC = 27|0x100U, /*!< XBARA_OUT27 output assigned to PWMA channel 3 external synchronization */ + kXbaraOutputPWMA_EXT_CLK = 28|0x100U, /*!< XBARA_OUT28 output assigned to PWMA external clock */ + kXbaraOutputPWMA_FAULT0 = 29|0x100U, /*!< XBARA_OUT29 output assigned to PWMA fault 0 */ + kXbaraOutputPWMA_FAULT1 = 30|0x100U, /*!< XBARA_OUT30 output assigned to PWMA fault 1 */ + kXbaraOutputPWMA_FAULT2 = 31|0x100U, /*!< XBARA_OUT31 output assigned to PWMA fault 2 */ + kXbaraOutputPWMA_FAULT3 = 32|0x100U, /*!< XBARA_OUT32 output assigned to PWMA fault 3 */ + kXbaraOutputPWMA_FORCE = 33|0x100U, /*!< XBARA_OUT33 output assigned to PWMA external output force */ + kXbaraOutputRESERVED34 = 34|0x100U, /*!< XBARA_OUT34 output is reserved. */ + kXbaraOutputRESERVED35 = 35|0x100U, /*!< XBARA_OUT35 output is reserved. */ + kXbaraOutputRESERVED36 = 36|0x100U, /*!< XBARA_OUT36 output is reserved. */ + kXbaraOutputRESERVED37 = 37|0x100U, /*!< XBARA_OUT37 output is reserved. */ + kXbaraOutputPDB0_IN_CH_12 = 38|0x100U, /*!< XBARA_OUT38 output assigned to PDB0 trigger option 12 */ + kXbaraOutputRESERVED39 = 39|0x100U, /*!< XBARA_OUT39 output is reserved. */ + kXbaraOutputRESERVED40 = 40|0x100U, /*!< XBARA_OUT40 output is reserved. */ + kXbaraOutputPDB1_IN_CH_12 = 41|0x100U, /*!< XBARA_OUT41 output assigned to PDB1 trigger option 12 */ + kXbaraOutputRESERVED42 = 42|0x100U, /*!< XBARA_OUT42 output is reserved. */ + kXbaraOutputRESERVED43 = 43|0x100U, /*!< XBARA_OUT43 output is reserved. */ + kXbaraOutputENC_PHA = 44|0x100U, /*!< XBARA_OUT44 output assigned to ENC quadrature waveform phase A */ + kXbaraOutputENC_PHB = 45|0x100U, /*!< XBARA_OUT45 output assigned to ENC quadrature waveform phase B */ + kXbaraOutputENC_INDEX = 46|0x100U, /*!< XBARA_OUT46 output assigned to ENC refresh/reload */ + kXbaraOutputENC_HOME = 47|0x100U, /*!< XBARA_OUT47 output assigned to ENC home position */ + kXbaraOutputENC_CAP_Trigger = 48|0x100U, /*!< XBARA_OUT48 output assigned to ENC clear/snapshot */ + kXbaraOutputRESERVED49 = 49|0x100U, /*!< XBARA_OUT49 output is reserved. */ + kXbaraOutputRESERVED50 = 50|0x100U, /*!< XBARA_OUT50 output is reserved. */ + kXbaraOutputRESERVED51 = 51|0x100U, /*!< XBARA_OUT51 output is reserved. */ + kXbaraOutputRESERVED52 = 52|0x100U, /*!< XBARA_OUT52 output is reserved. */ + kXbaraOutputRESERVED53 = 53|0x100U, /*!< XBARA_OUT53 output is reserved. */ + kXbaraOutputRESERVED54 = 54|0x100U, /*!< XBARA_OUT54 output is reserved. */ + kXbaraOutputRESERVED55 = 55|0x100U, /*!< XBARA_OUT55 output is reserved. */ + kXbaraOutputRESERVED56 = 56|0x100U, /*!< XBARA_OUT56 output is reserved. */ + kXbaraOutputRESERVED57 = 57|0x100U, /*!< XBARA_OUT57 output is reserved. */ + kXbaraOutputEWM_IN = 58|0x100U, /*!< XBARA_OUT58 output assigned to EWM input */ + kXbarbOutputAOI_IN0 = 0|0x200U, /*!< XBARB_OUT0 output assigned to AOI input0 */ + kXbarbOutputAOI_IN1 = 1|0x200U, /*!< XBARB_OUT1 output assigned to AOI input1 */ + kXbarbOutputAOI_IN2 = 2|0x200U, /*!< XBARB_OUT2 output assigned to AOI input2 */ + kXbarbOutputAOI_IN3 = 3|0x200U, /*!< XBARB_OUT3 output assigned to AOI input3 */ + kXbarbOutputAOI_IN4 = 4|0x200U, /*!< XBARB_OUT4 output assigned to AOI input4 */ + kXbarbOutputAOI_IN5 = 5|0x200U, /*!< XBARB_OUT5 output assigned to AOI input5 */ + kXbarbOutputAOI_IN6 = 6|0x200U, /*!< XBARB_OUT6 output assigned to AOI input6 */ + kXbarbOutputAOI_IN7 = 7|0x200U, /*!< XBARB_OUT7 output assigned to AOI input7 */ + kXbarbOutputAOI_IN8 = 8|0x200U, /*!< XBARB_OUT8 output assigned to AOI input8 */ + kXbarbOutputAOI_IN9 = 9|0x200U, /*!< XBARB_OUT9 output assigned to AOI input9 */ + kXbarbOutputAOI_IN10 = 10|0x200U, /*!< XBARB_OUT10 output assigned to AOI input10 */ + kXbarbOutputAOI_IN11 = 11|0x200U, /*!< XBARB_OUT11 output assigned to AOI input11 */ + kXbarbOutputAOI_IN12 = 12|0x200U, /*!< XBARB_OUT12 output assigned to AOI input12 */ + kXbarbOutputAOI_IN13 = 13|0x200U, /*!< XBARB_OUT13 output assigned to AOI input13 */ + kXbarbOutputAOI_IN14 = 14|0x200U, /*!< XBARB_OUT14 output assigned to AOI input14 */ + kXbarbOutputAOI_IN15 = 15|0x200U, /*!< XBARB_OUT15 output assigned to AOI input15 */ +#elif defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) + kXbaraOutputDMAMUX18 = 0|0x100U, /*!< XBARA_OUT0 output assigned to DMAMUX slot 18 */ + kXbaraOutputDMAMUX19 = 1|0x100U, /*!< XBARA_OUT1 output assigned to DMAMUX slot 19 */ + kXbaraOutputDMAMUX20 = 2|0x100U, /*!< XBARA_OUT2 output assigned to DMAMUX slot 20 */ + kXbaraOutputDMAMUX21 = 3|0x100U, /*!< XBARA_OUT3 output assigned to DMAMUX slot 21 */ + kXbaraOutputXB_OUT4 = 4|0x100U, /*!< XBARA_OUT4 output assigned to XBAROUT4 output pin */ + kXbaraOutputXB_OUT5 = 5|0x100U, /*!< XBARA_OUT5 output assigned to XBAROUT5 output pin */ + kXbaraOutputXB_OUT6 = 6|0x100U, /*!< XBARA_OUT6 output assigned to XBAROUT6 output pin */ + kXbaraOutputXB_OUT7 = 7|0x100U, /*!< XBARA_OUT7 output assigned to XBAROUT7 output pin */ + kXbaraOutputXB_OUT8 = 8|0x100U, /*!< XBARA_OUT8 output assigned to XBAROUT8 output pin */ + kXbaraOutputXB_OUT9 = 9|0x100U, /*!< XBARA_OUT9 output assigned to XBAROUT9 output pin */ + kXbaraOutputXB_OUT10 = 10|0x100U, /*!< XBARA_OUT10 output assigned to XBAROUT10 output pin */ + kXbaraOutputXB_OUT11 = 11|0x100U, /*!< XBARA_OUT11 output assigned to XBAROUT11 output pin */ + kXbaraOutputADCA_TRIG = 12|0x100U, /*!< XBARA_OUT12 output assigned to ADC converter A trigger */ + kXbaraOutputADCB_TRIG = 13|0x100U, /*!< XBARA_OUT13 output assigned to ADC converter B trigger */ + kXbaraOutputRESERVED14 = 14|0x100U, /*!< XBARA_OUT14 output is reserved. */ + kXbaraOutputDAC_12B_SYNC = 15|0x100U, /*!< XBARA_OUT15 output assigned to DAC synchronisation trigger */ + kXbaraOutputCMP0 = 16|0x100U, /*!< XBARA_OUT16 output assigned to CMP0 window/sample */ + kXbaraOutputCMP1 = 17|0x100U, /*!< XBARA_OUT17 output assigned to CMP1 window/sample */ + kXbaraOutputCMP2 = 18|0x100U, /*!< XBARA_OUT18 output assigned to CMP2 window/sample */ + kXbaraOutputCMP3 = 19|0x100U, /*!< XBARA_OUT19 output assigned to CMP3 window/sample */ + kXbaraOutputPWMA0_EXTA = 20|0x100U, /*!< XBARA_OUT20 output assigned to PWMA channel 0 external control A */ + kXbaraOutputPWMA1_EXTA = 21|0x100U, /*!< XBARA_OUT21 output assigned to PWMA channel 1 external control A */ + kXbaraOutputPWMA2_EXTA = 22|0x100U, /*!< XBARA_OUT22 output assigned to PWMA channel 2 external control A */ + kXbaraOutputPWMA3_EXTA = 23|0x100U, /*!< XBARA_OUT23 output assigned to PWMA channel 3 external control A */ + kXbaraOutputPWMA0_EXT_SYNC = 24|0x100U, /*!< XBARA_OUT24 output assigned to PWMA channel 0 external synchronization */ + kXbaraOutputPWMA1_EXT_SYNC = 25|0x100U, /*!< XBARA_OUT25 output assigned to PWMA channel 1 external synchronization */ + kXbaraOutputPWMA2_EXT_SYNC = 26|0x100U, /*!< XBARA_OUT26 output assigned to PWMA channel 2 external synchronization */ + kXbaraOutputPWMA3_EXT_SYNC = 27|0x100U, /*!< XBARA_OUT27 output assigned to PWMA channel 3 external synchronization */ + kXbaraOutputPWMA_EXT_CLK = 28|0x100U, /*!< XBARA_OUT28 output assigned to PWMA external clock */ + kXbaraOutputPWMA_FAULT0 = 29|0x100U, /*!< XBARA_OUT29 output assigned to PWMA fault 0 */ + kXbaraOutputPWMA_FAULT1 = 30|0x100U, /*!< XBARA_OUT30 output assigned to PWMA fault 1 */ + kXbaraOutputPWMA_FAULT2 = 31|0x100U, /*!< XBARA_OUT31 output assigned to PWMA fault 2 */ + kXbaraOutputPWMA_FAULT3 = 32|0x100U, /*!< XBARA_OUT32 output assigned to PWMA fault 3 */ + kXbaraOutputPWMA_FORCE = 33|0x100U, /*!< XBARA_OUT33 output assigned to PWMA external output force */ + kXbaraOutputRESERVED34 = 34|0x100U, /*!< XBARA_OUT34 output is reserved. */ + kXbaraOutputRESERVED35 = 35|0x100U, /*!< XBARA_OUT35 output is reserved. */ + kXbaraOutputRESERVED36 = 36|0x100U, /*!< XBARA_OUT36 output is reserved. */ + kXbaraOutputRESERVED37 = 37|0x100U, /*!< XBARA_OUT37 output is reserved. */ + kXbaraOutputPDB0_IN_CH_12 = 38|0x100U, /*!< XBARA_OUT38 output assigned to PDB0 trigger option 12 */ + kXbaraOutputRESERVED39 = 39|0x100U, /*!< XBARA_OUT39 output is reserved. */ + kXbaraOutputRESERVED40 = 40|0x100U, /*!< XBARA_OUT40 output is reserved. */ + kXbaraOutputPDB1_IN_CH_12 = 41|0x100U, /*!< XBARA_OUT41 output assigned to PDB1 trigger option 12 */ + kXbaraOutputRESERVED42 = 42|0x100U, /*!< XBARA_OUT42 output is reserved. */ + kXbaraOutputRESERVED43 = 43|0x100U, /*!< XBARA_OUT43 output is reserved. */ + kXbaraOutputENC_PHA = 44|0x100U, /*!< XBARA_OUT44 output assigned to ENC quadrature waveform phase A */ + kXbaraOutputENC_PHB = 45|0x100U, /*!< XBARA_OUT45 output assigned to ENC quadrature waveform phase B */ + kXbaraOutputENC_INDEX = 46|0x100U, /*!< XBARA_OUT46 output assigned to ENC refresh/reload */ + kXbaraOutputENC_HOME = 47|0x100U, /*!< XBARA_OUT47 output assigned to ENC home position */ + kXbaraOutputENC_CAP_Trigger = 48|0x100U, /*!< XBARA_OUT48 output assigned to ENC clear/snapshot */ + kXbaraOutputRESERVED49 = 49|0x100U, /*!< XBARA_OUT49 output is reserved. */ + kXbaraOutputRESERVED50 = 50|0x100U, /*!< XBARA_OUT50 output is reserved. */ + kXbaraOutputRESERVED51 = 51|0x100U, /*!< XBARA_OUT51 output is reserved. */ + kXbaraOutputRESERVED52 = 52|0x100U, /*!< XBARA_OUT52 output is reserved. */ + kXbaraOutputRESERVED53 = 53|0x100U, /*!< XBARA_OUT53 output is reserved. */ + kXbaraOutputRESERVED54 = 54|0x100U, /*!< XBARA_OUT54 output is reserved. */ + kXbaraOutputRESERVED55 = 55|0x100U, /*!< XBARA_OUT55 output is reserved. */ + kXbaraOutputRESERVED56 = 56|0x100U, /*!< XBARA_OUT56 output is reserved. */ + kXbaraOutputRESERVED57 = 57|0x100U, /*!< XBARA_OUT57 output is reserved. */ + kXbaraOutputEWM_IN = 58|0x100U, /*!< XBARA_OUT58 output assigned to EWM input */ + kXbarbOutputAOI_IN0 = 0|0x200U, /*!< XBARB_OUT0 output assigned to AOI input0 */ + kXbarbOutputAOI_IN1 = 1|0x200U, /*!< XBARB_OUT1 output assigned to AOI input1 */ + kXbarbOutputAOI_IN2 = 2|0x200U, /*!< XBARB_OUT2 output assigned to AOI input2 */ + kXbarbOutputAOI_IN3 = 3|0x200U, /*!< XBARB_OUT3 output assigned to AOI input3 */ + kXbarbOutputAOI_IN4 = 4|0x200U, /*!< XBARB_OUT4 output assigned to AOI input4 */ + kXbarbOutputAOI_IN5 = 5|0x200U, /*!< XBARB_OUT5 output assigned to AOI input5 */ + kXbarbOutputAOI_IN6 = 6|0x200U, /*!< XBARB_OUT6 output assigned to AOI input6 */ + kXbarbOutputAOI_IN7 = 7|0x200U, /*!< XBARB_OUT7 output assigned to AOI input7 */ + kXbarbOutputAOI_IN8 = 8|0x200U, /*!< XBARB_OUT8 output assigned to AOI input8 */ + kXbarbOutputAOI_IN9 = 9|0x200U, /*!< XBARB_OUT9 output assigned to AOI input9 */ + kXbarbOutputAOI_IN10 = 10|0x200U, /*!< XBARB_OUT10 output assigned to AOI input10 */ + kXbarbOutputAOI_IN11 = 11|0x200U, /*!< XBARB_OUT11 output assigned to AOI input11 */ + kXbarbOutputAOI_IN12 = 12|0x200U, /*!< XBARB_OUT12 output assigned to AOI input12 */ + kXbarbOutputAOI_IN13 = 13|0x200U, /*!< XBARB_OUT13 output assigned to AOI input13 */ + kXbarbOutputAOI_IN14 = 14|0x200U, /*!< XBARB_OUT14 output assigned to AOI input14 */ + kXbarbOutputAOI_IN15 = 15|0x200U, /*!< XBARB_OUT15 output assigned to AOI input15 */ +#elif defined(CPU_MKV45F128VLH15) || defined(CPU_MKV45F256VLH15) + kXbaraOutputDMAMUX18 = 0|0x100U, /*!< XBARA_OUT0 output assigned to DMAMUX slot 18 */ + kXbaraOutputDMAMUX19 = 1|0x100U, /*!< XBARA_OUT1 output assigned to DMAMUX slot 19 */ + kXbaraOutputDMAMUX20 = 2|0x100U, /*!< XBARA_OUT2 output assigned to DMAMUX slot 20 */ + kXbaraOutputDMAMUX21 = 3|0x100U, /*!< XBARA_OUT3 output assigned to DMAMUX slot 21 */ + kXbaraOutputXB_OUT4 = 4|0x100U, /*!< XBARA_OUT4 output assigned to XBAROUT4 output pin */ + kXbaraOutputXB_OUT5 = 5|0x100U, /*!< XBARA_OUT5 output assigned to XBAROUT5 output pin */ + kXbaraOutputXB_OUT6 = 6|0x100U, /*!< XBARA_OUT6 output assigned to XBAROUT6 output pin */ + kXbaraOutputXB_OUT7 = 7|0x100U, /*!< XBARA_OUT7 output assigned to XBAROUT7 output pin */ + kXbaraOutputXB_OUT8 = 8|0x100U, /*!< XBARA_OUT8 output assigned to XBAROUT8 output pin */ + kXbaraOutputXB_OUT9 = 9|0x100U, /*!< XBARA_OUT9 output assigned to XBAROUT9 output pin */ + kXbaraOutputXB_OUT10 = 10|0x100U, /*!< XBARA_OUT10 output assigned to XBAROUT10 output pin */ + kXbaraOutputXB_OUT11 = 11|0x100U, /*!< XBARA_OUT11 output assigned to XBAROUT11 output pin */ + kXbaraOutputADCA_TRIG = 12|0x100U, /*!< XBARA_OUT12 output assigned to ADC converter A trigger */ + kXbaraOutputADCB_TRIG = 13|0x100U, /*!< XBARA_OUT13 output assigned to ADC converter B trigger */ + kXbaraOutputRESERVED14 = 14|0x100U, /*!< XBARA_OUT14 output is reserved. */ + kXbaraOutputRESERVED15 = 15|0x100U, /*!< XBARA_OUT15 output is reserved. */ + kXbaraOutputCMP0 = 16|0x100U, /*!< XBARA_OUT16 output assigned to CMP0 window/sample */ + kXbaraOutputCMP1 = 17|0x100U, /*!< XBARA_OUT17 output assigned to CMP1 window/sample */ + kXbaraOutputCMP2 = 18|0x100U, /*!< XBARA_OUT18 output assigned to CMP2 window/sample */ + kXbaraOutputCMP3 = 19|0x100U, /*!< XBARA_OUT19 output assigned to CMP3 window/sample */ + kXbaraOutputPWMA0_EXTA = 20|0x100U, /*!< XBARA_OUT20 output assigned to PWMA channel 0 external control A */ + kXbaraOutputPWMA1_EXTA = 21|0x100U, /*!< XBARA_OUT21 output assigned to PWMA channel 1 external control A */ + kXbaraOutputPWMA2_EXTA = 22|0x100U, /*!< XBARA_OUT22 output assigned to PWMA channel 2 external control A */ + kXbaraOutputPWMA3_EXTA = 23|0x100U, /*!< XBARA_OUT23 output assigned to PWMA channel 3 external control A */ + kXbaraOutputPWMA0_EXT_SYNC = 24|0x100U, /*!< XBARA_OUT24 output assigned to PWMA channel 0 external synchronization */ + kXbaraOutputPWMA1_EXT_SYNC = 25|0x100U, /*!< XBARA_OUT25 output assigned to PWMA channel 1 external synchronization */ + kXbaraOutputPWMA2_EXT_SYNC = 26|0x100U, /*!< XBARA_OUT26 output assigned to PWMA channel 2 external synchronization */ + kXbaraOutputPWMA3_EXT_SYNC = 27|0x100U, /*!< XBARA_OUT27 output assigned to PWMA channel 3 external synchronization */ + kXbaraOutputPWMA_EXT_CLK = 28|0x100U, /*!< XBARA_OUT28 output assigned to PWMA external clock */ + kXbaraOutputPWMA_FAULT0 = 29|0x100U, /*!< XBARA_OUT29 output assigned to PWMA fault 0 */ + kXbaraOutputPWMA_FAULT1 = 30|0x100U, /*!< XBARA_OUT30 output assigned to PWMA fault 1 */ + kXbaraOutputPWMA_FAULT2 = 31|0x100U, /*!< XBARA_OUT31 output assigned to PWMA fault 2 */ + kXbaraOutputPWMA_FAULT3 = 32|0x100U, /*!< XBARA_OUT32 output assigned to PWMA fault 3 */ + kXbaraOutputPWMA_FORCE = 33|0x100U, /*!< XBARA_OUT33 output assigned to PWMA external output force */ + kXbaraOutputFTM0_TRIG2 = 34|0x100U, /*!< XBARA_OUT34 output assigned to FTM0 hardware trigger 2 */ + kXbaraOutputFTM1_TRIG2 = 35|0x100U, /*!< XBARA_OUT35 output assigned to FTM1 hardware trigger 2 */ + kXbaraOutputRESERVED36 = 36|0x100U, /*!< XBARA_OUT36 output is reserved. */ + kXbaraOutputRESERVED37 = 37|0x100U, /*!< XBARA_OUT37 output is reserved. */ + kXbaraOutputPDB0_IN_CH_12 = 38|0x100U, /*!< XBARA_OUT38 output assigned to PDB0 trigger option 12 */ + kXbaraOutputRESERVED39 = 39|0x100U, /*!< XBARA_OUT39 output is reserved. */ + kXbaraOutputRESERVED40 = 40|0x100U, /*!< XBARA_OUT40 output is reserved. */ + kXbaraOutputPDB1_IN_CH_12 = 41|0x100U, /*!< XBARA_OUT41 output assigned to PDB1 trigger option 12 */ + kXbaraOutputSIM_XOR_FTM1_CH1_FTM1_CH2 = 42|0x100U, /*!< XBARA_OUT42 output assigned to SIM XOR of FTM1_CH1 and FTM1_CH0 pins and XBARA output 42 */ + kXbaraOutputRESERVED43 = 43|0x100U, /*!< XBARA_OUT43 output is reserved. */ + kXbaraOutputENC_PHA = 44|0x100U, /*!< XBARA_OUT44 output assigned to ENC quadrature waveform phase A */ + kXbaraOutputENC_PHB = 45|0x100U, /*!< XBARA_OUT45 output assigned to ENC quadrature waveform phase B */ + kXbaraOutputENC_INDEX = 46|0x100U, /*!< XBARA_OUT46 output assigned to ENC refresh/reload */ + kXbaraOutputENC_HOME = 47|0x100U, /*!< XBARA_OUT47 output assigned to ENC home position */ + kXbaraOutputENC_CAP_Trigger = 48|0x100U, /*!< XBARA_OUT48 output assigned to ENC clear/snapshot */ + kXbaraOutputFTM0_FAULT3 = 49|0x100U, /*!< XBARA_OUT49 output assigned to FTM0 fault 3 */ + kXbaraOutputFTM1_FAULT1 = 50|0x100U, /*!< XBARA_OUT50 output assigned to FTM1 fault 1 */ + kXbaraOutputRESERVED51 = 51|0x100U, /*!< XBARA_OUT51 output is reserved. */ + kXbaraOutputRESERVED52 = 52|0x100U, /*!< XBARA_OUT52 output is reserved. */ + kXbaraOutputRESERVED53 = 53|0x100U, /*!< XBARA_OUT53 output is reserved. */ + kXbaraOutputRESERVED54 = 54|0x100U, /*!< XBARA_OUT54 output is reserved. */ + kXbaraOutputRESERVED55 = 55|0x100U, /*!< XBARA_OUT55 output is reserved. */ + kXbaraOutputRESERVED56 = 56|0x100U, /*!< XBARA_OUT56 output is reserved. */ + kXbaraOutputRESERVED57 = 57|0x100U, /*!< XBARA_OUT57 output is reserved. */ + kXbaraOutputEWM_IN = 58|0x100U, /*!< XBARA_OUT58 output assigned to EWM input */ + kXbarbOutputAOI_IN0 = 0|0x200U, /*!< XBARB_OUT0 output assigned to AOI input0 */ + kXbarbOutputAOI_IN1 = 1|0x200U, /*!< XBARB_OUT1 output assigned to AOI input1 */ + kXbarbOutputAOI_IN2 = 2|0x200U, /*!< XBARB_OUT2 output assigned to AOI input2 */ + kXbarbOutputAOI_IN3 = 3|0x200U, /*!< XBARB_OUT3 output assigned to AOI input3 */ + kXbarbOutputAOI_IN4 = 4|0x200U, /*!< XBARB_OUT4 output assigned to AOI input4 */ + kXbarbOutputAOI_IN5 = 5|0x200U, /*!< XBARB_OUT5 output assigned to AOI input5 */ + kXbarbOutputAOI_IN6 = 6|0x200U, /*!< XBARB_OUT6 output assigned to AOI input6 */ + kXbarbOutputAOI_IN7 = 7|0x200U, /*!< XBARB_OUT7 output assigned to AOI input7 */ + kXbarbOutputAOI_IN8 = 8|0x200U, /*!< XBARB_OUT8 output assigned to AOI input8 */ + kXbarbOutputAOI_IN9 = 9|0x200U, /*!< XBARB_OUT9 output assigned to AOI input9 */ + kXbarbOutputAOI_IN10 = 10|0x200U, /*!< XBARB_OUT10 output assigned to AOI input10 */ + kXbarbOutputAOI_IN11 = 11|0x200U, /*!< XBARB_OUT11 output assigned to AOI input11 */ + kXbarbOutputAOI_IN12 = 12|0x200U, /*!< XBARB_OUT12 output assigned to AOI input12 */ + kXbarbOutputAOI_IN13 = 13|0x200U, /*!< XBARB_OUT13 output assigned to AOI input13 */ + kXbarbOutputAOI_IN14 = 14|0x200U, /*!< XBARB_OUT14 output assigned to AOI input14 */ + kXbarbOutputAOI_IN15 = 15|0x200U, /*!< XBARB_OUT15 output assigned to AOI input15 */ +#elif defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLL15) + kXbaraOutputDMAMUX18 = 0|0x100U, /*!< XBARA_OUT0 output assigned to DMAMUX slot 18 */ + kXbaraOutputDMAMUX19 = 1|0x100U, /*!< XBARA_OUT1 output assigned to DMAMUX slot 19 */ + kXbaraOutputDMAMUX20 = 2|0x100U, /*!< XBARA_OUT2 output assigned to DMAMUX slot 20 */ + kXbaraOutputDMAMUX21 = 3|0x100U, /*!< XBARA_OUT3 output assigned to DMAMUX slot 21 */ + kXbaraOutputXB_OUT4 = 4|0x100U, /*!< XBARA_OUT4 output assigned to XBAROUT4 output pin */ + kXbaraOutputXB_OUT5 = 5|0x100U, /*!< XBARA_OUT5 output assigned to XBAROUT5 output pin */ + kXbaraOutputXB_OUT6 = 6|0x100U, /*!< XBARA_OUT6 output assigned to XBAROUT6 output pin */ + kXbaraOutputXB_OUT7 = 7|0x100U, /*!< XBARA_OUT7 output assigned to XBAROUT7 output pin */ + kXbaraOutputXB_OUT8 = 8|0x100U, /*!< XBARA_OUT8 output assigned to XBAROUT8 output pin */ + kXbaraOutputXB_OUT9 = 9|0x100U, /*!< XBARA_OUT9 output assigned to XBAROUT9 output pin */ + kXbaraOutputXB_OUT10 = 10|0x100U, /*!< XBARA_OUT10 output assigned to XBAROUT10 output pin */ + kXbaraOutputXB_OUT11 = 11|0x100U, /*!< XBARA_OUT11 output assigned to XBAROUT11 output pin */ + kXbaraOutputADCA_TRIG = 12|0x100U, /*!< XBARA_OUT12 output assigned to ADC converter A trigger */ + kXbaraOutputADCB_TRIG = 13|0x100U, /*!< XBARA_OUT13 output assigned to ADC converter B trigger */ + kXbaraOutputRESERVED14 = 14|0x100U, /*!< XBARA_OUT14 output is reserved. */ + kXbaraOutputRESERVED15 = 15|0x100U, /*!< XBARA_OUT15 output is reserved. */ + kXbaraOutputCMP0 = 16|0x100U, /*!< XBARA_OUT16 output assigned to CMP0 window/sample */ + kXbaraOutputCMP1 = 17|0x100U, /*!< XBARA_OUT17 output assigned to CMP1 window/sample */ + kXbaraOutputCMP2 = 18|0x100U, /*!< XBARA_OUT18 output assigned to CMP2 window/sample */ + kXbaraOutputCMP3 = 19|0x100U, /*!< XBARA_OUT19 output assigned to CMP3 window/sample */ + kXbaraOutputPWMA0_EXTA = 20|0x100U, /*!< XBARA_OUT20 output assigned to PWMA channel 0 external control A */ + kXbaraOutputPWMA1_EXTA = 21|0x100U, /*!< XBARA_OUT21 output assigned to PWMA channel 1 external control A */ + kXbaraOutputPWMA2_EXTA = 22|0x100U, /*!< XBARA_OUT22 output assigned to PWMA channel 2 external control A */ + kXbaraOutputPWMA3_EXTA = 23|0x100U, /*!< XBARA_OUT23 output assigned to PWMA channel 3 external control A */ + kXbaraOutputPWMA0_EXT_SYNC = 24|0x100U, /*!< XBARA_OUT24 output assigned to PWMA channel 0 external synchronization */ + kXbaraOutputPWMA1_EXT_SYNC = 25|0x100U, /*!< XBARA_OUT25 output assigned to PWMA channel 1 external synchronization */ + kXbaraOutputPWMA2_EXT_SYNC = 26|0x100U, /*!< XBARA_OUT26 output assigned to PWMA channel 2 external synchronization */ + kXbaraOutputPWMA3_EXT_SYNC = 27|0x100U, /*!< XBARA_OUT27 output assigned to PWMA channel 3 external synchronization */ + kXbaraOutputPWMA_EXT_CLK = 28|0x100U, /*!< XBARA_OUT28 output assigned to PWMA external clock */ + kXbaraOutputPWMA_FAULT0 = 29|0x100U, /*!< XBARA_OUT29 output assigned to PWMA fault 0 */ + kXbaraOutputPWMA_FAULT1 = 30|0x100U, /*!< XBARA_OUT30 output assigned to PWMA fault 1 */ + kXbaraOutputPWMA_FAULT2 = 31|0x100U, /*!< XBARA_OUT31 output assigned to PWMA fault 2 */ + kXbaraOutputPWMA_FAULT3 = 32|0x100U, /*!< XBARA_OUT32 output assigned to PWMA fault 3 */ + kXbaraOutputPWMA_FORCE = 33|0x100U, /*!< XBARA_OUT33 output assigned to PWMA external output force */ + kXbaraOutputFTM0_TRIG2 = 34|0x100U, /*!< XBARA_OUT34 output assigned to FTM0 hardware trigger 2 */ + kXbaraOutputFTM1_TRIG2 = 35|0x100U, /*!< XBARA_OUT35 output assigned to FTM1 hardware trigger 2 */ + kXbaraOutputRESERVED36 = 36|0x100U, /*!< XBARA_OUT36 output is reserved. */ + kXbaraOutputFTM3_TRIG2 = 37|0x100U, /*!< XBARA_OUT37 output assigned to FTM3 hardware trigger 2 */ + kXbaraOutputPDB0_IN_CH_12 = 38|0x100U, /*!< XBARA_OUT38 output assigned to PDB0 trigger option 12 */ + kXbaraOutputRESERVED39 = 39|0x100U, /*!< XBARA_OUT39 output is reserved. */ + kXbaraOutputRESERVED40 = 40|0x100U, /*!< XBARA_OUT40 output is reserved. */ + kXbaraOutputPDB1_IN_CH_12 = 41|0x100U, /*!< XBARA_OUT41 output assigned to PDB1 trigger option 12 */ + kXbaraOutputSIM_XOR_FTM1_CH1_FTM1_CH2 = 42|0x100U, /*!< XBARA_OUT42 output assigned to SIM XOR of FTM1_CH1 and FTM1_CH0 pins and XBARA output 42 */ + kXbaraOutputRESERVED43 = 43|0x100U, /*!< XBARA_OUT43 output is reserved. */ + kXbaraOutputENC_PHA = 44|0x100U, /*!< XBARA_OUT44 output assigned to ENC quadrature waveform phase A */ + kXbaraOutputENC_PHB = 45|0x100U, /*!< XBARA_OUT45 output assigned to ENC quadrature waveform phase B */ + kXbaraOutputENC_INDEX = 46|0x100U, /*!< XBARA_OUT46 output assigned to ENC refresh/reload */ + kXbaraOutputENC_HOME = 47|0x100U, /*!< XBARA_OUT47 output assigned to ENC home position */ + kXbaraOutputENC_CAP_Trigger = 48|0x100U, /*!< XBARA_OUT48 output assigned to ENC clear/snapshot */ + kXbaraOutputFTM0_FAULT3 = 49|0x100U, /*!< XBARA_OUT49 output assigned to FTM0 fault 3 */ + kXbaraOutputFTM1_FAULT1 = 50|0x100U, /*!< XBARA_OUT50 output assigned to FTM1 fault 1 */ + kXbaraOutputRESERVED51 = 51|0x100U, /*!< XBARA_OUT51 output is reserved. */ + kXbaraOutputFTM3_FAULT3 = 52|0x100U, /*!< XBARA_OUT52 output assigned to FTM3 fault 3 */ + kXbaraOutputRESERVED53 = 53|0x100U, /*!< XBARA_OUT53 output is reserved. */ + kXbaraOutputRESERVED54 = 54|0x100U, /*!< XBARA_OUT54 output is reserved. */ + kXbaraOutputRESERVED55 = 55|0x100U, /*!< XBARA_OUT55 output is reserved. */ + kXbaraOutputRESERVED56 = 56|0x100U, /*!< XBARA_OUT56 output is reserved. */ + kXbaraOutputRESERVED57 = 57|0x100U, /*!< XBARA_OUT57 output is reserved. */ + kXbaraOutputEWM_IN = 58|0x100U, /*!< XBARA_OUT58 output assigned to EWM input */ + kXbarbOutputAOI_IN0 = 0|0x200U, /*!< XBARB_OUT0 output assigned to AOI input0 */ + kXbarbOutputAOI_IN1 = 1|0x200U, /*!< XBARB_OUT1 output assigned to AOI input1 */ + kXbarbOutputAOI_IN2 = 2|0x200U, /*!< XBARB_OUT2 output assigned to AOI input2 */ + kXbarbOutputAOI_IN3 = 3|0x200U, /*!< XBARB_OUT3 output assigned to AOI input3 */ + kXbarbOutputAOI_IN4 = 4|0x200U, /*!< XBARB_OUT4 output assigned to AOI input4 */ + kXbarbOutputAOI_IN5 = 5|0x200U, /*!< XBARB_OUT5 output assigned to AOI input5 */ + kXbarbOutputAOI_IN6 = 6|0x200U, /*!< XBARB_OUT6 output assigned to AOI input6 */ + kXbarbOutputAOI_IN7 = 7|0x200U, /*!< XBARB_OUT7 output assigned to AOI input7 */ + kXbarbOutputAOI_IN8 = 8|0x200U, /*!< XBARB_OUT8 output assigned to AOI input8 */ + kXbarbOutputAOI_IN9 = 9|0x200U, /*!< XBARB_OUT9 output assigned to AOI input9 */ + kXbarbOutputAOI_IN10 = 10|0x200U, /*!< XBARB_OUT10 output assigned to AOI input10 */ + kXbarbOutputAOI_IN11 = 11|0x200U, /*!< XBARB_OUT11 output assigned to AOI input11 */ + kXbarbOutputAOI_IN12 = 12|0x200U, /*!< XBARB_OUT12 output assigned to AOI input12 */ + kXbarbOutputAOI_IN13 = 13|0x200U, /*!< XBARB_OUT13 output assigned to AOI input13 */ + kXbarbOutputAOI_IN14 = 14|0x200U, /*!< XBARB_OUT14 output assigned to AOI input14 */ + kXbarbOutputAOI_IN15 = 15|0x200U, /*!< XBARB_OUT15 output assigned to AOI input15 */ +#elif defined(CPU_MKV46F128VLH15) || defined(CPU_MKV46F256VLH15) + kXbaraOutputDMAMUX18 = 0|0x100U, /*!< XBARA_OUT0 output assigned to DMAMUX slot 18 */ + kXbaraOutputDMAMUX19 = 1|0x100U, /*!< XBARA_OUT1 output assigned to DMAMUX slot 19 */ + kXbaraOutputDMAMUX20 = 2|0x100U, /*!< XBARA_OUT2 output assigned to DMAMUX slot 20 */ + kXbaraOutputDMAMUX21 = 3|0x100U, /*!< XBARA_OUT3 output assigned to DMAMUX slot 21 */ + kXbaraOutputXB_OUT4 = 4|0x100U, /*!< XBARA_OUT4 output assigned to XBAROUT4 output pin */ + kXbaraOutputXB_OUT5 = 5|0x100U, /*!< XBARA_OUT5 output assigned to XBAROUT5 output pin */ + kXbaraOutputXB_OUT6 = 6|0x100U, /*!< XBARA_OUT6 output assigned to XBAROUT6 output pin */ + kXbaraOutputXB_OUT7 = 7|0x100U, /*!< XBARA_OUT7 output assigned to XBAROUT7 output pin */ + kXbaraOutputXB_OUT8 = 8|0x100U, /*!< XBARA_OUT8 output assigned to XBAROUT8 output pin */ + kXbaraOutputXB_OUT9 = 9|0x100U, /*!< XBARA_OUT9 output assigned to XBAROUT9 output pin */ + kXbaraOutputXB_OUT10 = 10|0x100U, /*!< XBARA_OUT10 output assigned to XBAROUT10 output pin */ + kXbaraOutputXB_OUT11 = 11|0x100U, /*!< XBARA_OUT11 output assigned to XBAROUT11 output pin */ + kXbaraOutputADCA_TRIG = 12|0x100U, /*!< XBARA_OUT12 output assigned to ADC converter A trigger */ + kXbaraOutputADCB_TRIG = 13|0x100U, /*!< XBARA_OUT13 output assigned to ADC converter B trigger */ + kXbaraOutputRESERVED14 = 14|0x100U, /*!< XBARA_OUT14 output is reserved. */ + kXbaraOutputDAC_12B_SYNC = 15|0x100U, /*!< XBARA_OUT15 output assigned to DAC synchronisation trigger */ + kXbaraOutputCMP0 = 16|0x100U, /*!< XBARA_OUT16 output assigned to CMP0 window/sample */ + kXbaraOutputCMP1 = 17|0x100U, /*!< XBARA_OUT17 output assigned to CMP1 window/sample */ + kXbaraOutputCMP2 = 18|0x100U, /*!< XBARA_OUT18 output assigned to CMP2 window/sample */ + kXbaraOutputCMP3 = 19|0x100U, /*!< XBARA_OUT19 output assigned to CMP3 window/sample */ + kXbaraOutputPWMA0_EXTA = 20|0x100U, /*!< XBARA_OUT20 output assigned to PWMA channel 0 external control A */ + kXbaraOutputPWMA1_EXTA = 21|0x100U, /*!< XBARA_OUT21 output assigned to PWMA channel 1 external control A */ + kXbaraOutputPWMA2_EXTA = 22|0x100U, /*!< XBARA_OUT22 output assigned to PWMA channel 2 external control A */ + kXbaraOutputPWMA3_EXTA = 23|0x100U, /*!< XBARA_OUT23 output assigned to PWMA channel 3 external control A */ + kXbaraOutputPWMA0_EXT_SYNC = 24|0x100U, /*!< XBARA_OUT24 output assigned to PWMA channel 0 external synchronization */ + kXbaraOutputPWMA1_EXT_SYNC = 25|0x100U, /*!< XBARA_OUT25 output assigned to PWMA channel 1 external synchronization */ + kXbaraOutputPWMA2_EXT_SYNC = 26|0x100U, /*!< XBARA_OUT26 output assigned to PWMA channel 2 external synchronization */ + kXbaraOutputPWMA3_EXT_SYNC = 27|0x100U, /*!< XBARA_OUT27 output assigned to PWMA channel 3 external synchronization */ + kXbaraOutputPWMA_EXT_CLK = 28|0x100U, /*!< XBARA_OUT28 output assigned to PWMA external clock */ + kXbaraOutputPWMA_FAULT0 = 29|0x100U, /*!< XBARA_OUT29 output assigned to PWMA fault 0 */ + kXbaraOutputPWMA_FAULT1 = 30|0x100U, /*!< XBARA_OUT30 output assigned to PWMA fault 1 */ + kXbaraOutputPWMA_FAULT2 = 31|0x100U, /*!< XBARA_OUT31 output assigned to PWMA fault 2 */ + kXbaraOutputPWMA_FAULT3 = 32|0x100U, /*!< XBARA_OUT32 output assigned to PWMA fault 3 */ + kXbaraOutputPWMA_FORCE = 33|0x100U, /*!< XBARA_OUT33 output assigned to PWMA external output force */ + kXbaraOutputFTM0_TRIG2 = 34|0x100U, /*!< XBARA_OUT34 output assigned to FTM0 hardware trigger 2 */ + kXbaraOutputFTM1_TRIG2 = 35|0x100U, /*!< XBARA_OUT35 output assigned to FTM1 hardware trigger 2 */ + kXbaraOutputRESERVED36 = 36|0x100U, /*!< XBARA_OUT36 output is reserved. */ + kXbaraOutputRESERVED37 = 37|0x100U, /*!< XBARA_OUT37 output is reserved. */ + kXbaraOutputPDB0_IN_CH_12 = 38|0x100U, /*!< XBARA_OUT38 output assigned to PDB0 trigger option 12 */ + kXbaraOutputRESERVED39 = 39|0x100U, /*!< XBARA_OUT39 output is reserved. */ + kXbaraOutputRESERVED40 = 40|0x100U, /*!< XBARA_OUT40 output is reserved. */ + kXbaraOutputPDB1_IN_CH_12 = 41|0x100U, /*!< XBARA_OUT41 output assigned to PDB1 trigger option 12 */ + kXbaraOutputSIM_XOR_FTM1_CH1_FTM1_CH2 = 42|0x100U, /*!< XBARA_OUT42 output assigned to SIM XOR of FTM1_CH1 and FTM1_CH0 pins and XBARA output 42 */ + kXbaraOutputRESERVED43 = 43|0x100U, /*!< XBARA_OUT43 output is reserved. */ + kXbaraOutputENC_PHA = 44|0x100U, /*!< XBARA_OUT44 output assigned to ENC quadrature waveform phase A */ + kXbaraOutputENC_PHB = 45|0x100U, /*!< XBARA_OUT45 output assigned to ENC quadrature waveform phase B */ + kXbaraOutputENC_INDEX = 46|0x100U, /*!< XBARA_OUT46 output assigned to ENC refresh/reload */ + kXbaraOutputENC_HOME = 47|0x100U, /*!< XBARA_OUT47 output assigned to ENC home position */ + kXbaraOutputENC_CAP_Trigger = 48|0x100U, /*!< XBARA_OUT48 output assigned to ENC clear/snapshot */ + kXbaraOutputFTM0_FAULT3 = 49|0x100U, /*!< XBARA_OUT49 output assigned to FTM0 fault 3 */ + kXbaraOutputFTM1_FAULT1 = 50|0x100U, /*!< XBARA_OUT50 output assigned to FTM1 fault 1 */ + kXbaraOutputRESERVED51 = 51|0x100U, /*!< XBARA_OUT51 output is reserved. */ + kXbaraOutputRESERVED52 = 52|0x100U, /*!< XBARA_OUT52 output is reserved. */ + kXbaraOutputRESERVED53 = 53|0x100U, /*!< XBARA_OUT53 output is reserved. */ + kXbaraOutputRESERVED54 = 54|0x100U, /*!< XBARA_OUT54 output is reserved. */ + kXbaraOutputRESERVED55 = 55|0x100U, /*!< XBARA_OUT55 output is reserved. */ + kXbaraOutputRESERVED56 = 56|0x100U, /*!< XBARA_OUT56 output is reserved. */ + kXbaraOutputRESERVED57 = 57|0x100U, /*!< XBARA_OUT57 output is reserved. */ + kXbaraOutputEWM_IN = 58|0x100U, /*!< XBARA_OUT58 output assigned to EWM input */ + kXbarbOutputAOI_IN0 = 0|0x200U, /*!< XBARB_OUT0 output assigned to AOI input0 */ + kXbarbOutputAOI_IN1 = 1|0x200U, /*!< XBARB_OUT1 output assigned to AOI input1 */ + kXbarbOutputAOI_IN2 = 2|0x200U, /*!< XBARB_OUT2 output assigned to AOI input2 */ + kXbarbOutputAOI_IN3 = 3|0x200U, /*!< XBARB_OUT3 output assigned to AOI input3 */ + kXbarbOutputAOI_IN4 = 4|0x200U, /*!< XBARB_OUT4 output assigned to AOI input4 */ + kXbarbOutputAOI_IN5 = 5|0x200U, /*!< XBARB_OUT5 output assigned to AOI input5 */ + kXbarbOutputAOI_IN6 = 6|0x200U, /*!< XBARB_OUT6 output assigned to AOI input6 */ + kXbarbOutputAOI_IN7 = 7|0x200U, /*!< XBARB_OUT7 output assigned to AOI input7 */ + kXbarbOutputAOI_IN8 = 8|0x200U, /*!< XBARB_OUT8 output assigned to AOI input8 */ + kXbarbOutputAOI_IN9 = 9|0x200U, /*!< XBARB_OUT9 output assigned to AOI input9 */ + kXbarbOutputAOI_IN10 = 10|0x200U, /*!< XBARB_OUT10 output assigned to AOI input10 */ + kXbarbOutputAOI_IN11 = 11|0x200U, /*!< XBARB_OUT11 output assigned to AOI input11 */ + kXbarbOutputAOI_IN12 = 12|0x200U, /*!< XBARB_OUT12 output assigned to AOI input12 */ + kXbarbOutputAOI_IN13 = 13|0x200U, /*!< XBARB_OUT13 output assigned to AOI input13 */ + kXbarbOutputAOI_IN14 = 14|0x200U, /*!< XBARB_OUT14 output assigned to AOI input14 */ + kXbarbOutputAOI_IN15 = 15|0x200U, /*!< XBARB_OUT15 output assigned to AOI input15 */ +#elif defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLL15) + kXbaraOutputDMAMUX18 = 0|0x100U, /*!< XBARA_OUT0 output assigned to DMAMUX slot 18 */ + kXbaraOutputDMAMUX19 = 1|0x100U, /*!< XBARA_OUT1 output assigned to DMAMUX slot 19 */ + kXbaraOutputDMAMUX20 = 2|0x100U, /*!< XBARA_OUT2 output assigned to DMAMUX slot 20 */ + kXbaraOutputDMAMUX21 = 3|0x100U, /*!< XBARA_OUT3 output assigned to DMAMUX slot 21 */ + kXbaraOutputXB_OUT4 = 4|0x100U, /*!< XBARA_OUT4 output assigned to XBAROUT4 output pin */ + kXbaraOutputXB_OUT5 = 5|0x100U, /*!< XBARA_OUT5 output assigned to XBAROUT5 output pin */ + kXbaraOutputXB_OUT6 = 6|0x100U, /*!< XBARA_OUT6 output assigned to XBAROUT6 output pin */ + kXbaraOutputXB_OUT7 = 7|0x100U, /*!< XBARA_OUT7 output assigned to XBAROUT7 output pin */ + kXbaraOutputXB_OUT8 = 8|0x100U, /*!< XBARA_OUT8 output assigned to XBAROUT8 output pin */ + kXbaraOutputXB_OUT9 = 9|0x100U, /*!< XBARA_OUT9 output assigned to XBAROUT9 output pin */ + kXbaraOutputXB_OUT10 = 10|0x100U, /*!< XBARA_OUT10 output assigned to XBAROUT10 output pin */ + kXbaraOutputXB_OUT11 = 11|0x100U, /*!< XBARA_OUT11 output assigned to XBAROUT11 output pin */ + kXbaraOutputADCA_TRIG = 12|0x100U, /*!< XBARA_OUT12 output assigned to ADC converter A trigger */ + kXbaraOutputADCB_TRIG = 13|0x100U, /*!< XBARA_OUT13 output assigned to ADC converter B trigger */ + kXbaraOutputRESERVED14 = 14|0x100U, /*!< XBARA_OUT14 output is reserved. */ + kXbaraOutputDAC_12B_SYNC = 15|0x100U, /*!< XBARA_OUT15 output assigned to DAC synchronisation trigger */ + kXbaraOutputCMP0 = 16|0x100U, /*!< XBARA_OUT16 output assigned to CMP0 window/sample */ + kXbaraOutputCMP1 = 17|0x100U, /*!< XBARA_OUT17 output assigned to CMP1 window/sample */ + kXbaraOutputCMP2 = 18|0x100U, /*!< XBARA_OUT18 output assigned to CMP2 window/sample */ + kXbaraOutputCMP3 = 19|0x100U, /*!< XBARA_OUT19 output assigned to CMP3 window/sample */ + kXbaraOutputPWMA0_EXTA = 20|0x100U, /*!< XBARA_OUT20 output assigned to PWMA channel 0 external control A */ + kXbaraOutputPWMA1_EXTA = 21|0x100U, /*!< XBARA_OUT21 output assigned to PWMA channel 1 external control A */ + kXbaraOutputPWMA2_EXTA = 22|0x100U, /*!< XBARA_OUT22 output assigned to PWMA channel 2 external control A */ + kXbaraOutputPWMA3_EXTA = 23|0x100U, /*!< XBARA_OUT23 output assigned to PWMA channel 3 external control A */ + kXbaraOutputPWMA0_EXT_SYNC = 24|0x100U, /*!< XBARA_OUT24 output assigned to PWMA channel 0 external synchronization */ + kXbaraOutputPWMA1_EXT_SYNC = 25|0x100U, /*!< XBARA_OUT25 output assigned to PWMA channel 1 external synchronization */ + kXbaraOutputPWMA2_EXT_SYNC = 26|0x100U, /*!< XBARA_OUT26 output assigned to PWMA channel 2 external synchronization */ + kXbaraOutputPWMA3_EXT_SYNC = 27|0x100U, /*!< XBARA_OUT27 output assigned to PWMA channel 3 external synchronization */ + kXbaraOutputPWMA_EXT_CLK = 28|0x100U, /*!< XBARA_OUT28 output assigned to PWMA external clock */ + kXbaraOutputPWMA_FAULT0 = 29|0x100U, /*!< XBARA_OUT29 output assigned to PWMA fault 0 */ + kXbaraOutputPWMA_FAULT1 = 30|0x100U, /*!< XBARA_OUT30 output assigned to PWMA fault 1 */ + kXbaraOutputPWMA_FAULT2 = 31|0x100U, /*!< XBARA_OUT31 output assigned to PWMA fault 2 */ + kXbaraOutputPWMA_FAULT3 = 32|0x100U, /*!< XBARA_OUT32 output assigned to PWMA fault 3 */ + kXbaraOutputPWMA_FORCE = 33|0x100U, /*!< XBARA_OUT33 output assigned to PWMA external output force */ + kXbaraOutputFTM0_TRIG2 = 34|0x100U, /*!< XBARA_OUT34 output assigned to FTM0 hardware trigger 2 */ + kXbaraOutputFTM1_TRIG2 = 35|0x100U, /*!< XBARA_OUT35 output assigned to FTM1 hardware trigger 2 */ + kXbaraOutputRESERVED36 = 36|0x100U, /*!< XBARA_OUT36 output is reserved. */ + kXbaraOutputFTM3_TRIG2 = 37|0x100U, /*!< XBARA_OUT37 output assigned to FTM3 hardware trigger 2 */ + kXbaraOutputPDB0_IN_CH_12 = 38|0x100U, /*!< XBARA_OUT38 output assigned to PDB0 trigger option 12 */ + kXbaraOutputRESERVED39 = 39|0x100U, /*!< XBARA_OUT39 output is reserved. */ + kXbaraOutputRESERVED40 = 40|0x100U, /*!< XBARA_OUT40 output is reserved. */ + kXbaraOutputPDB1_IN_CH_12 = 41|0x100U, /*!< XBARA_OUT41 output assigned to PDB1 trigger option 12 */ + kXbaraOutputSIM_XOR_FTM1_CH1_FTM1_CH2 = 42|0x100U, /*!< XBARA_OUT42 output assigned to SIM XOR of FTM1_CH1 and FTM1_CH0 pins and XBARA output 42 */ + kXbaraOutputRESERVED43 = 43|0x100U, /*!< XBARA_OUT43 output is reserved. */ + kXbaraOutputENC_PHA = 44|0x100U, /*!< XBARA_OUT44 output assigned to ENC quadrature waveform phase A */ + kXbaraOutputENC_PHB = 45|0x100U, /*!< XBARA_OUT45 output assigned to ENC quadrature waveform phase B */ + kXbaraOutputENC_INDEX = 46|0x100U, /*!< XBARA_OUT46 output assigned to ENC refresh/reload */ + kXbaraOutputENC_HOME = 47|0x100U, /*!< XBARA_OUT47 output assigned to ENC home position */ + kXbaraOutputENC_CAP_Trigger = 48|0x100U, /*!< XBARA_OUT48 output assigned to ENC clear/snapshot */ + kXbaraOutputFTM0_FAULT3 = 49|0x100U, /*!< XBARA_OUT49 output assigned to FTM0 fault 3 */ + kXbaraOutputFTM1_FAULT1 = 50|0x100U, /*!< XBARA_OUT50 output assigned to FTM1 fault 1 */ + kXbaraOutputRESERVED51 = 51|0x100U, /*!< XBARA_OUT51 output is reserved. */ + kXbaraOutputFTM3_FAULT3 = 52|0x100U, /*!< XBARA_OUT52 output assigned to FTM3 fault 3 */ + kXbaraOutputRESERVED53 = 53|0x100U, /*!< XBARA_OUT53 output is reserved. */ + kXbaraOutputRESERVED54 = 54|0x100U, /*!< XBARA_OUT54 output is reserved. */ + kXbaraOutputRESERVED55 = 55|0x100U, /*!< XBARA_OUT55 output is reserved. */ + kXbaraOutputRESERVED56 = 56|0x100U, /*!< XBARA_OUT56 output is reserved. */ + kXbaraOutputRESERVED57 = 57|0x100U, /*!< XBARA_OUT57 output is reserved. */ + kXbaraOutputEWM_IN = 58|0x100U, /*!< XBARA_OUT58 output assigned to EWM input */ + kXbarbOutputAOI_IN0 = 0|0x200U, /*!< XBARB_OUT0 output assigned to AOI input0 */ + kXbarbOutputAOI_IN1 = 1|0x200U, /*!< XBARB_OUT1 output assigned to AOI input1 */ + kXbarbOutputAOI_IN2 = 2|0x200U, /*!< XBARB_OUT2 output assigned to AOI input2 */ + kXbarbOutputAOI_IN3 = 3|0x200U, /*!< XBARB_OUT3 output assigned to AOI input3 */ + kXbarbOutputAOI_IN4 = 4|0x200U, /*!< XBARB_OUT4 output assigned to AOI input4 */ + kXbarbOutputAOI_IN5 = 5|0x200U, /*!< XBARB_OUT5 output assigned to AOI input5 */ + kXbarbOutputAOI_IN6 = 6|0x200U, /*!< XBARB_OUT6 output assigned to AOI input6 */ + kXbarbOutputAOI_IN7 = 7|0x200U, /*!< XBARB_OUT7 output assigned to AOI input7 */ + kXbarbOutputAOI_IN8 = 8|0x200U, /*!< XBARB_OUT8 output assigned to AOI input8 */ + kXbarbOutputAOI_IN9 = 9|0x200U, /*!< XBARB_OUT9 output assigned to AOI input9 */ + kXbarbOutputAOI_IN10 = 10|0x200U, /*!< XBARB_OUT10 output assigned to AOI input10 */ + kXbarbOutputAOI_IN11 = 11|0x200U, /*!< XBARB_OUT11 output assigned to AOI input11 */ + kXbarbOutputAOI_IN12 = 12|0x200U, /*!< XBARB_OUT12 output assigned to AOI input12 */ + kXbarbOutputAOI_IN13 = 13|0x200U, /*!< XBARB_OUT13 output assigned to AOI input13 */ + kXbarbOutputAOI_IN14 = 14|0x200U, /*!< XBARB_OUT14 output assigned to AOI input14 */ + kXbarbOutputAOI_IN15 = 15|0x200U, /*!< XBARB_OUT15 output assigned to AOI input15 */ +#else + #error "No valid CPU defined!" +#endif +} xbar_output_signal_t; + + +#endif /* __FSL_XBAR_SIGNALS_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ + |