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# TI/Luminary Stellaris LM3S chip family
# Luminary chips support both JTAG and SWD transports.
# Adapt based on what transport is active.
source [find target/swj-dp.tcl]
# For now we ignore the SPI and UART options, which
# are usable only for ISP style initial flash programming.
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME lm3s
}
# CPU TAP ID 0x1ba00477 for early Sandstorm parts
# CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
# CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest)
# ... we'll ignore the JTAG version field, rather than list every
# chip revision that turns up.
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x0ba00477
}
# SWD DAP, and JTAG TAP, take same params for now;
# ... even though SWD ignores all except TAPID, and
# JTAG shouldn't need anything more then irlen. (and TAPID).
swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
-expected-id $_CPUTAPID -ignore-version
if { [info exists WORKAREASIZE ] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
# default to 8K working area
set _WORKAREASIZE 0x2000
}
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
# 8K working area at base of ram, not backed up
#
# NOTE: you may need or want to reconfigure the work area;
# some parts have just 6K, and you may want to use other
# addresses (at end of mem not beginning) or back it up.
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
# JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
# LM3S parts don't support RTCK
#
# NOTE: this may be increased by a reset-init handler, after it
# configures and enables the PLL. Or you might need to decrease
# this, if you're using a slower clock.
adapter_khz 500
source [find mem_helper.tcl]
$_TARGETNAME configure -event reset-start {
adapter_khz 500
#
# When nRST is asserted on most Stellaris devices, it clears some of
# the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
# and OpenOCD depends on those TRMs. So we won't use SRST on those
# chips. (Only power-on reset should affect debug state, beyond a
# few specified bits; not the chip's nRST input, wired to SRST.)
#
# REVISIT current errata specs don't seem to cover this issue.
# Do we have more details than this email?
# https://lists.berlios.de/pipermail
# /openocd-development/2008-August/003065.html
#
set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)]
if {$device_class == 0 || $device_class == 1 || $device_class == 3} {
# Sandstorm, Fury and DustDevil are able to use NVIC SYSRESETREQ
cortex_m3 reset_config sysresetreq
} else {
# Tempest and newer default to using NVIC VECTRESET
# this does mean a reset-init event handler is required to reset
# any peripherals
cortex_m3 reset_config vectreset
}
}
# flash configuration ... autodetects sizes, autoprobed
flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME
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