blob: 2373c19fe9e9c64419711106b47941c3057c43d8 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
|
set PIO_PER 0x00 ;# Enable Register
set PIO_PDR 0x04 ;# Disable Register
set PIO_PSR 0x08 ;# Status Register
set PIO_OER 0x10 ;# Output Enable Register
set PIO_ODR 0x14 ;# Output Disable Register
set PIO_OSR 0x18 ;# Output Status Register
set PIO_IFER 0x20 ;# Glitch Input Filter Enable
set PIO_IFDR 0x24 ;# Glitch Input Filter Disable
set PIO_IFSR 0x28 ;# Glitch Input Filter Status
set PIO_SODR 0x30 ;# Set Output Data Register
set PIO_CODR 0x34 ;# Clear Output Data Register
set PIO_ODSR 0x38 ;# Output Data Status Register
set PIO_PDSR 0x3c ;# Pin Data Status Register
set PIO_IER 0x40 ;# Interrupt Enable Register
set PIO_IDR 0x44 ;# Interrupt Disable Register
set PIO_IMR 0x48 ;# Interrupt Mask Register
set PIO_ISR 0x4c ;# Interrupt Status Register
set PIO_MDER 0x50 ;# Multi-driver Enable Register
set PIO_MDDR 0x54 ;# Multi-driver Disable Register
set PIO_MDSR 0x58 ;# Multi-driver Status Register
set PIO_PUDR 0x60 ;# Pull-up Disable Register
set PIO_PUER 0x64 ;# Pull-up Enable Register
set PIO_PUSR 0x68 ;# Pull-up Status Register
set PIO_ASR 0x70 ;# Peripheral A Select Register
set PIO_BSR 0x74 ;# Peripheral B Select Register
set PIO_ABSR 0x78 ;# AB Status Register
set PIO_OWER 0xa0 ;# Output Write Enable Register
set PIO_OWDR 0xa4 ;# Output Write Disable Register
set PIO_OWSR 0xa8 ;# Output Write Status Register
|
