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# DANGER!!!! early work in progress for this PCB/target.
#
# The most basic operations work well enough that it is
# useful to have this in the repository for cooperation
# alpha testing purposes.
#
# TI AM3517
#
# http://focus.ti.com/docs/prod/folders/print/am3517.html
# http://processors.wiki.ti.com/index.php/Debug_Access_Port_(DAP)
# http://processors.wiki.ti.com/index.php?title=How_to_Find_the_Silicon_Revision_of_your_OMAP35x
# Slooow during startup
adapter_khz 10
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME am3517
}
set JRC_TAPID 0
set DAP_TAPID 0x0b86802f
# Subsidiary TAP: CoreSight Debug Access Port (DAP)
if { [info exists DAP_TAPID ] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x0b6d602f
}
# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
if { [info exists JRC_TAPID ] } {
set _JRC_TAPID $JRC_TAPID
} else {
set _JRC_TAPID 0x0b7ae02f
}
# ICEpick-C ... used to route Cortex, and more not shown here
source [find target/icepick.cfg]
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_DAP_TAPID -disable
jtag configure $_CHIPNAME.dap -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 3"
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
-expected-id $_JRC_TAPID
# GDB target: Cortex-A8, using DAP
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap
# SRAM: 64K at 0x4020.0000; use the first 16K
$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
###################
# the reset sequence is event-driven
# and kind of finicky...
# some TCK tycles are required to activate the DEBUG power domain
jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
# have the DAP "always" be active
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
proc omap3_dbginit {target} {
# General Cortex A8 debug initialisation
cortex_a8 dbginit
# Enable DBGU signal for OMAP353x
$target mww phys 0x5401d030 0x00002000
}
# be absolutely certain the JTAG clock will work with the worst-case
# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
# OK to speed up *after* PLL and clock tree setup.
$_TARGETNAME configure -event "reset-start" { adapter_khz 10}
# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick
# would issue. RST_DPLL3 (4) is a cold reset.
set PRM_RSTCTRL 0x48307250
$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 2"
$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME; adapter_khz 1000"
reset_config trst_only
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