path: root/src/target/nds32_cmd.c

/***************************************************************************
 *   Copyright (C) 2013 Andes Technology                                   *
 *   Hsiangkai Wang <hkwang@andestech.com>                                 *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
 ***************************************************************************/

#ifdef HAVE_CONFIG_H
#include "config.h"
#endif

#include <helper/command.h>
#include "nds32.h"
#include "nds32_aice.h"
#include "nds32_disassembler.h"

extern struct nds32_edm_operation nds32_edm_ops[NDS32_EDM_OPERATION_MAX_NUM];
extern uint32_t nds32_edm_ops_num;

static const char *const NDS_MEMORY_ACCESS_NAME[] = {
	"BUS",
	"CPU",
};

static const char *const NDS_MEMORY_SELECT_NAME[] = {
	"AUTO",
	"MEM",
	"ILM",
	"DLM",
};

COMMAND_HANDLER(handle_nds32_dssim_command)
{
	struct target *target = get_current_target(CMD_CTX);
	struct nds32 *nds32 = target_to_nds32(target);

	if (!is_nds32(nds32)) {
		command_print(CMD_CTX, "current target isn't an Andes core");
		return ERROR_FAIL;
	}

	if (CMD_ARGC > 0) {
		if (strcmp(CMD_ARGV[0], "on") == 0)
			nds32->step_isr_enable = true;
		if (strcmp(CMD_ARGV[0], "off") == 0)
			nds32->step_isr_enable = false;
	}

	command_print(CMD_CTX, "%s: $INT_MASK.DSSIM: %d", target_name(target),
			nds32->step_isr_enable);

	return ERROR_OK;
}

COMMAND_HANDLER(handle_nds32_memory_access_command)
{
	struct target *target = get_current_target(CMD_CTX);
	struct nds32 *nds32 = target_to_nds32(target);
	struct aice_port_s *aice = target_to_aice(target);
	struct nds32_memory *memory = &(nds32->memory);

	if (!is_nds32(nds32)) {
		command_print(CMD_CTX, "current target isn't an Andes core");
		return ERROR_FAIL;
	}

	if (CMD_ARGC > 0) {
		if (strcmp(CMD_ARGV[0], "bus") == 0)
			memory->access_channel = NDS_MEMORY_ACC_BUS;
		else if (strcmp(CMD_ARGV[0], "cpu") == 0)
			memory->access_channel = NDS_MEMORY_ACC_CPU;
		else /* default access channel is NDS_MEMORY_ACC_CPU */
			memory->access_channel = NDS_MEMORY_ACC_CPU;

		LOG_DEBUG("memory access channel is changed to %s",
				NDS_MEMORY_ACCESS_NAME[memory->access_channel]);

		aice_memory_access(aice, memory->access_channel);
	} else {
		command_print(CMD_CTX, "%s: memory access channel: %s",
				target_name(target),
				NDS_MEMORY_ACCESS_NAME[memory->access_channel]);
	}

	return ERROR_OK;
}

COMMAND_HANDLER(handle_nds32_memory_mode_command)
{
	struct target *target = get_current_target(CMD_CTX);
	struct nds32 *nds32 = target_to_nds32(target);
	struct aice_port_s *aice = target_to_aice(target);

	if (!is_nds32(nds32)) {
		command_print(CMD_CTX, "current target isn't an Andes core");
		return ERROR_FAIL;
	}

	if (CMD_ARGC > 0) {

		if (nds32->edm.access_control == false) {
			command_print(CMD_CTX, "%s does not support ACC_CTL. "
					"Set memory mode to MEMORY", target_name(target));
			nds32->memory.mode = NDS_MEMORY_SELECT_MEM;
		} else if (nds32->edm.direct_acces