From d4e195ad1b544b0396cab4c70437371958769196 Mon Sep 17 00:00:00 2001 From: Paul Fertser Date: Sun, 13 Oct 2013 19:15:24 +0400 Subject: Remove jtag_rclk from target configs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some boards might have RCLK omitted from the JTAG connector and if the interface claims support for it, OpenOCD will end up trying to use RCLK while it's actually impossible. This is a "cd tcl/target; sed -i s/jtag_rclk/adapter_khz/g *" patch. Change-Id: Iee7337107bc1457966b104389ba9db75a9c860b4 Signed-off-by: Paul Fertser Reviewed-on: http://openocd.zylin.com/1695 Tested-by: jenkins Reviewed-by: Spencer Oliver Reviewed-by: Mathias Küster --- tcl/target/str912.cfg | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'tcl/target/str912.cfg') diff --git a/tcl/target/str912.cfg b/tcl/target/str912.cfg index 599a254a..38545ac9 100644 --- a/tcl/target/str912.cfg +++ b/tcl/target/str912.cfg @@ -13,7 +13,7 @@ if { [info exists ENDIAN] } { } # jtag speed. We need to stick to 16kHz until we've finished reset. -jtag_rclk 16 +adapter_khz 16 adapter_nsrst_delay 100 jtag_ntrst_delay 100 @@ -48,11 +48,11 @@ jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BST set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e -$_TARGETNAME configure -event reset-start { jtag_rclk 16 } +$_TARGETNAME configure -event reset-start { adapter_khz 16 } $_TARGETNAME configure -event reset-init { # We can increase speed now that we know the target is halted. - #jtag_rclk 3000 + #adapter_khz 3000 # -- Enable 96K RAM # PFQBC enabled / DTCM & AHB wait-states disabled -- cgit v1.2.3-18-g5258