From c3ec1940b52e5d3f47c5c96bea2430b4444d83ea Mon Sep 17 00:00:00 2001
From: Karl Palsson <karlp@tweak.net.au>
Date: Fri, 21 Nov 2014 22:14:57 +0000
Subject: stm32l: split l0/l1 support no jtag, different HSI settings

L0 is cortex m0+, so different id codes, SWD only, different addresses
for the clock speedup.  It has no endian options, no boundary scan.

Removed all L0 specific portions from L1 files, and renamed files to clarify
their purpose.  The deprecated stm32lx_stlink.cfg is kept as is, as it is only
around for backwards compatibility with prior releases.

Tested on STM32L053 Discovery and STM32L151 Discovery.

Has _not_ been tested with jtag on L1.

Change-Id: I8eea890d2f92a302d9e9c8a8832d218ee1b6bcfc
Signed-off-by: Karl Palsson <karlp@tweak.net.au>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2405
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-by: Juha Niskanen <juha.niskanen@haltian.com>
---
 tcl/target/stm32l0.cfg | 73 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)
 create mode 100644 tcl/target/stm32l0.cfg

(limited to 'tcl/target/stm32l0.cfg')

diff --git a/tcl/target/stm32l0.cfg b/tcl/target/stm32l0.cfg
new file mode 100644
index 00000000..fc2751e9
--- /dev/null
+++ b/tcl/target/stm32l0.cfg
@@ -0,0 +1,73 @@
+#
+# M0+ devices only have SW-DP, but swj-dp code works, just don't
+# set any jtag related features
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32l0
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 8kB (max ram on smallest part)
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x2000
+}
+
+# JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is ~2MHz, so use F_JTAG max = 333kHz
+adapter_khz 300
+
+adapter_nsrst_delay 100
+
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+    # Arm, m0+, non-multidrop.
+    # http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka16088.html
+    set _CPUTAPID 0x0bc11477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}
+
+proc stm32l0_enable_HSI16 {} {
+	# Enable HSI16 as clock source
+	echo "STM32L0: Enabling HSI16"
+
+	# Set HSI16ON in RCC_CR (leave MSI enabled)
+	mww 0x40021000 0x00000101
+
+	# Set HSI16 as SYSCLK (RCC_CFGR)
+	mww 0x4002100c 0x00000001
+
+	# Increase speed
+	adapter_khz 2500
+}
+
+$_TARGETNAME configure -event reset-init {
+	stm32l0_enable_HSI16
+}
+
+$_TARGETNAME configure -event reset-start {
+	adapter_khz 300
+}
-- 
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