From d4e195ad1b544b0396cab4c70437371958769196 Mon Sep 17 00:00:00 2001 From: Paul Fertser Date: Sun, 13 Oct 2013 19:15:24 +0400 Subject: Remove jtag_rclk from target configs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some boards might have RCLK omitted from the JTAG connector and if the interface claims support for it, OpenOCD will end up trying to use RCLK while it's actually impossible. This is a "cd tcl/target; sed -i s/jtag_rclk/adapter_khz/g *" patch. Change-Id: Iee7337107bc1457966b104389ba9db75a9c860b4 Signed-off-by: Paul Fertser Reviewed-on: http://openocd.zylin.com/1695 Tested-by: jenkins Reviewed-by: Spencer Oliver Reviewed-by: Mathias Küster --- tcl/target/omap3530.cfg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tcl/target/omap3530.cfg') diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg index 0e20852c..f9dcf7cb 100644 --- a/tcl/target/omap3530.cfg +++ b/tcl/target/omap3530.cfg @@ -62,8 +62,8 @@ proc omap3_dbginit {target} { # be absolutely certain the JTAG clock will work with the worst-case # 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in. # OK to speed up *after* PLL and clock tree setup. -jtag_rclk 1000 -$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 } +adapter_khz 1000 +$_TARGETNAME configure -event "reset-start" { adapter_khz 1000 } # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset # ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick -- cgit v1.2.3-18-g5258