From c45de8073d027f1a4d39640dc140666f27960e3b Mon Sep 17 00:00:00 2001 From: kc8apf Date: Sat, 13 Dec 2008 06:25:50 +0000 Subject: Change tap_state naming to be consistent with SVF documentation. Courtesy of Dick Hollenbeck git-svn-id: svn://svn.berlios.de/openocd/trunk@1232 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/target/arm11.c | 16 +- src/target/arm11_dbgtap.c | 60 +++---- src/target/arm720t.c | 136 +++++++-------- src/target/arm7_9_common.c | 8 +- src/target/arm7tdmi.c | 172 +++++++++---------- src/target/arm920t.c | 402 ++++++++++++++++++++++----------------------- src/target/arm926ejs.c | 6 +- src/target/arm966e.c | 52 +++--- src/target/arm9tdmi.c | 212 ++++++++++++------------ src/target/cortex_swjdp.c | 248 ++++++++++++++-------------- src/target/embeddedice.c | 10 +- src/target/etb.c | 6 +- src/target/etm.c | 4 +- src/target/feroceon.c | 74 ++++----- src/target/mips_ejtag.c | 6 +- src/target/mips_m4k.c | 218 ++++++++++++------------ src/target/xscale.c | 64 ++++---- 17 files changed, 847 insertions(+), 847 deletions(-) (limited to 'src/target') diff --git a/src/target/arm11.c b/src/target/arm11.c index 38961bd7..39a6817d 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -393,7 +393,7 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11) arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1); arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2); - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD); + arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); } else { @@ -627,7 +627,7 @@ void arm11_leave_debug_state(arm11_common_t * arm11) arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1); arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2); - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD); + arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); } arm11_record_register_history(arm11); @@ -735,7 +735,7 @@ int arm11_halt(struct target_s *target) return ERROR_OK; } - arm11_add_IR(arm11, ARM11_HALT, TAP_RTI); + arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE); if((retval = jtag_execute_queue()) != ERROR_OK) { @@ -841,7 +841,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b arm11_leave_debug_state(arm11); - arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI); + arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE); if((retval = jtag_execute_queue()) != ERROR_OK) { @@ -956,7 +956,7 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre arm11_leave_debug_state(arm11); - arm11_add_IR(arm11, ARM11_RESTART, TAP_RTI); + arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE); if((retval = jtag_execute_queue()) != ERROR_OK) { @@ -1571,7 +1571,7 @@ int arm11_examine(struct target_s *target) arm11_setup_field(arm11, 32, NULL, &arm11->device_id, &idcode_field); - arm11_add_dr_scan_vc(1, &idcode_field, TAP_PD); + arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE); /* check DIDR */ @@ -1584,7 +1584,7 @@ int arm11_examine(struct target_s *target) arm11_setup_field(arm11, 32, NULL, &arm11->didr, chain0_fields + 0); arm11_setup_field(arm11, 8, NULL, &arm11->implementor, chain0_fields + 1); - arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_RTI); + arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE); if ((retval=jtag_execute_queue())!=ERROR_OK) return retval; @@ -1832,7 +1832,7 @@ arm11_common_t * arm11_find_target(const char * arg) { jtag_tap_t *tap; target_t * t; - + tap = jtag_TapByString( arg ); if( !tap ){ return NULL; diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c index a6660cdd..a433a7e1 100644 --- a/src/target/arm11_dbgtap.c +++ b/src/target/arm11_dbgtap.c @@ -38,13 +38,13 @@ enum tap_state arm11_move_pi_to_si_via_ci[] = { - TAP_E2I, TAP_UI, TAP_SDS, TAP_SIS, TAP_CI, TAP_SI + TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT }; int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state) { - if (cmd_queue_cur_state == TAP_PI) + if (cmd_queue_cur_state == TAP_IRPAUSE) jtag_add_pathmove(asizeof(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci); jtag_add_ir_scan(num_fields, fields, state); @@ -53,12 +53,12 @@ int arm11_add_ir_scan_vc(int num_fields, scan_field_t *fields, enum tap_state st enum tap_state arm11_move_pd_to_sd_via_cd[] = { - TAP_E2D, TAP_UD, TAP_SDS, TAP_CD, TAP_SD + TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT }; int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, enum tap_state state) { - if (cmd_queue_cur_state == TAP_PD) + if (cmd_queue_cur_state == TAP_DRPAUSE) jtag_add_pathmove(asizeof(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd); jtag_add_dr_scan(num_fields, fields, state); @@ -104,7 +104,7 @@ void arm11_add_IR(arm11_common_t * arm11, u8 instr, enum tap_state state) jtag_tap_t *tap; tap = arm11->jtag_info.tap; if( tap == NULL ){ - /* FIX!!!! error is logged, but not propagated back up the call stack... */ + /* FIX!!!! error is logged, but not propagated back up the call stack... */ LOG_ERROR( "tap is null here! This is bad!"); return; } @@ -120,7 +120,7 @@ void arm11_add_IR(arm11_common_t * arm11, u8 instr, enum tap_state state) arm11_setup_field(arm11, 5, &instr, NULL, &field); - arm11_add_ir_scan_vc(1, &field, state == -1 ? TAP_PI : state); + arm11_add_ir_scan_vc(1, &field, state == -1 ? TAP_IRPAUSE : state); } /** Verify shifted out data from Scan Chain Register (SCREG) @@ -135,8 +135,8 @@ static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s if (v != 0x10) { - LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v); - return ERROR_FAIL; + LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v); + return ERROR_FAIL; } JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v); @@ -179,7 +179,7 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, enum tap_state sta field.in_handler = arm11_in_handler_SCAN_N; - arm11_add_dr_scan_vc(1, &field, state == -1 ? TAP_PD : state); + arm11_add_dr_scan_vc(1, &field, state == -1 ? TAP_DRPAUSE : state); } /** Write an instruction into the ITR register @@ -194,7 +194,7 @@ void arm11_add_debug_SCAN_N(arm11_common_t * arm11, u8 chain, enum tap_state sta * \remarks By default this ends with Run-Test/Idle state * and causes the instruction to be executed. If * a subsequent write to DTR is needed before - * executing the instruction then TAP_PD should be + * executing the instruction then TAP_DRPAUSE should be * passed to \p state. * * \remarks This adds to the JTAG command queue but does \em not execute it. @@ -208,7 +208,7 @@ void arm11_add_debug_INST(arm11_common_t * arm11, u32 inst, u8 * flag, enum tap_ arm11_setup_field(arm11, 32, &inst, NULL, itr + 0); arm11_setup_field(arm11, 1, NULL, flag, itr + 1); - arm11_add_dr_scan_vc(asizeof(itr), itr, state == -1 ? TAP_RTI : state); + arm11_add_dr_scan_vc(asizeof(itr), itr, state == -1 ? TAP_IDLE : state); } /** Read the Debug Status and Control Register (DSCR) @@ -231,12 +231,12 @@ u32 arm11_read_DSCR(arm11_common_t * arm11) arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field); - arm11_add_dr_scan_vc(1, &chain1_field, TAP_PD); + arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE); jtag_execute_queue(); if (arm11->last_dscr != dscr) - JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr); + JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr); arm11->last_dscr = dscr; @@ -262,7 +262,7 @@ void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr) arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field); - arm11_add_dr_scan_vc(1, &chain1_field, TAP_PD); + arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE); jtag_execute_queue(); @@ -369,13 +369,13 @@ void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count) while (count--) { - arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_RTI); + arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_IDLE); while (1) { u8 flag; - arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_RTI : TAP_PD); + arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE); jtag_execute_queue(); @@ -416,7 +416,7 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data { arm11_add_IR(arm11, ARM11_ITRSEL, -1); - arm11_add_debug_INST(arm11, opcode, NULL, TAP_PD); + arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE); arm11_add_IR(arm11, ARM11_EXTEST, -1); @@ -436,7 +436,7 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data { Data = *data; - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_RTI); + arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE); jtag_execute_queue(); JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry); @@ -452,7 +452,7 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data { Data = 0; - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD); + arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); jtag_execute_queue(); JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry); @@ -462,18 +462,18 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data /** JTAG path for arm11_run_instr_data_to_core_noack * - * The repeated TAP_RTI's do not cause a repeated execution + * The repeated TAP_IDLE's do not cause a repeated execution * if passed without leaving the state. * * Since this is more than 7 bits (adjustable via adding more - * TAP_RTI's) it produces an artificial delay in the lower + * TAP_IDLE's) it produces an artificial delay in the lower * layer (FT2232) that is long enough to finish execution on * the core but still shorter than any manually inducible delays. * */ enum tap_state arm11_MOVE_PD_RTI_PD_with_delay[] = { - TAP_E2D, TAP_UD, TAP_RTI, TAP_RTI, TAP_RTI, TAP_SDS, TAP_CD, TAP_SD + TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT }; @@ -497,7 +497,7 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 { arm11_add_IR(arm11, ARM11_ITRSEL, -1); - arm11_add_debug_INST(arm11, opcode, NULL, TAP_PD); + arm11_add_debug_INST(arm11, opcode, NULL, TAP_DRPAUSE); arm11_add_IR(arm11, ARM11_EXTEST, -1); @@ -517,13 +517,13 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 if (count) { - jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_PD); + jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); jtag_add_pathmove(asizeof(arm11_MOVE_PD_RTI_PD_with_delay), arm11_MOVE_PD_RTI_PD_with_delay); } else { - jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_RTI); + jtag_add_dr_scan(asizeof(chain5_fields), chain5_fields, TAP_IDLE); } } @@ -532,7 +532,7 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 chain5_fields[0].out_value = 0; chain5_fields[1].in_value = ReadyPos++; - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_PD); + arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE); jtag_execute_queue(); @@ -586,7 +586,7 @@ void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * da { arm11_add_IR(arm11, ARM11_ITRSEL, -1); - arm11_add_debug_INST(arm11, opcode, NULL, TAP_RTI); + arm11_add_debug_INST(arm11, opcode, NULL, TAP_IDLE); arm11_add_IR(arm11, ARM11_INTEST, -1); @@ -604,7 +604,7 @@ void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * da { do { - arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_RTI : TAP_PD); + arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE); jtag_execute_queue(); JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry); @@ -699,11 +699,11 @@ void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t AddressOut = 0; } - do + do { JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW); - arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_PD); + arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE); jtag_execute_queue(); JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready); diff --git a/src/target/arm720t.c b/src/target/arm720t.c index 1d9efc04..d4eb6bd5 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -64,7 +64,7 @@ target_type_t arm720t_target = .assert_reset = arm7_9_assert_reset, .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm720t_soft_reset_halt, - + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, .read_memory = arm720t_read_memory, @@ -72,7 +72,7 @@ target_type_t arm720t_target = .bulk_write_memory = arm7_9_bulk_write_memory, .checksum_memory = arm7_9_checksum_memory, .blank_check_memory = arm7_9_blank_check_memory, - + .run_algorithm = armv4_5_run_algorithm, .add_breakpoint = arm7_9_add_breakpoint, @@ -96,10 +96,10 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c scan_field_t fields[2]; u8 out_buf[4]; u8 instruction_buf = instruction; - + buf_set_u32(out_buf, 0, 32, flip_u32(out, 32)); - - jtag_add_end_state(TAP_PD); + + jtag_add_end_state(TAP_DRPAUSE); if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) { return retval; @@ -108,7 +108,7 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c { return retval; } - + fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = &instruction_buf; @@ -135,7 +135,7 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c } fields[1].in_check_value = NULL; fields[1].in_check_mask = NULL; - + jtag_add_dr_scan(2, fields, -1); if (clock) @@ -171,7 +171,7 @@ int arm720t_read_cp15(target_t *target, u32 opcode, u32 *value) arm720t_scan_cp15(target, 0x0, NULL, 0, 1); /* "EXECUTE" stage (3), CDATA is read */ arm720t_scan_cp15(target, ARMV4_5_NOP, value, 1, 1); - + return ERROR_OK; } @@ -197,9 +197,9 @@ u32 arm720t_get_ttb(target_t *target) arm720t_read_cp15(target, 0xee120f10, &ttb); jtag_execute_queue(); - + ttb &= 0xffffc000; - + return ttb; } @@ -210,10 +210,10 @@ void arm720t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_ /* read cp15 control register */ arm720t_read_cp15(target, 0xee110f10, &cp15_control); jtag_execute_queue(); - + if (mmu) cp15_control &= ~0x1U; - + if (d_u_cache || i_cache) cp15_control &= ~0x4U; @@ -227,13 +227,13 @@ void arm720t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_c /* read cp15 control register */ arm720t_read_cp15(target, 0xee110f10, &cp15_control); jtag_execute_queue(); - + if (mmu) cp15_control |= 0x1U; - + if (d_u_cache || i_cache) cp15_control |= 0x4U; - + arm720t_write_cp15(target, 0xee010f10, cp15_control); } @@ -243,7 +243,7 @@ void arm720t_post_debug_entry(target_t *target) arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; arm720t_common_t *arm720t = arm7tdmi->arch_info; - + /* examine cp15 control reg */ arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg); jtag_execute_queue(); @@ -265,7 +265,7 @@ void arm720t_pre_restore_context(target_t *target) arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; arm720t_common_t *arm720t = arm7tdmi->arch_info; - + /* restore i/d fault status and address register */ arm720t_write_cp15(target, 0xee050f10, arm720t->fsr_reg); arm720t_write_cp15(target, 0xee060f10, arm720t->far_reg); @@ -277,35 +277,35 @@ int arm720t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, ar arm7_9_common_t *arm7_9; arm7tdmi_common_t *arm7tdmi; arm720t_common_t *arm720t; - + if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { return -1; } - + arm7_9 = armv4_5->arch_info; if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC) { return -1; } - + arm7tdmi = arm7_9->arch_info; if (arm7tdmi->common_magic != ARM7TDMI_COMMON_MAGIC) { return -1; } - + arm720t = arm7tdmi->arch_info; if (arm720t->common_magic != ARM720T_COMMON_MAGIC) { return -1; } - + *armv4_5_p = armv4_5; *arm7_9_p = arm7_9; *arm7tdmi_p = arm7tdmi; *arm720t_p = arm720t; - + return ERROR_OK; } @@ -315,18 +315,18 @@ int arm720t_arch_state(struct target_s *target) arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; arm720t_common_t *arm720t = arm7tdmi->arch_info; - - char *state[] = + + char *state[] = { "disabled", "enabled" }; - + if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { LOG_ERROR("BUG: called for a non-ARMv4/5 target"); exit(-1); } - + LOG_USER("target halted in %s state due to %s, current mode: %s\n" "cpsr: 0x%8.8x pc: 0x%8.8x\n" "MMU: %s, Cache: %s", @@ -337,7 +337,7 @@ int arm720t_arch_state(struct target_s *target) buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), state[arm720t->armv4_5_mmu.mmu_enabled], state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]); - + return ERROR_OK; } @@ -348,23 +348,23 @@ int arm720t_read_memory(struct target_s *target, u32 address, u32 size, u32 coun arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; arm720t_common_t *arm720t = arm7tdmi->arch_info; - + /* disable cache, but leave MMU enabled */ if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) arm720t_disable_mmu_caches(target, 0, 1, 0); - + retval = arm7_9_read_memory(target, address, size, count, buffer); - + if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) arm720t_enable_mmu_caches(target, 0, 1, 0); - + return retval; } int arm720t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) { int retval; - + if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK) return retval; @@ -379,12 +379,12 @@ int arm720t_soft_reset_halt(struct target_s *target) arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info; arm720t_common_t *arm720t = arm7tdmi->arch_info; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; - + if ((retval = target_halt(target)) != ERROR_OK) { return retval; } - + long long then=timeval_ms(); int timeout; while (!(timeout=((timeval_ms()-then)>1000))) @@ -413,22 +413,22 @@ int arm720t_soft_reset_halt(struct target_s *target) LOG_ERROR("Failed to halt CPU after 1 sec"); return ERROR_TARGET_TIMEOUT; } - + target->state = TARGET_HALTED; - + /* SVC, ARM state, IRQ and FIQ disabled */ buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3); armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; - + /* start fetching from 0x0 */ buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0); armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].valid = 1; - + armv4_5->core_mode = ARMV4_5_MODE_SVC; armv4_5->core_state = ARMV4_5_STATE_ARM; - + arm720t_disable_mmu_caches(target, 1, 1, 1); arm720t->armv4_5_mmu.mmu_enabled = 0; arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; @@ -438,21 +438,21 @@ int arm720t_soft_reset_halt(struct target_s *target) { return retval; } - + return ERROR_OK; } int arm720t_init_target(struct command_context_s *cmd_ctx, struct target_s *target) { arm7tdmi_init_target(cmd_ctx, target); - + return ERROR_OK; - + } int arm720t_quit(void) { - + return ERROR_OK; } @@ -460,15 +460,15 @@ int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap { arm7tdmi_common_t *arm7tdmi = &arm720t->arm7tdmi_common; arm7_9_common_t *arm7_9 = &arm7tdmi->arm7_9_common; - + arm7tdmi_init_arch_info(target, arm7tdmi, tap, variant); arm7tdmi->arch_info = arm720t; arm720t->common_magic = ARM720T_COMMON_MAGIC; - + arm7_9->post_debug_entry = arm720t_post_debug_entry; arm7_9->pre_restore_context = arm720t_pre_restore_context; - + arm720t->armv4_5_mmu.armv4_5_cache.ctype = -1; arm720t->armv4_5_mmu.get_ttb = arm720t_get_ttb; arm720t->armv4_5_mmu.read_memory = arm7_9_read_memory; @@ -477,14 +477,14 @@ int arm720t_init_arch_info(target_t *target, arm720t_common_t *arm720t, jtag_tap arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches; arm720t->armv4_5_mmu.has_tiny_pages = 0; arm720t->armv4_5_mmu.mmu_enabled = 0; - + return ERROR_OK; } int arm720t_target_create(struct target_s *target, Jim_Interp *interp) { arm720t_common_t *arm720t = calloc(1,sizeof(arm720t_common_t)); - + arm720t_init_arch_info(target, arm720t, target->tap, target->variant); return ERROR_OK; @@ -494,10 +494,10 @@ int arm720t_register_commands(struct command_context_s *cmd_ctx) { int retval; command_t *arm720t_cmd; - - + + retval = arm7tdmi_register_commands(cmd_ctx); - + arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands"); register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register [value]"); @@ -510,7 +510,7 @@ int arm720t_register_commands(struct command_context_s *cmd_ctx) register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word "); register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word "); register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte "); - + return ERROR_OK; } @@ -529,9 +529,9 @@ int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch command_print(cmd_ctx, "current target isn't an ARM720t target"); return ERROR_OK; } - + jtag_info = &arm7_9->jtag_info; - + if (target->state != TARGET_HALTED) { command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); @@ -556,7 +556,7 @@ int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch { return retval; } - + command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value); } else if (argc == 2) @@ -575,7 +575,7 @@ int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch } int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) -{ +{ target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; @@ -588,20 +588,20 @@ int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char command_print(cmd_ctx, "current target isn't an ARM720t target"); return ERROR_OK; } - + jtag_info = &arm7_9->jtag_info; - + if (target->state != TARGET_HALTED) { command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); return ERROR_OK; } - + return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu); } int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) -{ +{ target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; @@ -614,20 +614,20 @@ int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char * command_print(cmd_ctx, "current target isn't an ARM720t target"); return ERROR_OK; } - + jtag_info = &arm7_9->jtag_info; - + if (target->state != TARGET_HALTED) { command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); return ERROR_OK; } - + return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu); } int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) -{ +{ target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; @@ -640,14 +640,14 @@ int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char * command_print(cmd_ctx, "current target isn't an ARM720t target"); return ERROR_OK; } - + jtag_info = &arm7_9->jtag_info; - + if (target->state != TARGET_HALTED) { command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); return ERROR_OK; } - + return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu); } diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index edadcb2b..357daa39 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -584,7 +584,7 @@ int arm7_9_execute_sys_speed(struct target_s *target) reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* set RESTART instruction */ - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); if (arm7_9->need_bypass_before_restart) { arm7_9->need_bypass_before_restart = 0; arm_jtag_set_instr(jtag_info, 0xf, NULL); @@ -630,7 +630,7 @@ int arm7_9_execute_fast_sys_speed(struct target_s *target) reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; /* set RESTART instruction */ - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); if (arm7_9->need_bypass_before_restart) { arm7_9->need_bypass_before_restart = 0; arm_jtag_set_instr(jtag_info, 0xf, NULL); @@ -1492,14 +1492,14 @@ int arm7_9_restart_core(struct target_s *target) arm_jtag_t *jtag_info = &arm7_9->jtag_info; /* set RESTART instruction */ - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); if (arm7_9->need_bypass_before_restart) { arm7_9->need_bypass_before_restart = 0; arm_jtag_set_instr(jtag_info, 0xf, NULL); } arm_jtag_set_instr(jtag_info, 0x4, NULL); - jtag_add_runtest(1, TAP_RTI); + jtag_add_runtest(1, TAP_IDLE); return jtag_execute_queue(); } diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c index 2e9d28d8..be98c8e1 100644 --- a/src/target/arm7tdmi.c +++ b/src/target/arm7tdmi.c @@ -55,7 +55,7 @@ int arm7tdmi_quit(void); /* target function declarations */ int arm7tdmi_poll(struct target_s *target); int arm7tdmi_halt(target_t *target); - + target_type_t arm7tdmi_target = { .name = "arm7tdmi", @@ -74,15 +74,15 @@ target_type_t arm7tdmi_target = .soft_reset_halt = arm7_9_soft_reset_halt, .get_gdb_reg_list = armv4_5_get_gdb_reg_list, - + .read_memory = arm7_9_read_memory, .write_memory = arm7_9_write_memory, .bulk_write_memory = arm7_9_bulk_write_memory, .checksum_memory = arm7_9_checksum_memory, .blank_check_memory = arm7_9_blank_check_memory, - + .run_algorithm = armv4_5_run_algorithm, - + .add_breakpoint = arm7_9_add_breakpoint, .remove_breakpoint = arm7_9_remove_breakpoint, .add_watchpoint = arm7_9_add_watchpoint, @@ -101,7 +101,7 @@ int arm7tdmi_examine_debug_reason(target_t *target) /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - + /* only check the debug reason if we don't know it already */ if ((target->debug_reason != DBG_REASON_DBGRQ) && (target->debug_reason != DBG_REASON_SINGLESTEP)) @@ -109,8 +109,8 @@ int arm7tdmi_examine_debug_reason(target_t *target) scan_field_t fields[2]; u8 databus[4]; u8 breakpoint; - - jtag_add_end_state(TAP_PD); + + jtag_add_end_state(TAP_DRPAUSE); fields[0].tap = arm7_9->jtag_info.tap; fields[0].num_bits = 1; @@ -121,7 +121,7 @@ int arm7tdmi_examine_debug_reason(target_t *target) fields[0].in_check_mask = NULL; fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - + fields[1].tap = arm7_9->jtag_info.tap; fields[1].num_bits = 32; fields[1].out_value = NULL; @@ -131,30 +131,30 @@ int arm7tdmi_examine_debug_reason(target_t *target) fields[1].in_check_mask = NULL; fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - + if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK) { return retval; } arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL); - jtag_add_dr_scan(2, fields, TAP_PD); + jtag_add_dr_scan(2, fields, TAP_DRPAUSE); if((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } - + fields[0].in_value = NULL; fields[0].out_value = &breakpoint; fields[1].in_value = NULL; fields[1].out_value = databus; - - jtag_add_dr_scan(2, fields, TAP_PD); + + jtag_add_dr_scan(2, fields, TAP_DRPAUSE); if (breakpoint & 1) - target->debug_reason = DBG_REASON_WATCHPOINT; + target->debug_reason = DBG_REASON_WATCHPOINT; else - target->debug_reason = DBG_REASON_BREAKPOINT; + target->debug_reason = DBG_REASON_BREAKPOINT; } return ERROR_OK; @@ -164,13 +164,13 @@ static int arm7tdmi_num_bits[]={1, 32}; static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int breakpoint) { u32 values[2]={breakpoint, flip_u32(out, 32)}; - + jtag_add_dr_out(jtag_info->tap, 2, arm7tdmi_num_bits, values, -1); - + jtag_add_runtest(0, -1); return ERROR_OK; @@ -179,10 +179,10 @@ static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int /* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */ static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *deprecated, int breakpoint) { - jtag_add_end_state(TAP_PD); + jtag_add_end_state(TAP_DRPAUSE); arm_jtag_scann(jtag_info, 0x1); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - + return arm7tdmi_clock_out_inner(jtag_info, out, breakpoint); } @@ -192,13 +192,13 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) int retval = ERROR_OK; scan_field_t fields[2]; - jtag_add_end_state(TAP_PD); + jtag_add_end_state(TAP_DRPAUSE); if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) { return retval; } arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - + fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = NULL; @@ -208,7 +208,7 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) fields[0].in_check_mask = NULL; fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - + fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = NULL; @@ -222,14 +222,14 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) jtag_add_dr_scan(2, fields, -1); jtag_add_runtest(0, -1); - + #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { if((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } - + if (in) { LOG_DEBUG("in: 0x%8.8x", *in); @@ -247,19 +247,19 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) /* clock the target, and read the databus * the *in pointer points to a buffer where elements of 'size' bytes * are stored in big (be==1) or little (be==0) endianness - */ + */ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be) { int retval = ERROR_OK; scan_field_t fields[2]; - jtag_add_end_state(TAP_PD); + jtag_add_end_state(TAP_DRPAUSE); if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) { return retval; } arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - + fields[0].tap = jtag_info->tap; fields[0].num_bits = 1; fields[0].out_value = NULL; @@ -269,7 +269,7 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, fields[0].in_check_mask = NULL; fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - + fields[1].tap = jtag_info->tap; fields[1].num_bits = 32; fields[1].out_value = NULL; @@ -294,14 +294,14 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, jtag_add_dr_scan(2, fields, -1); jtag_add_runtest(0, -1); - + #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { if((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } - + if (in) { LOG_DEBUG("in: 0x%8.8x", *(u32*)in); @@ -322,10 +322,10 @@ void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - - /* save r0 before using it and put system in ARM state + + /* save r0 before using it and put system in ARM state * to allow common handling of ARM and THUMB debugging */ - + /* fetch STR r0, [r0] */ arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0); @@ -333,7 +333,7 @@ void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc) /* nothing fetched, STR r0, [r0] in Execute (2) */ arm7tdmi_clock_data_in(jtag_info, r0); - /* MOV r0, r15 fetched, STR in Decode */ + /* MOV r0, r15 fetched, STR in Decode */ arm7tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0); @@ -349,22 +349,22 @@ void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc) arm7tdmi_clock_out(jtag_info, 0x0, NULL, 0); /* nothing fetched, data from previous cycle is written to register */ arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0); - + /* fetch BX */ arm7tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), NULL, 0); /* NOP fetched, BX in Decode, MOV in Execute */ arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0); /* NOP fetched, BX in Execute (1) */ arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0); - + jtag_execute_queue(); - + /* fix program counter: * MOV r0, r15 was the 4th instruction (+6) * reading PC in Thumb state gives address of instruction + 4 */ *pc -= 0xa; - + } void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16]) @@ -374,7 +374,7 @@ void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16]) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + /* STMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK */ @@ -405,7 +405,7 @@ void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf u32 *buf_u32 = buffer; u16 *buf_u16 = buffer; u8 *buf_u8 = buffer; - + /* STMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK */ @@ -435,7 +435,7 @@ void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf } } } - + } void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr) @@ -444,10 +444,10 @@ void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + /* MRS r0, cpsr */ arm7tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), NULL, 0); - + /* STR r0, [r15] */ arm7tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), NULL, 0); /* fetch NOP, STR in DECODE stage */ @@ -465,7 +465,7 @@ void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr); /* MSR1 fetched */ @@ -496,9 +496,9 @@ void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr); - + /* MSR fetched */ arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), NULL, 0); /* NOP fetched, MSR in DECODE */ @@ -507,7 +507,7 @@ void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr) arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); /* nothing fetched, MSR in EXECUTE (2) */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); - + } void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16]) @@ -517,7 +517,7 @@ void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16]) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + /* LDMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK */ @@ -535,7 +535,7 @@ void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16]) arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0); } arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0); - + } void arm7tdmi_load_word_regs(target_t *target, u32 mask) @@ -558,7 +558,7 @@ void arm7tdmi_load_hword_reg(target_t *target, int num) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + /* put system-speed load half-word into the pipeline */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1); @@ -591,7 +591,7 @@ void arm7tdmi_store_word_regs(target_t *target, u32 mask) arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1); arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), NULL, 0); - + } void arm7tdmi_store_hword_reg(target_t *target, int num) @@ -628,7 +628,7 @@ void arm7tdmi_write_pc(target_t *target, u32 pc) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + /* LDMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK */ @@ -655,7 +655,7 @@ void arm7tdmi_branch_resume(target_t *target) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1); arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0); @@ -664,7 +664,7 @@ void arm7tdmi_branch_resume(target_t *target) void arm7tdmi_branch_resume_thumb(target_t *target) { LOG_DEBUG("-"); - + /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; @@ -687,15 +687,15 @@ void arm7tdmi_branch_resume_thumb(target_t *target) /* Branch and eXchange */ arm7tdmi_clock_out(jtag_info, ARMV4_5_BX(0), NULL, 0); - + embeddedice_read_reg(dbg_stat); - + /* fetch NOP, BX in DECODE stage */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); - + /* target is now in Thumb state */ embeddedice_read_reg(dbg_stat); - + /* fetch NOP, BX in EXECUTE stage (1st cycle) */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); @@ -712,17 +712,17 @@ void arm7tdmi_branch_resume_thumb(target_t *target) arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0); /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */ arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0); - + arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0); arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0); embeddedice_read_reg(dbg_stat); - + arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 1); arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), NULL, 0); } - + void arm7tdmi_build_reg_cache(target_t *target) { reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); @@ -745,10 +745,10 @@ int arm7tdmi_examine(struct target_s *target) reg_cache_t *t=embeddedice_build_reg_cache(target, arm7_9); if (t==NULL) return ERROR_FAIL; - + (*cache_p) = t; arm7_9->eice_cache = (*cache_p); - + if (arm7_9->etm_ctx) { arm_jtag_t *jtag_info = &arm7_9->jtag_info; @@ -771,16 +771,16 @@ int arm7tdmi_examine(struct target_s *target) int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target) { - + arm7tdmi_build_reg_cache(target); - + return ERROR_OK; - + } int arm7tdmi_quit(void) { - + return ERROR_OK; } @@ -788,56 +788,56 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_ { armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; - + arm7_9 = &arm7tdmi->arm7_9_common; armv4_5 = &arm7_9->armv4_5_common; - + /* prepare JTAG information for the new target */ arm7_9->jtag_info.tap = tap; arm7_9->jtag_info.scann_size = 4; - + /* register arch-specific functions */ arm7_9->examine_debug_reason = arm7tdmi_examine_debug_reason; arm7_9->change_to_arm = arm7tdmi_change_to_arm; arm7_9->read_core_regs = arm7tdmi_read_core_regs; arm7_9->read_core_regs_target_buffer = arm7tdmi_read_core_regs_target_buffer; arm7_9->read_xpsr = arm7tdmi_read_xpsr; - + arm7_9->write_xpsr = arm7tdmi_write_xpsr; arm7_9->write_xpsr_im8 = arm7tdmi_write_xpsr_im8; arm7_9->write_core_regs = arm7tdmi_write_core_regs; - + arm7_9->load_word_regs = arm7tdmi_load_word_regs; arm7_9->load_hword_reg = arm7tdmi_load_hword_reg; arm7_9->load_byte_reg = arm7tdmi_load_byte_reg; - + arm7_9->store_word_regs = arm7tdmi_store_word_regs; arm7_9->store_hword_reg = arm7tdmi_store_hword_reg; arm7_9->store_byte_reg = arm7tdmi_store_byte_reg; - + arm7_9->write_pc = arm7tdmi_write_pc; arm7_9->branch_resume = arm7tdmi_branch_resume; arm7_9->branch_resume_thumb = arm7tdmi_branch_resume_thumb; - + arm7_9->enable_single_step = arm7_9_enable_eice_step; arm7_9->disable_single_step = arm7_9_disable_eice_step; - + arm7_9->pre_debug_entry = NULL; arm7_9->post_debug_entry = NULL; - + arm7_9->pre_restore_context = NULL; arm7_9->post_restore_context = NULL; - + /* initialize arch-specific breakpoint handling */ arm7_9->arm_bkpt = 0xdeeedeee; arm7_9->thumb_bkpt = 0xdeee; - + arm7_9->dbgreq_adjust_pc = 2; arm7_9->arch_info = arm7tdmi; arm7tdmi->arch_info = NULL; arm7tdmi->common_magic = ARM7TDMI_COMMON_MAGIC; - + if (variant) { arm7tdmi->variant = strdup(variant); @@ -846,7 +846,7 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_ { arm7tdmi->variant = strdup(""); } - + arm7_9_init_arch_info(target, arm7_9); return ERROR_OK; @@ -857,11 +857,11 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_ int arm7tdmi_target_create( struct target_s *target, Jim_Interp *interp ) { arm7tdmi_common_t *arm7tdmi; - + arm7tdmi = calloc(1,sizeof(arm7tdmi_common_t)); - + arm7tdmi_init_arch_info(target, arm7tdmi, target->tap, target->variant); - + return ERROR_OK; } @@ -869,9 +869,9 @@ int arm7tdmi_target_create( struct target_s *target, Jim_Interp *interp ) int arm7tdmi_register_commands(struct command_context_s *cmd_ctx) { int retval; - + retval = arm7_9_register_commands(cmd_ctx); - + return retval; } diff --git a/src/target/arm920t.c b/src/target/arm920t.c index 76e54f72..2aed9966 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -73,7 +73,7 @@ target_type_t arm920t_target = .assert_reset = arm7_9_assert_reset, .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm920t_soft_reset_halt, - + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, .read_memory = arm920t_read_memory, @@ -81,7 +81,7 @@ target_type_t arm920t_target = .bulk_write_memory = arm7_9_bulk_write_memory, .checksum_memory = arm7_9_checksum_memory, .blank_check_memory = arm7_9_blank_check_memory, - + .run_algorithm = armv4_5_run_algorithm, .add_breakpoint = arm7_9_add_breakpoint, @@ -105,8 +105,8 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value) u8 access_type_buf = 1; u8 reg_addr_buf = reg_addr & 0x3f; u8 nr_w_buf = 0; - - jtag_add_end_state(TAP_RTI); + + jtag_add_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0xf); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); @@ -149,7 +149,7 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value) fields[3].in_check_mask = NULL; fields[3].in_handler = NULL; fields[3].in_handler_priv = NULL; - + jtag_add_dr_scan(4, fields, -1); fields[1].in_handler_priv = value; @@ -175,10 +175,10 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value) u8 reg_addr_buf = reg_addr & 0x3f; u8 nr_w_buf = 1; u8 value_buf[4]; - + buf_set_u32(value_buf, 0, 32, value); - - jtag_add_end_state(TAP_RTI); + + jtag_add_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0xf); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); @@ -221,7 +221,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value) fields[3].in_check_mask = NULL; fields[3].in_handler = NULL; fields[3].in_handler_priv = NULL; - + jtag_add_dr_scan(4, fields, -1); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ @@ -242,11 +242,11 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode) u8 reg_addr_buf = 0x0; u8 nr_w_buf = 0; u8 cp15_opcode_buf[4]; - - jtag_add_end_state(TAP_RTI); + + jtag_add_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0xf); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - + buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode); fields[0].tap = jtag_info->tap; @@ -296,13 +296,13 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode) retval = arm7_9_execute_sys_speed(target); if (retval != ERROR_OK) return retval; - + if ((retval = jtag_execute_queue()) != ERROR_OK) { LOG_ERROR("failed executing JTAG queue, exiting"); return retval; } - + return ERROR_OK; } @@ -315,18 +315,18 @@ int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address /* load address into R1 */ regs[1] = address; - arm9tdmi_write_core_regs(target, 0x2, regs); - - /* read-modify-write CP15 test state register + arm9tdmi_write_core_regs(target, 0x2, regs); + + /* read-modify-write CP15 test state register * to enable interpreted access mode */ - arm920t_read_cp15_physical(target, 0x1e, &cp15c15); + arm920t_read_cp15_physical(target, 0x1e, &cp15c15); jtag_execute_queue(); cp15c15 |= 1; /* set interpret mode */ arm920t_write_cp15_physical(target, 0x1e, cp15c15); /* execute CP15 instruction and ARM load (reading from coprocessor) */ arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1)); - + /* disable interpreted access mode */ cp15c15 &= ~1U; /* clear interpret mode */ arm920t_write_cp15_physical(target, 0x1e, cp15c15); @@ -335,7 +335,7 @@ int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address regs_p[0] = value; arm9tdmi_read_core_regs(target, 0x1, regs_p); jtag_execute_queue(); - + #ifdef _DEBUG_INSTRUCTION_EXECUTION_ LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value); #endif @@ -360,7 +360,7 @@ int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value, regs[1] = address; arm9tdmi_write_core_regs(target, 0x3, regs); - /* read-modify-write CP15 test state register + /* read-modify-write CP15 test state register * to enable interpreted access mode */ arm920t_read_cp15_physical(target, 0x1e, &cp15c15); jtag_execute_queue(); @@ -380,10 +380,10 @@ int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value, if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; - + ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1; - + return ERROR_OK; } @@ -405,13 +405,13 @@ void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_ /* read cp15 control register */ arm920t_read_cp15_physical(target, 0x2, &cp15_control); jtag_execute_queue(); - + if (mmu) cp15_control &= ~0x1U; - + if (d_u_cache) cp15_control &= ~0x4U; - + if (i_cache) cp15_control &= ~0x1000U; @@ -425,16 +425,16 @@ void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_c /* read cp15 control register */ arm920t_read_cp15_physical(target, 0x2, &cp15_control); jtag_execute_queue(); - + if (mmu) cp15_control |= 0x1U; - + if (d_u_cache) cp15_control |= 0x4U; - + if (i_cache) cp15_control |= 0x1000U; - + arm920t_write_cp15_physical(target, 0x2, cp15_control); } @@ -445,7 +445,7 @@ void arm920t_post_debug_entry(target_t *target) arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; arm920t_common_t *arm920t = arm9tdmi->arch_info; - + /* examine cp15 control reg */ arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg); jtag_execute_queue(); @@ -469,13 +469,13 @@ void arm920t_post_debug_entry(target_t *target) arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr); arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far); arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far); - + LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x", - arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far); + arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far); if (arm920t->preserve_cache) { - /* read-modify-write CP15 test state register + /* read-modify-write CP15 test state register * to disable I/D-cache linefills */ arm920t_read_cp15_physical(target, 0x1e, &cp15c15); jtag_execute_queue(); @@ -491,14 +491,14 @@ void arm920t_pre_restore_context(target_t *target) arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; arm920t_common_t *arm920t = arm9tdmi->arch_info; - + /* restore i/d fault status and address register */ arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0); arm920t_write_cp15_interpreted(target, 0xee050f30, arm920t->i_fsr, 0x0); arm920t_write_cp15_interpreted(target, 0xee060f10, arm920t->d_far, 0x0); arm920t_write_cp15_interpreted(target, 0xee060f30, arm920t->i_far, 0x0); - - /* read-modify-write CP15 test state register + + /* read-modify-write CP15 test state register * to reenable I/D-cache linefills */ if (arm920t->preserve_cache) { @@ -515,35 +515,35 @@ int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, ar arm7_9_common_t *arm7_9; arm9tdmi_common_t *arm9tdmi; arm920t_common_t *arm920t; - + if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { return -1; } - + arm7_9 = armv4_5->arch_info; if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC) { return -1; } - + arm9tdmi = arm7_9->arch_info; if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC) { return -1; } - + arm920t = arm9tdmi->arch_info; if (arm920t->common_magic != ARM920T_COMMON_MAGIC) { return -1; } - + *armv4_5_p = armv4_5; *arm7_9_p = arm7_9; *arm9tdmi_p = arm9tdmi; *arm920t_p = arm920t; - + return ERROR_OK; } @@ -553,18 +553,18 @@ int arm920t_arch_state(struct target_s *target) arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; arm920t_common_t *arm920t = arm9tdmi->arch_info; - - char *state[] = + + char *state[] = { "disabled", "enabled" }; - + if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { LOG_ERROR("BUG: called for a non-ARMv4/5 target"); exit(-1); } - + LOG_USER( "target halted in %s state due to %s, current mode: %s\n" "cpsr: 0x%8.8x pc: 0x%8.8x\n" "MMU: %s, D-Cache: %s, I-Cache: %s", @@ -574,18 +574,18 @@ int arm920t_arch_state(struct target_s *target) buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32), state[arm920t->armv4_5_mmu.mmu_enabled], - state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], + state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]); - + return ERROR_OK; } int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer) { int retval; - + retval = arm7_9_read_memory(target, address, size, count, buffer); - + return retval; } @@ -596,7 +596,7 @@ int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 cou arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; arm920t_common_t *arm920t = arm9tdmi->arch_info; - + if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK) return retval; @@ -615,7 +615,7 @@ int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 cou if (cb == 3) armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa, size, count, buffer); } - + if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled) { LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line"); @@ -634,12 +634,12 @@ int arm920t_soft_reset_halt(struct target_s *target) arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info; arm920t_common_t *arm920t = arm9tdmi->arch_info; reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; - + if((retval = target_halt(target)) != ERROR_OK) { return retval; } - + long long then=timeval_ms(); int timeout; while (!(timeout=((timeval_ms()-then)>1000))) @@ -669,22 +669,22 @@ int arm920t_soft_reset_halt(struct target_s *target) LOG_ERROR("Failed to halt CPU after 1 sec"); return ERROR_TARGET_TIMEOUT; } - + target->state = TARGET_HALTED; - + /* SVC, ARM state, IRQ and FIQ disabled */ buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3); armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1; armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1; - + /* start fetching from 0x0 */ buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0); armv4_5->core_cache->reg_list[15].dirty = 1; armv4_5->core_cache->reg_list[15].valid = 1; - + armv4_5->core_mode = ARMV4_5_MODE_SVC; armv4_5->core_state = ARMV4_5_STATE_ARM; - + arm920t_disable_mmu_caches(target, 1, 1, 1); arm920t->armv4_5_mmu.mmu_enabled = 0; arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0; @@ -694,21 +694,21 @@ int arm920t_soft_reset_halt(struct target_s *target) { return retval; } - + return ERROR_OK; } int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target) { arm9tdmi_init_target(cmd_ctx, target); - + return ERROR_OK; - + } int arm920t_quit(void) { - + return ERROR_OK; } @@ -716,17 +716,17 @@ int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap { arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common; arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common; - + /* initialize arm9tdmi specific info (including arm7_9 and armv4_5) */ arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant); arm9tdmi->arch_info = arm920t; arm920t->common_magic = ARM920T_COMMON_MAGIC; - + arm7_9->post_debug_entry = arm920t_post_debug_entry; arm7_9->pre_restore_context = arm920t_pre_restore_context; - + arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1; arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb; arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory; @@ -735,23 +735,23 @@ int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, jtag_tap arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches; arm920t->armv4_5_mmu.has_tiny_pages = 1; arm920t->armv4_5_mmu.mmu_enabled = 0; - + /* disabling linefills leads to lockups, so keep them enabled for now * this doesn't affect correctness, but might affect timing issues, if * important data is evicted from the cache during the debug session * */ arm920t->preserve_cache = 0; - + /* override hw single-step capability from ARM9TDMI */ arm7_9->has_single_step = 1; - + return ERROR_OK; } int arm920t_target_create(struct target_s *target, Jim_Interp *interp) { arm920t_common_t *arm920t = calloc(1,sizeof(arm920t_common_t)); - + arm920t_init_arch_info(target, arm920t, target->tap, target->variant); return ERROR_OK; @@ -761,10 +761,10 @@ int arm920t_register_commands(struct command_context_s *cmd_ctx) { int retval; command_t *arm920t_cmd; - - + + retval = arm9tdmi_register_commands(cmd_ctx); - + arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", NULL, COMMAND_ANY, "arm920t specific commands"); register_command(cmd_ctx, arm920t_cmd, "cp15", arm920t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register [value]"); @@ -804,30 +804,30 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c FILE *output; arm920t_cache_line_t d_cache[8][64], i_cache[8][64]; int segment, index; - + if (argc != 1) { command_print(cmd_ctx, "usage: arm920t read_cache "); return ERROR_OK; } - + if ((output = fopen(args[0], "w")) == NULL) { LOG_DEBUG("error opening cache content file"); return ERROR_OK; } - + for (i = 0; i < 16; i++) regs_p[i] = ®s[i]; - + if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK) { command_print(cmd_ctx, "current target isn't an ARM920t target"); return ERROR_OK; } - + jtag_info = &arm7_9->jtag_info; - + /* disable MMU and Caches */ arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl); if((retval = jtag_execute_queue()) != ERROR_OK) @@ -838,29 +838,29 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED); arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl); - /* read CP15 test state register */ + /* read CP15 test state register */ arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15); jtag_execute_queue(); - + /* read DCache content */ fprintf(output, "DCache:\n"); - - /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */ + + /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */ for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++) { fprintf(output, "\nsegment: %i\n----------", segment); - + /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */ regs[0] = 0x0 | (segment << 5); arm9tdmi_write_core_regs(target, 0x1, regs); - + /* set interpret mode */ cp15c15 |= 0x1; arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); - + /* D CAM Read, loads current victim into C15.C.D.Ind */ arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0)); - + /* read current victim */ arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind); @@ -877,16 +877,16 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c /* set interpret mode */ cp15c15 |= 0x1; arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); - + /* Write DCache victim */ arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0)); - + /* Read D RAM */ arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0)); - + /* Read D CAM */ arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0)); - + /* clear interpret mode */ cp15c15 &= ~0x1; arm920t_write_cp15_physical(target, 0x1e, cp15c15); @@ -899,19 +899,19 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c } d_cache[segment][index].cam = regs[9]; - + /* mask LFSR[6] */ regs[9] &= 0xfffffffe; fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid"); - + for (i = 1; i < 9; i++) { d_cache[segment][index].data[i] = regs[i]; fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]); } - + } - + /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */ regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26); arm9tdmi_write_core_regs(target, 0x1, regs); @@ -919,10 +919,10 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c /* set interpret mode */ cp15c15 |= 0x1; arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); - + /* Write DCache victim */ arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0)); - + /* clear interpret mode */ cp15c15 &= ~0x1; arm920t_write_cp15_physical(target, 0x1e, cp15c15); @@ -930,23 +930,23 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c /* read ICache content */ fprintf(output, "ICache:\n"); - - /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */ + + /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */ for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++) { fprintf(output, "segment: %i\n----------", segment); - + /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */ regs[0] = 0x0 | (segment << 5); arm9tdmi_write_core_regs(target, 0x1, regs); - + /* set interpret mode */ cp15c15 |= 0x1; arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); - + /* I CAM Read, loads current victim into C15.C.I.Ind */ arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0)); - + /* read current victim */ arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind); @@ -963,16 +963,16 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c /* set interpret mode */ cp15c15 |= 0x1; arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); - + /* Write ICache victim */ arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0)); - + /* Read I RAM */ arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0)); - + /* Read I CAM */ arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0)); - + /* clear interpret mode */ cp15c15 &= ~0x1; arm920t_write_cp15_physical(target, 0x1e, cp15c15); @@ -985,20 +985,20 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c } i_cache[segment][index].cam = regs[9]; - + /* mask LFSR[6] */ regs[9] &= 0xfffffffe; fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid"); - + for (i = 1; i < 9; i++) { i_cache[segment][index].data[i] = regs[i]; fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]); } - + } - - + + /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */ regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26); arm9tdmi_write_core_regs(target, 0x1, regs); @@ -1006,22 +1006,22 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c /* set interpret mode */ cp15c15 |= 0x1; arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); - + /* Write ICache victim */ arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0)); - + /* clear interpret mode */ cp15c15 &= ~0x1; arm920t_write_cp15_physical(target, 0x1e, cp15c15); } - + /* restore CP15 MMU and Cache settings */ arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved); - + command_print(cmd_ctx, "cache content successfully output to %s", args[0]); - + fclose(output); - + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; @@ -1036,7 +1036,7 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid; - + return ERROR_OK; } @@ -1058,30 +1058,30 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd u32 Dlockdown, Ilockdown; arm920t_tlb_entry_t d_tlb[64], i_tlb[64]; int victim; - + if (argc != 1) { command_print(cmd_ctx, "usage: arm920t read_mmu "); return ERROR_OK; } - + if ((output = fopen(args[0], "w")) == NULL) { LOG_DEBUG("error opening mmu content file"); return ERROR_OK; } - + for (i = 0; i < 16; i++) regs_p[i] = ®s[i]; - + if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK) { command_print(cmd_ctx, "current target isn't an ARM920t target"); return ERROR_OK; } - + jtag_info = &arm7_9->jtag_info; - + /* disable MMU and Caches */ arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl); if((retval = jtag_execute_queue()) != ERROR_OK) @@ -1092,27 +1092,27 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED); arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl); - /* read CP15 test state register */ + /* read CP15 test state register */ arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15); if((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } - /* prepare reading D TLB content + /* prepare reading D TLB content * */ - + /* set interpret mode */ cp15c15 |= 0x1; arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); - + /* Read D TLB lockdown */ arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0)); - + /* clear interpret mode */ cp15c15 &= ~0x1; arm920t_write_cp15_physical(target, 0x1e, cp15c15); - + /* read D TLB lockdown stored to r1 */ arm9tdmi_read_core_regs(target, 0x2, regs_p); if((retval = jtag_execute_queue()) != ERROR_OK) @@ -1120,63 +1120,63 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd return retval; } Dlockdown = regs[1]; - + for (victim = 0; victim < 64; victim += 8) { - /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] + /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] * base remains unchanged, victim goes through entries 0 to 63 */ regs[1] = (Dlockdown & 0xfc000000) | (victim << 20); arm9tdmi_write_core_regs(target, 0x2, regs); - + /* set interpret mode */ cp15c15 |= 0x1; arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); - + /* Write D TLB lockdown */ arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0)); - + /* Read D TLB CAM */ arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0)); - + /* clear interpret mode */ cp15c15 &= ~0x1; arm920t_write_cp15_physical(target, 0x1e, cp15c15); - + /* read D TLB CAM content stored to r2-r9 */ arm9tdmi_read_core_regs(target, 0x3fc, regs_p); if((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } - + for (i = 0; i < 8; i++) - d_tlb[victim + i].cam = regs[i + 2]; + d_tlb[victim + i].cam = regs[i + 2]; } for (victim = 0; victim < 64; victim++) { - /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] + /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] * base remains unchanged, victim goes through entries 0 to 63 */ regs[1] = (Dlockdown & 0xfc000000) | (victim << 20); arm9tdmi_write_core_regs(target, 0x2, regs); - + /* set interpret mode */ cp15c15 |= 0x1; arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); - + /* Write D TLB lockdown */ arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0)); - + /* Read D TLB RAM1 */ arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0)); /* Read D TLB RAM2 */ arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0)); - + /* clear interpret mode */ cp15c15 &= ~0x1; arm920t_write_cp15_physical(target, 0x1e, cp15c15); - + /* read D TLB RAM content stored to r2 and r3 */ arm9tdmi_read_core_regs(target, 0xc, regs_p); if((retval = jtag_execute_queue()) != ERROR_OK) @@ -1184,31 +1184,31 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd return retval; } - d_tlb[victim].ram1 = regs[2]; - d_tlb[victim].ram2 = regs[3]; + d_tlb[victim].ram1 = regs[2]; + d_tlb[victim].ram2 = regs[3]; } - + /* restore D TLB lockdown */ regs[1] = Dlockdown; arm9tdmi_write_core_regs(target, 0x2, regs); - + /* Write D TLB lockdown */ arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0)); - /* prepare reading I TLB content + /* prepare reading I TLB content * */ - + /* set interpret mode */ cp15c15 |= 0x1; arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); - + /* Read I TLB lockdown */ arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0)); - + /* clear interpret mode */ cp15c15 &= ~0x1; arm920t_write_cp15_physical(target, 0x1e, cp15c15); - + /* read I TLB lockdown stored to r1 */ arm9tdmi_read_core_regs(target, 0x2, regs_p); if((retval = jtag_execute_queue()) != ERROR_OK) @@ -1216,63 +1216,63 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd return retval; } Ilockdown = regs[1]; - + for (victim = 0; victim < 64; victim += 8) { - /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] + /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] * base remains unchanged, victim goes through entries 0 to 63 */ regs[1] = (Ilockdown & 0xfc000000) | (victim << 20); arm9tdmi_write_core_regs(target, 0x2, regs); - + /* set interpret mode */ cp15c15 |= 0x1; arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); - + /* Write I TLB lockdown */ arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0)); - + /* Read I TLB CAM */ arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0)); - + /* clear interpret mode */ cp15c15 &= ~0x1; arm920t_write_cp15_physical(target, 0x1e, cp15c15); - + /* read I TLB CAM content stored to r2-r9 */ arm9tdmi_read_core_regs(target, 0x3fc, regs_p); if((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } - + for (i = 0; i < 8; i++) - i_tlb[i + victim].cam = regs[i + 2]; + i_tlb[i + victim].cam = regs[i + 2]; } for (victim = 0; victim < 64; victim++) { - /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] + /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] * base remains unchanged, victim goes through entries 0 to 63 */ regs[1] = (Dlockdown & 0xfc000000) | (victim << 20); arm9tdmi_write_core_regs(target, 0x2, regs); - + /* set interpret mode */ cp15c15 |= 0x1; arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15); - + /* Write I TLB lockdown */ arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0)); - + /* Read I TLB RAM1 */ arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0)); /* Read I TLB RAM2 */ arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0)); - + /* clear interpret mode */ cp15c15 &= ~0x1; arm920t_write_cp15_physical(target, 0x1e, cp15c15); - + /* read I TLB RAM content stored to r2 and r3 */ arm9tdmi_read_core_regs(target, 0xc, regs_p); if((retval = jtag_execute_queue()) != ERROR_OK) @@ -1280,21 +1280,21 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd return retval; } - i_tlb[victim].ram1 = regs[2]; - i_tlb[victim].ram2 = regs[3]; + i_tlb[victim].ram1 = regs[2]; + i_tlb[victim].ram2 = regs[3]; } - + /* restore I TLB lockdown */ regs[1] = Ilockdown; arm9tdmi_write_core_regs(target, 0x2, regs); - + /* Write I TLB lockdown */ arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0)); - + /* restore CP15 MMU and Cache settings */ arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved); - /* output data to file */ + /* output data to file */ fprintf(output, "D TLB content:\n"); for (i = 0; i < 64; i++) { @@ -1306,11 +1306,11 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd { fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)"); } - + command_print(cmd_ctx, "mmu content successfully output to %s", args[0]); - + fclose(output); - + if (armv4_5_mode_to_number(armv4_5->core_mode)==-1) return ERROR_FAIL; @@ -1325,7 +1325,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid; ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid; - + return ERROR_OK; } int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) @@ -1343,9 +1343,9 @@ int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch command_print(cmd_ctx, "current target isn't an ARM920t target"); return ERROR_OK; } - + jtag_info = &arm7_9->jtag_info; - + if (target->state != TARGET_HALTED) { command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); @@ -1369,7 +1369,7 @@ int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch { return retval; } - + command_print(cmd_ctx, "%i: %8.8x", address, value); } else if (argc == 2) @@ -1402,9 +1402,9 @@ int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, c command_print(cmd_ctx, "current target isn't an ARM920t target"); return ERROR_OK; } - + jtag_info = &arm7_9->jtag_info; - + if (target->state != TARGET_HALTED) { command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); @@ -1424,7 +1424,7 @@ int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, c command_print(cmd_ctx, "couldn't execute %8.8x", opcode); return ERROR_OK; } - + command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value); } else if (argc == 2) @@ -1464,18 +1464,18 @@ int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *c arm7_9_common_t *arm7_9; arm9tdmi_common_t *arm9tdmi; arm920t_common_t *arm920t; - + if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK) { command_print(cmd_ctx, "current target isn't an ARM920t target"); return ERROR_OK; } - + return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache); } int arm920t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) -{ +{ target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; @@ -1488,20 +1488,20 @@ int arm920t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char command_print(cmd_ctx, "current target isn't an ARM920t target"); return ERROR_OK; } - + jtag_info = &arm7_9->jtag_info; - + if (target->state != TARGET_HALTED) { command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); return ERROR_OK; } - + return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu); } int arm920t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) -{ +{ target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; @@ -1514,20 +1514,20 @@ int arm920t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char * command_print(cmd_ctx, "current target isn't an ARM920t target"); return ERROR_OK; } - + jtag_info = &arm7_9->jtag_info; - + if (target->state != TARGET_HALTED) { command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); return ERROR_OK; } - + return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu); } int arm920t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc) -{ +{ target_t *target = get_current_target(cmd_ctx); armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; @@ -1540,14 +1540,14 @@ int arm920t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char * command_print(cmd_ctx, "current target isn't an ARM920t target"); return ERROR_OK; } - + jtag_info = &arm7_9->jtag_info; - + if (target->state != TARGET_HALTED) { command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); return ERROR_OK; } - + return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu); } diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index b812e984..c959f135 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -132,7 +132,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3 buf_set_u32(address_buf, 0, 14, address); - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) { return retval; @@ -222,7 +222,7 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u buf_set_u32(address_buf, 0, 14, address); buf_set_u32(value_buf, 0, 32, value); - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) { return retval; @@ -366,7 +366,7 @@ int arm926ejs_examine_debug_reason(target_t *target) default: LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason); target->debug_reason = DBG_REASON_DBGRQ; - /* if we fail here, we won't talk to the target and it will + /* if we fail here, we won't talk to the target and it will * be reported to be in the halted state */ retval = ERROR_TARGET_FAILURE; break; diff --git a/src/target/arm966e.c b/src/target/arm966e.c index 576be2e1..a7cee34f 100644 --- a/src/target/arm966e.c +++ b/src/target/arm966e.c @@ -74,9 +74,9 @@ target_type_t arm966e_target = .bulk_write_memory = arm7_9_bulk_write_memory, .checksum_memory = arm7_9_checksum_memory, .blank_check_memory = arm7_9_blank_check_memory, - + .run_algorithm = armv4_5_run_algorithm, - + .add_breakpoint = arm7_9_add_breakpoint, .remove_breakpoint = arm7_9_remove_breakpoint, .add_watchpoint = arm7_9_add_watchpoint, @@ -92,13 +92,13 @@ target_type_t arm966e_target = int arm966e_init_target(struct command_context_s *cmd_ctx, struct target_s *target) { arm9tdmi_init_target(cmd_ctx, target); - + return ERROR_OK; } int arm966e_quit(void) { - + return ERROR_OK; } @@ -106,25 +106,25 @@ int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, jtag_tap { arm9tdmi_common_t *arm9tdmi = &arm966e->arm9tdmi_common; arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common; - + arm9tdmi_init_arch_info(target, arm9tdmi, tap, variant); arm9tdmi->arch_info = arm966e; arm966e->common_magic = ARM966E_COMMON_MAGIC; - + /* The ARM966E-S implements the ARMv5TE architecture which * has the BKPT instruction, so we don't have to use a watchpoint comparator */ arm7_9->arm_bkpt = ARMV5_BKPT(0x0); arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff; - + return ERROR_OK; } int arm966e_target_create( struct target_s *target, Jim_Interp *interp ) { arm966e_common_t *arm966e = calloc(1,sizeof(arm966e_common_t)); - + arm966e_init_arch_info(target, arm966e, target->tap, target->variant); return ERROR_OK; @@ -136,35 +136,35 @@ int arm966e_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, ar arm7_9_common_t *arm7_9; arm9tdmi_common_t *arm9tdmi; arm966e_common_t *arm966e; - + if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { return -1; } - + arm7_9 = armv4_5->arch_info; if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC) { return -1; } - + arm9tdmi = arm7_9->arch_info; if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC) { return -1; } - + arm966e = arm9tdmi->arch_info; if (arm966e->common_magic != ARM966E_COMMON_MAGIC) { return -1; } - + *armv4_5_p = armv4_5; *arm7_9_p = arm7_9; *arm9tdmi_p = arm9tdmi; *arm966e_p = arm966e; - + return ERROR_OK; } @@ -177,8 +177,8 @@ int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value) scan_field_t fields[3]; u8 reg_addr_buf = reg_addr & 0x3f; u8 nr_w_buf = 0; - - jtag_add_end_state(TAP_RTI); + + jtag_add_end_state(TAP_IDLE); if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) { return retval; @@ -214,7 +214,7 @@ int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value) fields[2].in_check_mask = NULL; fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - + jtag_add_dr_scan(3, fields, -1); fields[0].in_handler_priv = value; @@ -243,10 +243,10 @@ int arm966e_write_cp15(target_t *target, int reg_addr, u32 value) u8 reg_addr_buf = reg_addr & 0x3f; u8 nr_w_buf = 1; u8 value_buf[4]; - + buf_set_u32(value_buf, 0, 32, value); - - jtag_add_end_state(TAP_RTI); + + jtag_add_end_state(TAP_IDLE); if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK) { return retval; @@ -282,7 +282,7 @@ int arm966e_write_cp15(target_t *target, int reg_addr, u32 value) fields[2].in_check_mask = NULL; fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - + jtag_add_dr_scan(3, fields, -1); #ifdef _DEBUG_INSTRUCTION_EXECUTION_ @@ -307,9 +307,9 @@ int arm966e_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch command_print(cmd_ctx, "current target isn't an ARM966e target"); return ERROR_OK; } - + jtag_info = &arm7_9->jtag_info; - + if (target->state != TARGET_HALTED) { command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd); @@ -333,7 +333,7 @@ int arm966e_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch { return retval; } - + command_print(cmd_ctx, "%i: %8.8x", address, value); } else if (argc == 2) @@ -355,10 +355,10 @@ int arm966e_register_commands(struct command_context_s *cmd_ctx) { int retval; command_t *arm966e_cmd; - + retval = arm9tdmi_register_commands(cmd_ctx); arm966e_cmd = register_command(cmd_ctx, NULL, "arm966e", NULL, COMMAND_ANY, "arm966e specific commands"); register_command(cmd_ctx, arm966e_cmd, "cp15", arm966e_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register [value]"); - + return retval; } diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c index 70ee6239..f717dc9d 100644 --- a/src/target/arm9tdmi.c +++ b/src/target/arm9tdmi.c @@ -56,7 +56,7 @@ int arm9tdmi_target_create( struct target_s *target, Jim_Interp *interp ); int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target); int arm9tdmi_quit(void); - + target_type_t arm9tdmi_target = { .name = "arm9tdmi", @@ -81,9 +81,9 @@ target_type_t arm9tdmi_target = .bulk_write_memory = arm7_9_bulk_write_memory, .checksum_memory = arm7_9_checksum_memory, .blank_check_memory = arm7_9_blank_check_memory, - + .run_algorithm = armv4_5_run_algorithm, - + .add_breakpoint = arm7_9_add_breakpoint, .remove_breakpoint = arm7_9_remove_breakpoint, .add_watchpoint = arm7_9_add_watchpoint, @@ -115,7 +115,7 @@ int arm9tdmi_examine_debug_reason(target_t *target) /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - + /* only check the debug reason if we don't know it already */ if ((target->debug_reason != DBG_REASON_DBGRQ) && (target->debug_reason != DBG_REASON_SINGLESTEP)) @@ -125,7 +125,7 @@ int arm9tdmi_examine_debug_reason(target_t *target) u8 instructionbus[4]; u8 debug_reason; - jtag_add_end_state(TAP_PD); + jtag_add_end_state(TAP_DRPAUSE); fields[0].tap = arm7_9->jtag_info.tap; fields[0].num_bits = 32; @@ -136,7 +136,7 @@ int arm9tdmi_examine_debug_reason(target_t *target) fields[0].in_check_mask = NULL; fields[0].in_handler = NULL; fields[0].in_handler_priv = NULL; - + fields[1].tap = arm7_9->jtag_info.tap; fields[1].num_bits = 3; fields[1].out_value = NULL; @@ -146,7 +146,7 @@ int arm9tdmi_examine_debug_reason(target_t *target) fields[1].in_check_mask = NULL; fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - + fields[2].tap = arm7_9->jtag_info.tap; fields[2].num_bits = 32; fields[2].out_value = NULL; @@ -156,27 +156,27 @@ int arm9tdmi_examine_debug_reason(target_t *target) fields[2].in_check_mask = NULL; fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - + if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK) { return retval; } arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL); - jtag_add_dr_scan(3, fields, TAP_PD); + jtag_add_dr_scan(3, fields, TAP_DRPAUSE); if((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } - + fields[0].in_value = NULL; fields[0].out_value = databus; fields[1].in_value = NULL; fields[1].out_value = &debug_reason; fields[2].in_value = NULL; fields[2].out_value = instructionbus; - - jtag_add_dr_scan(3, fields, TAP_PD); + + jtag_add_dr_scan(3, fields, TAP_DRPAUSE); if (debug_reason & 0x4) if (debug_reason & 0x2) @@ -198,23 +198,23 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s u8 out_buf[4]; u8 instr_buf[4]; u8 sysspeed_buf = 0x0; - + /* prepare buffer */ buf_set_u32(out_buf, 0, 32, out); - + buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32)); - + if (sysspeed) buf_set_u32(&sysspeed_buf, 2, 1, 1); - - jtag_add_end_state(TAP_PD); + + jtag_add_end_state(TAP_DRPAUSE); if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) { return retval; } - + arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - + fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = out_buf; @@ -232,7 +232,7 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s } fields[0].in_check_value = NULL; fields[0].in_check_mask = NULL; - + fields[1].tap = jtag_info->tap; fields[1].num_bits = 3; fields[1].out_value = &sysspeed_buf; @@ -242,7 +242,7 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s fields[1].in_check_mask = NULL; fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - + fields[2].tap = jtag_info->tap; fields[2].num_bits = 32; fields[2].out_value = instr_buf; @@ -256,14 +256,14 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s jtag_add_dr_scan(3, fields, -1); jtag_add_runtest(0, -1); - + #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { if((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } - + if (in) { LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in); @@ -282,14 +282,14 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) int retval = ERROR_OK;; scan_field_t fields[3]; - jtag_add_end_state(TAP_PD); + jtag_add_end_state(TAP_DRPAUSE); if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) { return retval; } - + arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - + fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = NULL; @@ -299,7 +299,7 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) fields[0].in_handler_priv = in; fields[0].in_check_value = NULL; fields[0].in_check_mask = NULL; - + fields[1].tap = jtag_info->tap; fields[1].num_bits = 3; fields[1].out_value = NULL; @@ -319,18 +319,18 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in) fields[2].in_check_mask = NULL; fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - + jtag_add_dr_scan(3, fields, -1); jtag_add_runtest(0, -1); - + #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { if((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } - + if (in) { LOG_DEBUG("in: 0x%8.8x", *in); @@ -353,15 +353,15 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, { int retval = ERROR_OK; scan_field_t fields[3]; - - jtag_add_end_state(TAP_PD); + + jtag_add_end_state(TAP_DRPAUSE); if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK) { return retval; } - + arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - + fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = NULL; @@ -382,7 +382,7 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, fields[0].in_handler_priv = in; fields[0].in_check_value = NULL; fields[0].in_check_mask = NULL; - + fields[1].tap = jtag_info->tap; fields[1].num_bits = 3; fields[1].out_value = NULL; @@ -402,18 +402,18 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, fields[2].in_check_mask = NULL; fields[2].in_handler = NULL; fields[2].in_handler_priv = NULL; - + jtag_add_dr_scan(3, fields, -1); jtag_add_runtest(0, -1); - + #ifdef _DEBUG_INSTRUCTION_EXECUTION_ { if((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } - + if (in) { LOG_DEBUG("in: 0x%8.8x", *(u32*)in); @@ -435,10 +435,10 @@ void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - - /* save r0 before using it and put system in ARM state + + /* save r0 before using it and put system in ARM state * to allow common handling of ARM and THUMB debugging */ - + /* fetch STR r0, [r0] */ arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); @@ -446,7 +446,7 @@ void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc) /* STR r0, [r0] in Memory */ arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0); - /* MOV r0, r15 fetched, STR in Decode */ + /* MOV r0, r15 fetched, STR in Decode */ arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0); @@ -470,12 +470,12 @@ void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc) arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); /* NOP fetched, BX in Execute (1) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); - + if((retval = jtag_execute_queue()) != ERROR_OK) { return; } - + /* fix program counter: * MOV r0, r15 was the 5th instruction (+8) * reading PC in Thumb state gives address of instruction + 4 @@ -490,7 +490,7 @@ void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16]) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + /* STMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK */ @@ -521,7 +521,7 @@ void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buf u32 *buf_u32 = buffer; u16 *buf_u16 = buffer; u8 *buf_u8 = buffer; - + /* STMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK */ @@ -558,7 +558,7 @@ void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + /* MRS r0, cpsr */ arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -583,7 +583,7 @@ void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr); /* MSR1 fetched */ @@ -619,16 +619,16 @@ void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr); - + /* MSR fetched */ arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0); /* NOP fetched, MSR in DECODE */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); /* NOP fetched, MSR in EXECUTE (1) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - + /* rot == 4 writes flags, which takes only one cycle */ if (rot != 4) { @@ -646,7 +646,7 @@ void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16]) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + /* LDMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK */ @@ -664,7 +664,7 @@ void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16]) arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0); } arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - + } void arm9tdmi_load_word_regs(target_t *target, u32 mask) @@ -686,7 +686,7 @@ void arm9tdmi_load_hword_reg(target_t *target, int num) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + /* put system-speed load half-word into the pipeline */ arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1); @@ -750,7 +750,7 @@ void arm9tdmi_write_pc(target_t *target, u32 pc) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + /* LDMIA r0-15, [r0] at debug speed * register values will start to appear on 4th DCLK */ @@ -777,7 +777,7 @@ void arm9tdmi_branch_resume(target_t *target) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1); @@ -786,7 +786,7 @@ void arm9tdmi_branch_resume(target_t *target) void arm9tdmi_branch_resume_thumb(target_t *target) { LOG_DEBUG("-"); - + /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; @@ -809,14 +809,14 @@ void arm9tdmi_branch_resume_thumb(target_t *target) /* Branch and eXchange */ arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0); - + embeddedice_read_reg(dbg_stat); - + /* fetch NOP, BX in DECODE stage */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); - + embeddedice_read_reg(dbg_stat); - + /* fetch NOP, BX in EXECUTE stage (1st cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -833,12 +833,12 @@ void arm9tdmi_branch_resume_thumb(target_t *target) arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0); /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); - + arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); embeddedice_read_reg(dbg_stat); - + arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); @@ -849,7 +849,7 @@ void arm9tdmi_enable_single_step(target_t *target, u32 next_pc) /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - + if (arm7_9->has_single_step) { buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1); @@ -866,7 +866,7 @@ void arm9tdmi_disable_single_step(target_t *target) /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; - + if (arm7_9->has_single_step) { buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0); @@ -905,7 +905,7 @@ int arm9tdmi_examine(struct target_s *target) return ERROR_FAIL; (*cache_p) = t; arm7_9->eice_cache = (*cache_p); - + if (arm7_9->etm_ctx) { arm_jtag_t *jtag_info = &arm7_9->jtag_info; @@ -928,16 +928,16 @@ int arm9tdmi_examine(struct target_s *target) int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target) { - + arm9tdmi_build_reg_cache(target); - + return ERROR_OK; - + } int arm9tdmi_quit(void) { - + return ERROR_OK; } @@ -945,53 +945,53 @@ int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_ { armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; - + arm7_9 = &arm9tdmi->arm7_9_common; armv4_5 = &arm7_9->armv4_5_common; - + /* prepare JTAG information for the new target */ arm7_9->jtag_info.tap = tap; arm7_9->jtag_info.scann_size = 5; - + /* register arch-specific functions */ arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason; arm7_9->change_to_arm = arm9tdmi_change_to_arm; arm7_9->read_core_regs = arm9tdmi_read_core_regs; arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer; arm7_9->read_xpsr = arm9tdmi_read_xpsr; - + arm7_9->write_xpsr = arm9tdmi_write_xpsr; arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8; arm7_9->write_core_regs = arm9tdmi_write_core_regs; - + arm7_9->load_word_regs = arm9tdmi_load_word_regs; arm7_9->load_hword_reg = arm9tdmi_load_hword_reg; arm7_9->load_byte_reg = arm9tdmi_load_byte_reg; - + arm7_9->store_word_regs = arm9tdmi_store_word_regs; arm7_9->store_hword_reg = arm9tdmi_store_hword_reg; arm7_9->store_byte_reg = arm9tdmi_store_byte_reg; - + arm7_9->write_pc = arm9tdmi_write_pc; arm7_9->branch_resume = arm9tdmi_branch_resume; arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb; arm7_9->enable_single_step = arm9tdmi_enable_single_step; arm7_9->disable_single_step = arm9tdmi_disable_single_step; - + arm7_9->pre_debug_entry = NULL; arm7_9->post_debug_entry = NULL; - + arm7_9->pre_restore_context = NULL; arm7_9->post_restore_context = NULL; /* initialize arch-specific breakpoint handling */ arm7_9->arm_bkpt = 0xdeeedeee; arm7_9->thumb_bkpt = 0xdeee; - + arm7_9->dbgreq_adjust_pc = 3; arm7_9->arch_info = arm9tdmi; - + arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC; arm9tdmi->arch_info = NULL; @@ -1003,7 +1003,7 @@ int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_ { arm9tdmi->variant = strdup(""); } - + arm7_9_init_arch_info(target, arm7_9); /* override use of DBGRQ, this is safe on ARM9TDMI */ @@ -1011,7 +1011,7 @@ int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_ /* all ARM9s have the vector catch register */ arm7_9->has_vector_catch = 1; - + return ERROR_OK; } @@ -1020,28 +1020,28 @@ int arm9tdmi_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, a armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9; arm9tdmi_common_t *arm9tdmi; - + if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) { return -1; } - + arm7_9 = armv4_5->arch_info; if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC) { return -1; } - + arm9tdmi = arm7_9->arch_info; if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC) { return -1; } - + *armv4_5_p = armv4_5; *arm7_9_p = arm7_9; *arm9tdmi_p = arm9tdmi; - + return ERROR_OK; } @@ -1052,24 +1052,24 @@ int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp) arm9tdmi_common_t *arm9tdmi = calloc(1,sizeof(arm9tdmi_common_t)); arm9tdmi_init_arch_info(target, arm9tdmi, target->tap, target->variant); - + return ERROR_OK; } int arm9tdmi_register_commands(struct command_context_s *cmd_ctx) { int retval; - + command_t *arm9tdmi_cmd; - - + + retval = arm7_9_register_commands(cmd_ctx); - + arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands"); register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'']"); - - + + return retval; } @@ -1083,22 +1083,22 @@ int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, cha reg_t *vector_catch; u32 vector_catch_value; int i, j; - + if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK) { command_print(cmd_ctx, "current target isn't an ARM9TDMI based target"); return ERROR_OK; } - + vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]; - + /* read the vector catch register if necessary */ if (!vector_catch->valid) embeddedice_read_reg(vector_catch); - + /* get the current setting */ vector_catch_value = buf_get_u32(vector_catch->value, 0, 32); - + if (argc > 0) { vector_catch_value = 0x0; @@ -1123,25 +1123,25 @@ int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, cha break; } } - + /* complain if vector wasn't found */ if (!arm9tdmi_vectors[j].name) { command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]); - + /* reread current setting */ vector_catch_value = buf_get_u32(vector_catch->value, 0, 32); - + break; } } } - + /* store new settings */ buf_set_u32(vector_catch->value, 0, 32, vector_catch_value); embeddedice_store_reg(vector_catch); } - + /* output current settings (skip RESERVED vector) */ for (i = 0; i < 8; i++) { @@ -1149,7 +1149,7 @@ int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, cha { command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name, (vector_catch_value & (1 << i)) ? "catch" : "don't catch"); - } + } } return ERROR_OK; diff --git a/src/target/cortex_swjdp.c b/src/target/cortex_swjdp.c index 02cbe004..974ced02 100644 --- a/src/target/cortex_swjdp.c +++ b/src/target/cortex_swjdp.c @@ -44,7 +44,7 @@ /* * Transaction Mode: * swjdp->trans_mode = TRANS_MODE_COMPOSITE; - * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction + * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction * result checking until swjdp_end_transaction() * This must be done before using or deallocating any return variables. * swjdp->trans_mode == TRANS_MODE_ATOMIC @@ -63,8 +63,8 @@ int swjdp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalu { scan_field_t fields[2]; u8 out_addr_buf; - - jtag_add_end_state(TAP_RTI); + + jtag_add_end_state(TAP_IDLE); arm_jtag_set_instr(jtag_info, instr, NULL); fields[0].tap = jtag_info->tap; @@ -99,8 +99,8 @@ int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 out scan_field_t fields[2]; u8 out_value_buf[4]; u8 out_addr_buf; - - jtag_add_end_state(TAP_RTI); + + jtag_add_end_state(TAP_IDLE); arm_jtag_set_instr(jtag_info, instr, NULL); fields[0].tap = jtag_info->tap; @@ -138,7 +138,7 @@ int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 out return ERROR_OK; } -/* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */ +/* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */ int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue) { swjdp_scan(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL); @@ -146,7 +146,7 @@ int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *o { swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); } - + /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */ if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) { @@ -163,7 +163,7 @@ int scan_inout_check_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u { swjdp_scan_u32(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack); } - + /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */ if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC)) { @@ -179,10 +179,10 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) u32 ctrlstat; keep_alive(); - + /* Danger!!!! BROKEN!!!! */ scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); - /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here???? + /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here???? R956 introduced the check on return value here and now Michael Schwingen reports that this code no longer works.... @@ -196,9 +196,9 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); if ((retval=jtag_execute_queue())!=ERROR_OK) return retval; - + swjdp->ack = swjdp->ack & 0x7; - + long long then=timeval_ms(); while (swjdp->ack != 2) { @@ -234,13 +234,13 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) else { u32 dcb_dhcsr,nvic_shcsr, nvic_bfar, nvic_cfsr; - + if (ctrlstat & SSTICKYORUN) LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed"); - + if (ctrlstat & SSTICKYERR) LOG_ERROR("SWJ-DP STICKY ERROR"); - + /* Clear Sticky Error Bits */ scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL); scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat); @@ -248,8 +248,8 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp) return retval; LOG_DEBUG("swjdp: status 0x%x", ctrlstat); - - /* Can we find out the reason for the error ?? */ + + /* Can we find out the reason for the error ?? */ ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr); ahbap_read_system_atomic_u32(swjdp, NVIC_SHCSR, &nvic_shcsr); ahbap_read_system_atomic_u32(swjdp, NVIC_CFSR, &nvic_cfsr); @@ -312,7 +312,7 @@ int ahbap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf) int ahbap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value) { u8 out_value_buf[4]; - + buf_set_u32(out_value_buf, 0, 32, value); swjdp_bankselect_apacc(swjdp, reg_addr); scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL); @@ -350,7 +350,7 @@ int ahbap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar) swjdp->ap_tar_value = tar; } if (csw & CSW_ADDRINC_MASK) - { + { /* Do not cache TAR value when autoincrementing */ swjdp->ap_tar_value = -1; } @@ -371,14 +371,14 @@ int ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value) ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0); ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (address & 0xC), value ); - + return ERROR_OK; } int ahbap_read_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value) { ahbap_read_system_u32(swjdp, address, value); - + return swjdp_transaction_endcheck(swjdp); } @@ -402,7 +402,7 @@ int ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value) int ahbap_write_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value) { ahbap_write_system_u32(swjdp, address, value); - + return swjdp_transaction_endcheck(swjdp); } @@ -419,12 +419,12 @@ int ahbap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK; u32 adr = address; u8* pBuffer = buffer; - + swjdp->trans_mode = TRANS_MODE_COMPOSITE; - + count >>= 2; wcount = count; - + /* if we have an unaligned access - reorder data */ if (adr & 0x3u) { @@ -432,7 +432,7 @@ int ahbap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres { int i; outvalue = *((u32*)pBuffer); - + for (i = 0; i < 4; i++ ) { *((u8*)pBuffer + (adr & 0x3)) = outvalue; @@ -442,25 +442,25 @@ int ahbap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres pBuffer += 4; } } - + while (wcount > 0) { /* Adjust to write blocks within 4K aligned boundaries */ blocksize = (0x1000 - (0xFFF & address)) >> 2; if (wcount < blocksize) blocksize = wcount; - + /* handle unaligned data at 4k boundary */ if (blocksize == 0) blocksize = 1; - + ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address); - + for (writecount = 0; writecount < blocksize; writecount++) { ahbap_write_reg(swjdp, AHBAP_DRW, buffer + 4 * writecount ); } - + if (swjdp_transaction_endcheck(swjdp) == ERROR_OK) { wcount = wcount - blocksize; @@ -471,14 +471,14 @@ int ahbap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres { errorcount++; } - + if (errorcount > 1) { LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount); return ERROR_JTAG_DEVICE_ERROR; } } - + return retval; } @@ -487,32 +487,32 @@ int ahbap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 u32 outvalue; int retval = ERROR_OK; int wcount, blocksize, writecount, i; - + swjdp->trans_mode = TRANS_MODE_COMPOSITE; - + wcount = count >> 1; - + while (wcount > 0) { int nbytes; - + /* Adjust to read within 4K block boundaries */ blocksize = (0x1000 - (0xFFF & address)) >> 1; - + if (wcount < blocksize) blocksize = wcount; - + /* handle unaligned data at 4k boundary */ if (blocksize == 0) blocksize = 1; - + ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address); writecount = blocksize; - + do { nbytes = MIN((writecount << 1), 4); - + if (nbytes < 4 ) { if (ahbap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK) @@ -520,20 +520,20 @@ int ahbap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } - + address += nbytes >> 1; } else { outvalue = *((u32*)buffer); - + for (i = 0; i < nbytes; i++ ) { *((u8*)buffer + (address & 0x3)) = outvalue; outvalue >>= 8; address++; } - + outvalue = *((u32*)buffer); ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue); if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) @@ -542,14 +542,14 @@ int ahbap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 return ERROR_JTAG_DEVICE_ERROR; } } - + buffer += nbytes >> 1; writecount -= nbytes >> 1; - + } while (writecount); wcount -= blocksize; } - + return retval; } @@ -557,12 +557,12 @@ int ahbap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres { u32 outvalue; int retval = ERROR_OK; - + if (count >= 4) return ahbap_write_buf_packed_u16(swjdp, buffer, count, address); - + swjdp->trans_mode = TRANS_MODE_COMPOSITE; - + while (count > 0) { ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address); @@ -582,28 +582,28 @@ int ahbap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 u32 outvalue; int retval = ERROR_OK; int wcount, blocksize, writecount, i; - + swjdp->trans_mode = TRANS_MODE_COMPOSITE; - + wcount = count; - + while (wcount > 0) { int nbytes; - + /* Adjust to read within 4K block boundaries */ blocksize = (0x1000 - (0xFFF & address)); - + if (wcount < blocksize) blocksize = wcount; - + ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address); writecount = blocksize; - + do { nbytes = MIN(writecount, 4); - + if (nbytes < 4 ) { if (ahbap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK) @@ -611,20 +611,20 @@ int ahbap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } - + address += nbytes; } else { outvalue = *((u32*)buffer); - + for (i = 0; i < nbytes; i++ ) { *((u8*)buffer + (address & 0x3)) = outvalue; outvalue >>= 8; address++; } - + outvalue = *((u32*)buffer); ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue); if (swjdp_transaction_endcheck(swjdp) != ERROR_OK) @@ -633,14 +633,14 @@ int ahbap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 return ERROR_JTAG_DEVICE_ERROR; } } - + buffer += nbytes; writecount -= nbytes; - + } while (writecount); wcount -= blocksize; } - + return retval; } @@ -648,12 +648,12 @@ int ahbap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address { u32 outvalue; int retval = ERROR_OK; - + if (count >= 4) return ahbap_write_buf_packed_u8(swjdp, buffer, count, address); - + swjdp->trans_mode = TRANS_MODE_COMPOSITE; - + while (count > 0) { ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); @@ -664,7 +664,7 @@ int ahbap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address address++; buffer++; } - + return retval; } @@ -680,25 +680,25 @@ int ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK; u32 adr = address; u8* pBuffer = buffer; - + swjdp->trans_mode = TRANS_MODE_COMPOSITE; - + count >>= 2; wcount = count; - + while (wcount > 0) { /* Adjust to read within 4K block boundaries */ blocksize = (0x1000 - (0xFFF & address)) >> 2; if (wcount < blocksize) blocksize = wcount; - + /* handle unaligned data at 4k boundary */ if (blocksize == 0) blocksize = 1; - + ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address); - + /* Scan out first read */ swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, NULL, NULL); for (readcount = 0; readcount < blocksize - 1; readcount++) @@ -706,27 +706,27 @@ int ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address /* Scan out read instruction and scan in previous value */ swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack); } - + /* Scan in last value */ swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack); if (swjdp_transaction_endcheck(swjdp) == ERROR_OK) { wcount = wcount - blocksize; address += 4 * blocksize; - buffer += 4 * blocksize; + buffer += 4 * blocksize; } else { errorcount++; } - + if (errorcount > 1) { LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } } - + /* if we have an unaligned access - reorder data */ if (adr & 0x3u) { @@ -734,7 +734,7 @@ int ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address { int i; u32 data = *((u32*)pBuffer); - + for (i = 0; i < 4; i++ ) { *((u8*)pBuffer) = (data >> 8 * (adr & 0x3)); @@ -743,7 +743,7 @@ int ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address } } } - + return retval; } @@ -752,27 +752,27 @@ int ahbap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 u32 invalue; int retval = ERROR_OK; int wcount, blocksize, readcount, i; - + swjdp->trans_mode = TRANS_MODE_COMPOSITE; - + wcount = count >> 1; - + while (wcount > 0) { int nbytes; - + /* Adjust to read within 4K block boundaries */ blocksize = (0x1000 - (0xFFF & address)) >> 1; if (wcount < blocksize) blocksize = wcount; - + ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address); - + /* handle unaligned data at 4k boundary */ if (blocksize == 0) blocksize = 1; readcount = blocksize; - + do { ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue ); @@ -781,21 +781,21 @@ int ahbap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } - + nbytes = MIN((readcount << 1), 4); - + for (i = 0; i < nbytes; i++ ) { *((u8*)buffer) = (invalue >> 8 * (address & 0x3)); buffer++; address++; } - + readcount -= (nbytes >> 1); } while (readcount); wcount -= blocksize; } - + return retval; } @@ -803,12 +803,12 @@ int ahbap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address { u32 invalue, i; int retval = ERROR_OK; - + if (count >= 4) return ahbap_read_buf_packed_u16(swjdp, buffer, count, address); - + swjdp->trans_mode = TRANS_MODE_COMPOSITE; - + while (count > 0) { ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address); @@ -840,24 +840,24 @@ int ahbap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 a u32 invalue; int retval = ERROR_OK; int wcount, blocksize, readcount, i; - + swjdp->trans_mode = TRANS_MODE_COMPOSITE; - + wcount = count; - + while (wcount > 0) { int nbytes; - + /* Adjust to read within 4K block boundaries */ blocksize = (0x1000 - (0xFFF & address)); - + if (wcount < blocksize) blocksize = wcount; - + ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address); readcount = blocksize; - + do { ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue ); @@ -866,21 +866,21 @@ int ahbap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 a LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count); return ERROR_JTAG_DEVICE_ERROR; } - + nbytes = MIN(readcount, 4); - + for (i = 0; i < nbytes; i++ ) { *((u8*)buffer) = (invalue >> 8 * (address & 0x3)); buffer++; address++; } - + readcount -= nbytes; } while (readcount); wcount -= blocksize; } - + return retval; } @@ -888,12 +888,12 @@ int ahbap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) { u32 invalue; int retval = ERROR_OK; - + if (count >= 4) return ahbap_read_buf_packed_u8(swjdp, buffer, count, address); - + swjdp->trans_mode = TRANS_MODE_COMPOSITE; - + while (count > 0) { ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address); @@ -912,12 +912,12 @@ int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum) { int retval; u32 dcrdr; - + /* because the DCB_DCRDR is used for the emulated dcc channel * we gave to save/restore the DCB_DCRDR when used */ - + ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr); - + swjdp->trans_mode = TRANS_MODE_COMPOSITE; /* ahbap_write_system_u32(swjdp, DCB_DCRSR, regnum); */ @@ -927,7 +927,7 @@ int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum) /* ahbap_read_system_u32(swjdp, DCB_DCRDR, value); */ ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value ); - + retval = swjdp_transaction_endcheck(swjdp); ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr); return retval; @@ -937,14 +937,14 @@ int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum) { int retval; u32 dcrdr; - + /* because the DCB_DCRDR is used for the emulated dcc channel * we gave to save/restore the DCB_DCRDR when used */ - + ahbap_read_system_atomic_u32(swjdp, DCB_DCRDR, &dcrdr); - + swjdp->trans_mode = TRANS_MODE_COMPOSITE; - + /* ahbap_write_system_u32(swjdp, DCB_DCRDR, core_regs[i]); */ ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0); ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value ); @@ -952,7 +952,7 @@ int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum) /* ahbap_write_system_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR ); */ ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0); ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR ); - + retval = swjdp_transaction_endcheck(swjdp); ahbap_write_system_atomic_u32(swjdp, DCB_DCRDR, dcrdr); return retval; @@ -964,16 +964,16 @@ int ahbap_debugport_init(swjdp_common_t *swjdp) u32 ctrlstat; int cnt = 0; int retval; - + LOG_DEBUG(" "); - + swjdp->ap_csw_value = -1; swjdp->ap_tar_value = -1; swjdp->trans_mode = TRANS_MODE_ATOMIC; swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT); swjdp_write_dpacc(swjdp, SSTICKYERR, DP_CTRL_STAT); swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT); - + swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ; swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT); @@ -1005,11 +1005,11 @@ int ahbap_debugport_init(swjdp_common_t *swjdp) swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT; swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT); swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT); - + ahbap_read_reg_u32(swjdp, 0xFC, &idreg); ahbap_read_reg_u32(swjdp, 0xF8, &romaddr); - + LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr); - + return ERROR_OK; } diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index 8a1b3987..05c80f8b 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -246,7 +246,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) u8 field1_out[1]; u8 field2_out[1]; - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); arm_jtag_scann(ice_reg->jtag_info, 0x2); arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL); @@ -309,7 +309,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size) u8 field1_out[1]; u8 field2_out[1]; - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0x2); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); @@ -400,7 +400,7 @@ void embeddedice_write_reg(reg_t *reg, u32 value) LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value); - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); arm_jtag_scann(ice_reg->jtag_info, 0x2); arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL); @@ -426,7 +426,7 @@ int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size) u8 field1_out[1]; u8 field2_out[1]; - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0x2); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); @@ -495,7 +495,7 @@ int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout) else return ERROR_INVALID_ARGUMENTS; - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); arm_jtag_scann(jtag_info, 0x2); arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); diff --git a/src/target/etb.c b/src/target/etb.c index c536773d..cfaf1cdc 100644 --- a/src/target/etb.c +++ b/src/target/etb.c @@ -184,7 +184,7 @@ int etb_read_ram(etb_t *etb, u32 *data, int num_frames) scan_field_t fields[3]; int i; - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); etb_scann(etb, 0x0); etb_set_instr(etb, 0xc); @@ -255,7 +255,7 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) LOG_DEBUG("%i", etb_reg->addr); - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); etb_scann(etb_reg->etb, 0x0); etb_set_instr(etb_reg->etb, 0xc); @@ -351,7 +351,7 @@ int etb_write_reg(reg_t *reg, u32 value) LOG_DEBUG("%i: 0x%8.8x", etb_reg->addr, value); - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); etb_scann(etb_reg->etb, 0x0); etb_set_instr(etb_reg->etb, 0xc); diff --git a/src/target/etm.c b/src/target/etm.c index e2846ad0..e0aac07f 100644 --- a/src/target/etm.c +++ b/src/target/etm.c @@ -335,7 +335,7 @@ int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask) LOG_DEBUG("%i", etm_reg->addr); - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); arm_jtag_scann(etm_reg->jtag_info, 0x6); arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL); @@ -426,7 +426,7 @@ int etm_write_reg(reg_t *reg, u32 value) LOG_DEBUG("%i: 0x%8.8x", etm_reg->addr, value); - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); arm_jtag_scann(etm_reg->jtag_info, 0x6); arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL); diff --git a/src/target/feroceon.c b/src/target/feroceon.c index 407ac52b..92d2aa00 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -91,7 +91,7 @@ target_type_t feroceon_target = .assert_reset = feroceon_assert_reset, .deassert_reset = arm7_9_deassert_reset, .soft_reset_halt = arm926ejs_soft_reset_halt, - + .get_gdb_reg_list = armv4_5_get_gdb_reg_list, .read_memory = arm7_9_read_memory, @@ -99,7 +99,7 @@ target_type_t feroceon_target = .bulk_write_memory = feroceon_bulk_write_memory, .checksum_memory = arm7_9_checksum_memory, .blank_check_memory = arm7_9_blank_check_memory, - + .run_algorithm = armv4_5_run_algorithm, .add_breakpoint = arm7_9_add_breakpoint, @@ -121,17 +121,17 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr) u8 out_buf[4]; u8 instr_buf[4]; u8 sysspeed_buf = 0x0; - + /* prepare buffer */ buf_set_u32(out_buf, 0, 32, 0); - + buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32)); - - jtag_add_end_state(TAP_PD); + + jtag_add_end_state(TAP_DRPAUSE); arm_jtag_scann(jtag_info, 0x1); - + arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL); - + fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = out_buf; @@ -141,7 +141,7 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr) fields[0].in_handler_priv = NULL; fields[0].in_check_value = NULL; fields[0].in_check_mask = NULL; - + fields[1].tap = jtag_info->tap; fields[1].num_bits = 3; fields[1].out_value = &sysspeed_buf; @@ -151,7 +151,7 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr) fields[1].in_check_mask = NULL; fields[1].in_handler = NULL; fields[1].in_handler_priv = NULL; - + fields[2].tap = jtag_info->tap; fields[2].num_bits = 32; fields[2].out_value = instr_buf; @@ -165,7 +165,7 @@ int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, u32 instr) jtag_add_dr_scan(3, fields, -1); /* no jtag_add_runtest(0, -1) here */ - + return ERROR_OK; } @@ -174,9 +174,9 @@ void feroceon_change_to_arm(target_t *target, u32 *r0, u32 *pc) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + /* - * save r0 before using it and put system in ARM state + * save r0 before using it and put system in ARM state * to allow common handling of ARM and THUMB debugging */ @@ -221,7 +221,7 @@ void feroceon_read_core_regs(target_t *target, u32 mask, u32* core_regs[16]) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -276,7 +276,7 @@ void feroceon_read_xpsr(target_t *target, u32 *xpsr, int spsr) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -299,7 +299,7 @@ void feroceon_write_xpsr(target_t *target, u32 xpsr, int spsr) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr); arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0); @@ -358,7 +358,7 @@ void feroceon_write_core_regs(target_t *target, u32 mask, u32 core_regs[16]) armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; - + arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -390,13 +390,13 @@ void feroceon_branch_resume(target_t *target) void feroceon_branch_resume_thumb(target_t *target) { LOG_DEBUG("-"); - + armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; arm_jtag_t *jtag_info = &arm7_9->jtag_info; u32 r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); u32 pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32); - (void)(r0); // use R0... + (void)(r0); // use R0... arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -411,7 +411,7 @@ void feroceon_branch_resume_thumb(target_t *target) arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDMIA(0, 0x1), 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); - + arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, pc, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); @@ -523,7 +523,7 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf * We can't use the dcc flow control bits, so let's transfer data * with 31 bits and flip the MSB each time a new data word is sent. */ - static u32 dcc_code[] = + static u32 dcc_code[] = { 0xee115e10, /* 3: mrc p14, 0, r5, c1, c0, 0 */ 0xe3a0301e, /* 1: mov r3, #30 */ @@ -586,7 +586,7 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf armv4_5->core_cache->reg_list[0].dirty = 1; armv4_5->core_state = ARMV4_5_STATE_ARM; - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0); arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1); /* send data over */ @@ -597,12 +597,12 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf { u32 y = target_buffer_get_u32(target, buffer); u32 z = (x >> 1) | (y >> shift) | (flip ^= 0x80000000); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z); x = y << (32 - shift); if (++shift >= 32 || i + 1 >= count) { z = (x >> 1) | (flip ^= 0x80000000); - embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z); + embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], z); x = 0; shift = 1; } @@ -644,7 +644,7 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp) armv4_5_common_t *armv4_5; arm7_9_common_t *arm7_9; arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t)); - + arm926ejs_init_arch_info(target, arm926ejs, target->tap, target->variant); armv4_5 = target->arch_info; @@ -678,8 +678,8 @@ int feroceon_target_create(struct target_s *target, Jim_Interp *interp) arm7_9->set_special_dbgrq = feroceon_set_dbgrq; /* only one working comparator */ - arm7_9->wp_available_max = 1; - arm7_9->wp1_used_default = -1; + arm7_9->wp_available_max = 1; + arm7_9->wp1_used_default = -1; return ERROR_OK; } @@ -694,27 +694,27 @@ int feroceon_examine(struct target_s *target) retval = arm9tdmi_examine(target); if (retval!=ERROR_OK) return retval; - + armv4_5 = target->arch_info; arm7_9 = armv4_5->arch_info; - + /* the COMMS_CTRL bits are all contiguous */ if (buf_get_u32(arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL].value, 2, 4) != 6) LOG_ERROR("unexpected Feroceon EICE version signature"); - - arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].size = 6; - arm7_9->eice_cache->reg_list[EICE_DBG_STAT].size = 5; + + arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].size = 6; + arm7_9->eice_cache->reg_list[EICE_DBG_STAT].size = 5; arm7_9->has_monitor_mode = 1; - + /* vector catch reg is not initialized on reset */ embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0); - + /* clear monitor mode, enable comparators */ embeddedice_read_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]); - jtag_execute_queue(); + jtag_execute_queue(); buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 4, 1, 0); - buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 5, 1, 0); + buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 5, 1, 0); embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]); - + return ERROR_OK; } diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c index 729b1a23..698e0b83 100644 --- a/src/target/mips_ejtag.c +++ b/src/target/mips_ejtag.c @@ -65,7 +65,7 @@ int mips_ejtag_get_idcode(mips_ejtag_t *ejtag_info, u32 *idcode, in_handler_t ha { scan_field_t field; - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE, NULL); @@ -92,7 +92,7 @@ int mips_ejtag_get_impcode(mips_ejtag_t *ejtag_info, u32 *impcode, in_handler_t { scan_field_t field; - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE, NULL); @@ -202,7 +202,7 @@ int mips_ejtag_config_step(mips_ejtag_t *ejtag_info, int enable_step) int mips_ejtag_enter_debug(mips_ejtag_t *ejtag_info) { u32 ejtag_ctrl; - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); /* set debug break bit */ diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index e1fd8dc8..353126d9 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -67,7 +67,7 @@ target_type_t mips_m4k_target = .assert_reset = mips_m4k_assert_reset, .deassert_reset = mips_m4k_deassert_reset, .soft_reset_halt = mips_m4k_soft_reset_halt, - + .get_gdb_reg_list = mips32_get_gdb_reg_list, .read_memory = mips_m4k_read_memory, @@ -75,7 +75,7 @@ target_type_t mips_m4k_target = .bulk_write_memory = mips_m4k_bulk_write_memory, .checksum_memory = NULL, .blank_check_memory = NULL, - + .run_algorithm = mips32_run_algorithm, .add_breakpoint = mips_m4k_add_breakpoint, @@ -91,10 +91,10 @@ target_type_t mips_m4k_target = }; int mips_m4k_examine_debug_reason(target_t *target) -{ +{ int break_status; int retval; - + if ((target->debug_reason != DBG_REASON_DBGRQ) && (target->debug_reason != DBG_REASON_SINGLESTEP)) { @@ -108,7 +108,7 @@ int mips_m4k_examine_debug_reason(target_t *target) return retval; target->debug_reason = DBG_REASON_BREAKPOINT; } - + /* get info about data breakpoint support */ if ((retval = target_read_u32(target, 0xFF302000, &break_status)) != ERROR_OK) return retval; @@ -120,7 +120,7 @@ int mips_m4k_examine_debug_reason(target_t *target) target->debug_reason = DBG_REASON_WATCHPOINT; } } - + return ERROR_OK; } @@ -129,29 +129,29 @@ int mips_m4k_debug_entry(target_t *target) mips32_common_t *mips32 = target->arch_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info; u32 debug_reg; - + /* read debug register */ mips_ejtag_read_debug(ejtag_info, &debug_reg); - + /* make sure break uit configured */ mips32_configure_break_unit(target); - + /* attempt to find halt reason */ mips_m4k_examine_debug_reason(target); - + /* clear single step if active */ if (debug_reg & EJTAG_DEBUG_DSS) { /* stopped due to single step - clear step bit */ mips_ejtag_config_step(ejtag_info, 0); } - + mips32_save_context(target); - - LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s", - *(u32*)(mips32->core_cache->reg_list[MIPS32_PC].value), + + LOG_DEBUG("entered debug state at PC 0x%x, target->state: %s", + *(u32*)(mips32->core_cache->reg_list[MIPS32_PC].value), Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); - + return ERROR_OK; } @@ -161,48 +161,48 @@ int mips_m4k_poll(target_t *target) mips32_common_t *mips32 = target->arch_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info; u32 ejtag_ctrl = ejtag_info->ejtag_ctrl; - + /* read ejtag control reg */ - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); - + /* clear this bit before handling polling * as after reset registers will read zero */ if (ejtag_ctrl & EJTAG_CTRL_ROCC) { /* we have detected a reset, clear flag * otherwise ejtag will not work */ - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC; - + mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL); mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl); LOG_DEBUG("Reset Detected"); } - + /* check for processor halted */ if (ejtag_ctrl & EJTAG_CTRL_BRKST) { if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) { - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL); - + target->state = TARGET_HALTED; - + if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK) return retval; - + target_call_event_callbacks(target, TARGET_EVENT_HALTED); } else if (target->state == TARGET_DEBUG_RUNNING) { target->state = TARGET_HALTED; - + if ((retval = mips_m4k_debug_entry(target)) != ERROR_OK) return retval; - + target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED); } } @@ -210,9 +210,9 @@ int mips_m4k_poll(target_t *target) { target->state = TARGET_RUNNING; } - + // LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl); - + return ERROR_OK; } @@ -220,22 +220,22 @@ int mips_m4k_halt(struct target_s *target) { mips32_common_t *mips32 = target->arch_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info; - - LOG_DEBUG("target->state: %s", + + LOG_DEBUG("target->state: %s", Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); - + if (target->state == TARGET_HALTED) { LOG_DEBUG("target was already halted"); return ERROR_OK; } - + if (target->state == TARGET_UNKNOWN) { LOG_WARNING("target was in unknown state when halt was requested"); } - - if (target->state == TARGET_RESET) + + if (target->state == TARGET_RESET) { if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst) { @@ -248,16 +248,16 @@ int mips_m4k_halt(struct target_s *target) * debug entry was already prepared in mips32_prepare_reset_halt() */ target->debug_reason = DBG_REASON_DBGRQ; - + return ERROR_OK; } } - + /* break processor */ mips_ejtag_enter_debug(ejtag_info); - + target->debug_reason = DBG_REASON_DBGRQ; - + return ERROR_OK; } @@ -266,28 +266,28 @@ int mips_m4k_assert_reset(target_t *target) mips32_common_t *mips32 = target->arch_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info; mips_m4k_common_t *mips_m4k = mips32->arch_info; - - LOG_DEBUG("target->state: %s", + + LOG_DEBUG("target->state: %s", Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); - + if (!(jtag_reset_config & RESET_HAS_SRST)) { LOG_ERROR("Can't assert SRST"); return ERROR_FAIL; } - + if (target->reset_halt) { /* use hardware to catch reset */ - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL); } else { - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL); } - + if (strcmp(mips_m4k->variant, "ejtag_srst") == 0) { u32 ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST; @@ -307,7 +307,7 @@ int mips_m4k_assert_reset(target_t *target) jtag_add_reset(0, 1); } } - + target->state = TARGET_RESET; jtag_add_sleep(50000); @@ -319,18 +319,18 @@ int mips_m4k_assert_reset(target_t *target) if ((retval = target_halt(target))!=ERROR_OK) return retval; } - + return ERROR_OK; } int mips_m4k_deassert_reset(target_t *target) { - LOG_DEBUG("target->state: %s", + LOG_DEBUG("target->state: %s", Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name); - + /* deassert reset lines */ jtag_add_reset(0, 0); - + return ERROR_OK; } @@ -344,15 +344,15 @@ int mips_m4k_single_step_core(target_t *target) { mips32_common_t *mips32 = target->arch_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info; - + /* configure single step mode */ mips_ejtag_config_step(ejtag_info, 1); - + /* exit debug mode */ mips_ejtag_exit_debug(ejtag_info, 1); - + mips_m4k_debug_entry(target); - + return ERROR_OK; } @@ -362,20 +362,20 @@ int mips_m4k_resume(struct target_s *target, int current, u32 address, int handl mips_ejtag_t *ejtag_info = &mips32->ejtag_info; breakpoint_t *breakpoint = NULL; u32 resume_pc; - + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - + if (!debug_execution) { target_free_all_working_areas(target); mips_m4k_enable_breakpoints(target); mips_m4k_enable_watchpoints(target); } - + /* current = 1: continue on current pc, otherwise continue at
*/ if (!current) { @@ -383,11 +383,11 @@ int mips_m4k_resume(struct target_s *target, int current, u32 address, int handl mips32->core_cache->reg_list[MIPS32_PC].dirty = 1; mips32->core_cache->reg_list[MIPS32_PC].valid = 1; } - + resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32); - + mips32_restore_context(target); - + /* the front-end may request us not to handle breakpoints */ if (handle_breakpoints) { @@ -400,14 +400,14 @@ int mips_m4k_resume(struct target_s *target, int current, u32 address, int handl mips_m4k_set_breakpoint(target, breakpoint); } } - + /* exit debug mode - enable interrupts if required */ mips_ejtag_exit_debug(ejtag_info, !debug_execution); target->debug_reason = DBG_REASON_NOTHALTED; - + /* registers are now invalid */ mips32_invalidate_core_regs(target); - + if (!debug_execution) { target->state = TARGET_RUNNING; @@ -420,7 +420,7 @@ int mips_m4k_resume(struct target_s *target, int current, u32 address, int handl target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED); LOG_DEBUG("target debug resumed at 0x%x", resume_pc); } - + return ERROR_OK; } @@ -440,43 +440,43 @@ int mips_m4k_step(struct target_s *target, int current, u32 address, int handle_ /* current = 1: continue on current pc, otherwise continue at
*/ if (!current) buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address); - + /* the front-end may request us not to handle breakpoints */ if (handle_breakpoints) if ((breakpoint = breakpoint_find(target, buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32)))) mips_m4k_unset_breakpoint(target, breakpoint); - + /* restore context */ mips32_restore_context(target); - + /* configure single step mode */ mips_ejtag_config_step(ejtag_info, 1); - + target->debug_reason = DBG_REASON_SINGLESTEP; - + target_call_event_callbacks(target, TARGET_EVENT_RESUMED); - + /* exit debug mode */ mips_ejtag_exit_debug(ejtag_info, 1); - + /* registers are now invalid */ mips32_invalidate_core_regs(target); - + if (breakpoint) mips_m4k_set_breakpoint(target, breakpoint); LOG_DEBUG("target stepped "); - + mips_m4k_debug_entry(target); target_call_event_callbacks(target, TARGET_EVENT_HALTED); - + return ERROR_OK; } void mips_m4k_enable_breakpoints(struct target_s *target) { breakpoint_t *breakpoint = target->breakpoints; - + /* set any pending breakpoints */ while (breakpoint) { @@ -490,17 +490,17 @@ int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { mips32_common_t *mips32 = target->arch_info; mips32_comparator_t * comparator_list = mips32->inst_break_list; - + if (breakpoint->set) { LOG_WARNING("breakpoint already set"); return ERROR_OK; } - + if (breakpoint->type == BKPT_HARD) { int bp_num = 0; - + while(comparator_list[bp_num].used && (bp_num < mips32->num_inst_bpoints)) bp_num++; if (bp_num >= mips32->num_inst_bpoints) @@ -521,7 +521,7 @@ int mips_m4k_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { } - + return ERROR_OK; } @@ -536,7 +536,7 @@ int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) LOG_WARNING("breakpoint not set"); return ERROR_OK; } - + if (breakpoint->type == BKPT_HARD) { int bp_num = breakpoint->set - 1; @@ -554,26 +554,26 @@ int mips_m4k_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint) } breakpoint->set = 0; - + return ERROR_OK; } int mips_m4k_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint) { mips32_common_t *mips32 = target->arch_info; - + if (mips32->num_inst_bpoints_avail < 1) { LOG_INFO("no hardware breakpoint available"); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - + /* default to hardware for now */ breakpoint->type = BKPT_HARD; - + mips32->num_inst_bpoints_avail--; mips_m4k_set_breakpoint(target, breakpoint); - + return ERROR_OK; } @@ -581,21 +581,21 @@ int mips_m4k_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint { /* get pointers to arch-specific information */ mips32_common_t *mips32 = target->arch_info; - + if (target->state != TARGET_HALTED) { LOG_WARNING("target not halted"); return ERROR_TARGET_NOT_HALTED; } - + if (breakpoint->set) { mips_m4k_unset_breakpoint(target, breakpoint); } - + if (breakpoint->type == BKPT_HARD) mips32->num_inst_bpoints_avail++; - + return ERROR_OK; } @@ -626,7 +626,7 @@ int mips_m4k_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint void mips_m4k_enable_watchpoints(struct target_s *target) { watchpoint_t *watchpoint = target->watchpoints; - + /* set any pending watchpoints */ while (watchpoint) { @@ -640,7 +640,7 @@ int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 cou { mips32_common_t *mips32 = target->arch_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info; - + LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); if (target->state != TARGET_HALTED) @@ -655,7 +655,7 @@ int mips_m4k_read_memory(struct target_s *target, u32 address, u32 size, u32 cou if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) return ERROR_TARGET_UNALIGNED_ACCESS; - + switch (size) { case 4: @@ -679,7 +679,7 @@ int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 co { mips32_common_t *mips32 = target->arch_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info; - + LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count); if (target->state != TARGET_HALTED) @@ -694,7 +694,7 @@ int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 co if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u))) return ERROR_TARGET_UNALIGNED_ACCESS; - + switch (size) { case 4: @@ -711,14 +711,14 @@ int mips_m4k_write_memory(struct target_s *target, u32 address, u32 size, u32 co exit(-1); break; } - + return ERROR_OK; } int mips_m4k_register_commands(struct command_context_s *cmd_ctx) { int retval; - + retval = mips32_register_commands(cmd_ctx); return retval; } @@ -726,7 +726,7 @@ int mips_m4k_register_commands(struct command_context_s *cmd_ctx) int mips_m4k_init_target(struct command_context_s *cmd_ctx, struct target_s *target) { mips32_build_reg_cache(target); - + return ERROR_OK; } @@ -738,7 +738,7 @@ int mips_m4k_quit(void) int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_tap_t *tap, const char *variant) { mips32_common_t *mips32 = &mips_m4k->mips32_common; - + if (variant) { mips_m4k->variant = strdup(variant); @@ -747,22 +747,22 @@ int mips_m4k_init_arch_info(target_t *target, mips_m4k_common_t *mips_m4k, jtag_ { mips_m4k->variant = strdup(""); } - + mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC; - + /* initialize mips4k specific info */ mips32_init_arch_info(target, mips32, tap, variant); mips32->arch_info = mips_m4k; - + return ERROR_OK; } int mips_m4k_target_create(struct target_s *target, Jim_Interp *interp) { mips_m4k_common_t *mips_m4k = calloc(1,sizeof(mips_m4k_common_t)); - + mips_m4k_init_arch_info(target, mips_m4k, target->tap, target->variant); - + return ERROR_OK; } @@ -772,11 +772,11 @@ int mips_m4k_examine(struct target_s *target) mips32_common_t *mips32 = target->arch_info; mips_ejtag_t *ejtag_info = &mips32->ejtag_info; u32 idcode = 0; - + if (!target->type->examined) { mips_ejtag_get_idcode(ejtag_info, &idcode, NULL); - + if (((idcode >> 1) & 0x7FF) == 0x29) { /* we are using a pic32mx so select ejtag port @@ -785,14 +785,14 @@ int mips_m4k_examine(struct target_s *target) LOG_DEBUG("PIC32MX Detected - using EJTAG Interface"); } } - + /* init rest of ejtag interface */ if ((retval = mips_ejtag_init(ejtag_info)) != ERROR_OK) return retval; - + if ((retval = mips32_examine(target)) != ERROR_OK) return retval; - + return ERROR_OK; } diff --git a/src/target/xscale.c b/src/target/xscale.c index ef476027..30447765 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -252,7 +252,7 @@ int xscale_read_dcsr(target_t *target) u8 field2_check_value = 0x0; u8 field2_check_mask = 0x1; - jtag_add_end_state(TAP_PD); + jtag_add_end_state(TAP_DRPAUSE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); buf_set_u32(&field0, 1, 1, xscale->hold_rst); @@ -300,7 +300,7 @@ int xscale_read_dcsr(target_t *target) fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value; fields[1].in_value = NULL; - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); jtag_add_dr_scan(3, fields, -1); @@ -332,9 +332,9 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) int i; - path[0] = TAP_SDS; - path[1] = TAP_CD; - path[2] = TAP_SD; + path[0] = TAP_DRSELECT; + path[1] = TAP_DRCAPTURE; + path[2] = TAP_DRSHIFT; fields[0].tap = xscale->jtag_info.tap; fields[0].num_bits = 3; @@ -362,9 +362,9 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) fields[2].in_value = NULL; jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL); - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx); - jtag_add_runtest(1, -1); /* ensures that we're in the TAP_RTI state as the above could be a no-op */ + jtag_add_runtest(1, -1); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */ /* repeat until all words have been collected */ int attempts=0; @@ -379,7 +379,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words) fields[1].in_handler_priv = (u8*)&field1[i]; jtag_add_pathmove(3, path); - jtag_add_dr_scan(3, fields, TAP_RTI); + jtag_add_dr_scan(3, fields, TAP_IDLE); words_scheduled++; } @@ -442,20 +442,20 @@ int xscale_read_tx(target_t *target, int consume) u8 field2_check_value = 0x0; u8 field2_check_mask = 0x1; - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx); - path[0] = TAP_SDS; - path[1] = TAP_CD; - path[2] = TAP_SD; + path[0] = TAP_DRSELECT; + path[1] = TAP_DRCAPTURE; + path[2] = TAP_DRSHIFT; - noconsume_path[0] = TAP_SDS; - noconsume_path[1] = TAP_CD; - noconsume_path[2] = TAP_E1D; - noconsume_path[3] = TAP_PD; - noconsume_path[4] = TAP_E2D; - noconsume_path[5] = TAP_SD; + noconsume_path[0] = TAP_DRSELECT; + noconsume_path[1] = TAP_DRCAPTURE; + noconsume_path[2] = TAP_DREXIT1; + noconsume_path[3] = TAP_DRPAUSE; + noconsume_path[4] = TAP_DREXIT2; + noconsume_path[5] = TAP_DRSHIFT; fields[0].tap = xscale->jtag_info.tap; fields[0].num_bits = 3; @@ -499,7 +499,7 @@ int xscale_read_tx(target_t *target, int consume) jtag_add_pathmove(sizeof(noconsume_path)/sizeof(*noconsume_path), noconsume_path); } - jtag_add_dr_scan(3, fields, TAP_RTI); + jtag_add_dr_scan(3, fields, TAP_IDLE); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -551,7 +551,7 @@ int xscale_write_rx(target_t *target) u8 field2_check_value = 0x0; u8 field2_check_mask = 0x1; - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx); @@ -588,7 +588,7 @@ int xscale_write_rx(target_t *target) LOG_DEBUG("polling RX"); for (;;) { - jtag_add_dr_scan(3, fields, TAP_RTI); + jtag_add_dr_scan(3, fields, TAP_IDLE); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -617,7 +617,7 @@ int xscale_write_rx(target_t *target) /* set rx_valid */ field2 = 0x1; - jtag_add_dr_scan(3, fields, TAP_RTI); + jtag_add_dr_scan(3, fields, TAP_IDLE); if ((retval = jtag_execute_queue()) != ERROR_OK) { @@ -640,7 +640,7 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size) int done_count = 0; - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx); @@ -683,7 +683,7 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size) 3, bits, t, - TAP_RTI); + TAP_IDLE); buffer += size; } @@ -726,7 +726,7 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk) if (ext_dbg_brk != -1) xscale->external_debug_break = ext_dbg_brk; - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); buf_set_u32(&field0, 1, 1, xscale->hold_rst); @@ -796,7 +796,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8]) LOG_DEBUG("loading miniIC at 0x%8.8x", va); - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */ /* CMD is b010 for Main IC and b011 for Mini IC */ @@ -859,7 +859,7 @@ int xscale_invalidate_ic_line(target_t *target, u32 va) scan_field_t fields[2]; - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */ /* CMD for invalidate IC line b000, bits [6:4] b000 */ @@ -1597,7 +1597,7 @@ int xscale_assert_reset(target_t *target) /* select DCSR instruction (set endstate to R-T-I to ensure we don't * end up in T-L-R, which would reset JTAG */ - jtag_add_end_state(TAP_RTI); + jtag_add_end_state(TAP_IDLE); xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr); /* set Hold reset, Halt mode and Trap Reset */ @@ -1620,7 +1620,7 @@ int xscale_assert_reset(target_t *target) if (target->reset_halt) { - int retval; + int retval; if ((retval = target_halt(target))!=ERROR_OK) return retval; } @@ -1671,7 +1671,7 @@ int xscale_deassert_reset(target_t *target) /* wait 300ms; 150 and 100ms were not enough */ jtag_add_sleep(300*1000); - jtag_add_runtest(2030, TAP_RTI); + jtag_add_runtest(2030, TAP_IDLE); jtag_execute_queue(); /* set Hold reset, Halt mode and Trap Reset */ @@ -1734,7 +1734,7 @@ int xscale_deassert_reset(target_t *target) xscale_load_ic(target, 1, 0x0, xscale->low_vectors); xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors); - jtag_add_runtest(30, TAP_RTI); + jtag_add_runtest(30, TAP_IDLE); jtag_add_sleep(100000); @@ -3381,7 +3381,7 @@ int xscale_handle_idcache_command(command_context_t *cmd_ctx, char *cmd, char ** command_print(cmd_ctx, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled"); if (dcache) - command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled"); + command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled"); return ERROR_OK; } -- cgit v1.2.3-18-g5258