From ada631cc5ff09e20a245fdca1afd4064be5eaa3d Mon Sep 17 00:00:00 2001 From: Bas Vermeulen Date: Sun, 26 Nov 2017 22:31:55 +0100 Subject: target aarch64: rework memory read/write to use 8/16/32 bit operations The existing code only used Memory Access mode to read memory, which uses 32 bit operations only. Rework the code to check the alignment/size of the read/write operation, and use the Memory Access mode to read aligned 32 bit memory. When using unaligned access, or 8 or 16 bit reads, use LDR{BHW} and STR{BHW} instead. The exception handling is still the same as it was before (meaning it breaks when things go wrong), but I can now read an 8 bit register correctly. Change-Id: I739a5ee825c0226ed4a89c32895cc2a047b8dc15 Signed-off-by: Bas Vermeulen Reviewed-on: http://openocd.zylin.com/4301 Tested-by: jenkins Reviewed-by: Matthias Welwarsky Reviewed-by: Paul Fertser --- src/target/armv8_opcodes.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/target/armv8_opcodes.h') diff --git a/src/target/armv8_opcodes.h b/src/target/armv8_opcodes.h index 2d8ddd82..987198a8 100644 --- a/src/target/armv8_opcodes.h +++ b/src/target/armv8_opcodes.h @@ -159,6 +159,14 @@ #define ARMV8_MOVFSP_32(Rt) (0x11000000 | (0x1f << 5) | (Rt)) #define ARMV8_MOVTSP_32(Rt) (0x11000000 | (Rt << 5) | (0x1F)) +#define ARMV8_LDRB_IP(Rd, Rn) (0x38401400 | (Rn << 5) | Rd) +#define ARMV8_LDRH_IP(Rd, Rn) (0x78402400 | (Rn << 5) | Rd) +#define ARMV8_LDRW_IP(Rd, Rn) (0xb8404400 | (Rn << 5) | Rd) + +#define ARMV8_STRB_IP(Rd, Rn) (0x38001400 | (Rn << 5) | Rd) +#define ARMV8_STRH_IP(Rd, Rn) (0x78002400 | (Rn << 5) | Rd) +#define ARMV8_STRW_IP(Rd, Rn) (0xb8004400 | (Rn << 5) | Rd) + #define ARMV8_SYS(System, Rt) (0xD5080000 | ((System) << 5) | Rt) enum armv8_opcode { @@ -180,6 +188,12 @@ enum armv8_opcode { ARMV8_OPC_DCCIVAC, ARMV8_OPC_ICIVAU, ARMV8_OPC_HLT, + ARMV8_OPC_STRB_IP, + ARMV8_OPC_STRH_IP, + ARMV8_OPC_STRW_IP, + ARMV8_OPC_LDRB_IP, + ARMV8_OPC_LDRH_IP, + ARMV8_OPC_LDRW_IP, ARMV8_OPC_NUM, }; -- cgit v1.2.3-18-g5258