From db429c34d047ac40dadf0087f3b3434551c855d4 Mon Sep 17 00:00:00 2001 From: Matthias Welwarsky Date: Thu, 5 Apr 2018 13:42:21 +0200 Subject: armv8: allow halt on exception add command 'catch_exc' to halt a core on entering any of Secure EL1 or EL3 or Non-Secure EL1 or EL2. Change-Id: I0c68e247af68dd96616855a9bc1063c277d222e5 Signed-off-by: Matthias Welwarsky Reviewed-on: http://openocd.zylin.com/4479 Tested-by: jenkins Reviewed-by: Antonio Borneo Reviewed-by: Matthias Welwarsky --- src/target/armv8_dpm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/target/armv8_dpm.c') diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c index a5d7d11f..081eed21 100644 --- a/src/target/armv8_dpm.c +++ b/src/target/armv8_dpm.c @@ -1381,13 +1381,15 @@ void armv8_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr) case DSCRV8_ENTRY_BKPT: /* SW BKPT (?) */ case DSCRV8_ENTRY_RESET_CATCH: /* Reset catch */ case DSCRV8_ENTRY_OS_UNLOCK: /*OS unlock catch*/ - case DSCRV8_ENTRY_EXCEPTION_CATCH: /*exception catch*/ case DSCRV8_ENTRY_SW_ACCESS_DBG: /*SW access dbg register*/ target->debug_reason = DBG_REASON_BREAKPOINT; break; case DSCRV8_ENTRY_WATCHPOINT: /* asynch watchpoint */ target->debug_reason = DBG_REASON_WATCHPOINT; break; + case DSCRV8_ENTRY_EXCEPTION_CATCH: /*exception catch*/ + target->debug_reason = DBG_REASON_EXC_CATCH; + break; default: target->debug_reason = DBG_REASON_UNDEFINED; break; -- cgit v1.2.3-18-g5258