From 5d00fd9d1dc504335dd71e474a3d61dec7696c40 Mon Sep 17 00:00:00 2001 From: Matthias Welwarsky Date: Wed, 26 Oct 2016 17:32:43 +0200 Subject: aarch64: fix software breakpoints when in aarch32 state Use the correct opcode for Aarch32 state, both for the breakpoint instruction itself and the cache handling functions. Change-Id: I975fa67b1e577b54f5c672a01d516419c6a614b2 Signed-off-by: Matthias Welwarsky Reviewed-on: http://openocd.zylin.com/3981 Tested-by: jenkins Reviewed-by: Paul Fertser --- src/target/armv8_dpm.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'src/target/armv8_dpm.c') diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c index b4c14c2c..b06e456b 100644 --- a/src/target/armv8_dpm.c +++ b/src/target/armv8_dpm.c @@ -336,6 +336,9 @@ static int dpmv8_instr_write_data_r0_64(struct arm_dpm *dpm, struct armv8_common *armv8 = dpm->arm->arch_info; int retval; + if (dpm->arm->core_state != ARM_STATE_AARCH64) + return dpmv8_instr_write_data_r0(dpm, opcode, data); + /* transfer data from DCC to R0 */ retval = dpmv8_write_dcc_64(armv8, data); if (retval == ERROR_OK) @@ -413,6 +416,14 @@ static int dpmv8_instr_read_data_r0_64(struct arm_dpm *dpm, struct armv8_common *armv8 = dpm->arm->arch_info; int retval; + if (dpm->arm->core_state != ARM_STATE_AARCH64) { + uint32_t tmp; + retval = dpmv8_instr_read_data_r0(dpm, opcode, &tmp); + if (retval == ERROR_OK) + *data = tmp; + return retval; + } + /* the opcode, writing data to R0 */ retval = dpmv8_exec_opcode(dpm, opcode, &dpm->dscr); if (retval != ERROR_OK) -- cgit v1.2.3-18-g5258